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*******************************************************************************/
#ifndef __INCmvSata3RegsH
#define __INCmvSata3RegsH


#define SATA3_UNIT_REG_BASE(u)				MV_SATA3_REGS_OFFSET(u)
#define SATA3_PORT_REG_BASE(u, nPort)			(SATA3_UNIT_REG_BASE(u) + (nPort%2)*0x80)

#define SATA3_HBA_CAPABILITY_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x000)
#define SATA3_GLOBAL_HBA_CONTROL_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x004)
#define SATA3_INTERRUPT_STATUS_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x008)
#define SATA3_PORTS_IMPLEMENTED_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x00C)
#define AHCI_VERSION_REG(u)				(SATA3_UNIT_REG_BASE(u) + 0x010)
#define VENDOR_SPECIFIC_0_ADDR_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x0A0)
#define VENDOR_SPECIFIC_0_DATA_REG(u)			(SATA3_UNIT_REG_BASE(u) + 0x0A4)

#define SATA3_CMD_LIST_BASE_ADDR_LOW(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x100)
#define SATA3_CMD_LIST_BASE_ADDR_HIGH(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x104)
#define SATA3_RECEIVED_FIS_BASE_ADDR_LOW(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x108)
#define SATA3_RECEIVED_FIS_BASE_ADDR_HIGH(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x10C)
#define SATA3_PORT_INTERRUPT_STATUS_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x110)
#define SATA3_PORT_INTERRUPT_ENABLE_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x114)
#define SATA3_PORT_CMD_STATUS_REG(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x118)
#define SATA3_PORT_TASK_FILE_DATA_REG(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x120)
#define SATA3_PORT_SIGNATURE_REG(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x124)
#define SATA3_STATUS_REG(u, nPort)			(SATA3_PORT_REG_BASE(u, nPort) + 0x128)
#define SATA3_CONTROL_REG(u, nPort)			(SATA3_PORT_REG_BASE(u, nPort) + 0x12C)
#define SATA3_ERROR_REG(u, nPort)			(SATA3_PORT_REG_BASE(u, nPort) + 0x130)
#define SATA3_ACTIVE_REG(u, nPort)			(SATA3_PORT_REG_BASE(u, nPort) + 0x134)
#define SATA3_CMD_ISSUE_REG(u, nPort)			(SATA3_PORT_REG_BASE(u, nPort) + 0x138)
#define SATA3_PORT_NOTIFICATION_REG(u, nPort)		(SATA3_PORT_REG_BASE(u, nPort) + 0x13C)
#define SATA3_PORT_FIS_SWITCH_CNTRL_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x140)


#define SATA3_PORT_CMD_LBA_TABLE_BA_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x170)
#define VENDOR_SPEC_INTERRUPT_CNTRL_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x174)
#define SATA3_INDIRECT_PORT_PHY_ADD_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x178)
#define SATA3_INDIRECT_PORT_PHY_DATA_REG(u, nPort)	(SATA3_PORT_REG_BASE(u, nPort) + 0x17C)

#define SATA_GLOBAL_HBA_INTERRUPT_ENABLE_BIT	BIT1
#define SATA_GLOBAL_HBA_AHCI_ENABLE_BIT		BIT31

#define SATA_COMMAND_LIST_BASE_ADDR_ALIGN	0x400
#define SATA_RECEIVED_FIS_BASE_ADDR_ALIGN	0x1000
#define SATA_COMMAND_TABLE_DESC_ADDR_ALIGN	0x80
#define SATA_COMMAND_HEADER_ADDR_ALIGN		0x20

#define SATA_RECEIVED_FIS_LENGTH		0x1000
#define SATA_COMMAND_LIST_LENGTH		0x400

#define SATA_COMMAND_TABLE_CFIS_OFFSET		0x00
#define SATA_COMMAND_TABLE_CATAPI_OFFSET	0x60
#define SATA_COMMAND_TABLE_PRD_OFFSET		0x80
#define SATA_COMMAND_HEADER_ADDR_OFFSET		0x20

#define SATA_PORT_TASK_FILE_STATUS_BITS		0xff

#define MV_SATA3_MAX_ADDR_DECODE_WIN		4


#define MV_SATA3_WIN_CTRL_REG(dev, win)        (SATA3_UNIT_REG_BASE(dev) + 0x60 + ((win)<<4))
#define MV_SATA3_WIN_BASE_REG(dev, win)        (SATA3_UNIT_REG_BASE(dev)  + 0x64 + ((win)<<4))
#define MV_SATA3_WIN_SIZE_REG(dev, win)        (SATA3_UNIT_REG_BASE(dev)  + 0x68 + ((win)<<4))

#endif /*  __INCmvSata3RegsH */