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*******************************************************************************/

typedef enum mvNetComplexPhase {
	MV_NETC_FIRST_PHASE,
	MV_NETC_SECOND_PHASE,
} MV_NETC_PHASE_CFG;

/******************************************************************************/
/* Power managment clock control1 */
#define MV_NETCOMP_CLOCK_GATING					(MV_NET_COMPLEX_OFFSET)

#define NETC_CLOCK_GATING_SRAM_X2_OFFSET			8
#define NETC_CLOCK_GATING_SRAM_X2_MASK				(0x1 << NETC_CLOCK_GATING_SRAM_X2_OFFSET)

#define NETC_CLOCK_GATING_SRAM_OFFSET				9
#define NETC_CLOCK_GATING_SRAM_MASK				(0x1 << NETC_CLOCK_GATING_SRAM_OFFSET)

#define NETC_CLOCK_GATING_PPC_CMAC_OFFSET			10
#define NETC_CLOCK_GATING_PPC_CMAC_MASK				(0x1 << NETC_CLOCK_GATING_PPC_CMAC_OFFSET)

#define NETC_CLOCK_GATING_PPC_PP_OFFSET				11
#define NETC_CLOCK_GATING_PPC_PP_MASK				(0x1 << NETC_CLOCK_GATING_PPC_PP_OFFSET)

#define NETC_CLOCK_GATING_PPC_NSS_OFFSET			12
#define NETC_CLOCK_GATING_PPC_NSS_MASK				(0x1 << NETC_CLOCK_GATING_PPC_NSS_OFFSET)

#define NETC_CLOCK_GATING_CMAC_OFFSET				13
#define NETC_CLOCK_GATING_CMAC_MASK				(0x1 << NETC_CLOCK_GATING_CMAC_OFFSET)

#define NETC_CLOCK_GATING_NSS_OFFSET				14
#define NETC_CLOCK_GATING_NSS_MASK				(0x1 << NETC_CLOCK_GATING_NSS_OFFSET)

#define NETC_CLOCK_GATING_QM2_OFFSET				15
#define NETC_CLOCK_GATING_QM2_MASK				(0x1 << NETC_CLOCK_GATING_QM2_OFFSET)

#define NETC_CLOCK_GATING_QM1_X2_OFFSET				16
#define NETC_CLOCK_GATING_QM1_X2_MASK				(0x1 << NETC_CLOCK_GATING_QM1_X2_OFFSET)

#define NETC_CLOCK_GATING_QM1_OFFSET				17
#define NETC_CLOCK_GATING_QM1_MASK				(0x1 << NETC_CLOCK_GATING_QM1_OFFSET)

/* System Soft Reset 1 */
#define MV_NETCOMP_SYSTEM_SOFT_RESET			(MV_NET_COMPLEX_OFFSET + 0x8)

#define NETC_GOP_SOFT_RESET_OFFSET				6
#define NETC_GOP_SOFT_RESET_MASK				(0x1 << NETC_GOP_SOFT_RESET_OFFSET)

#define NETC_NSS_SRAM_LOAD_CONF_OFFSET				10
#define NETC_NSS_SRAM_LOAD_CONF_MASK				(0x1 << NETC_NSS_SRAM_LOAD_CONF_OFFSET)

#define NETC_NSS_PPC_LOAD_CONF_OFFSET				12
#define NETC_NSS_PPC_LOAD_CONF_MASK				(0x1 << NETC_NSS_PPC_LOAD_CONF_OFFSET)

#define NETC_NSS_MACS_LOAD_CONF_OFFSET				14
#define NETC_NSS_MACS_LOAD_CONF_MASK				(0x1 << NETC_NSS_MACS_LOAD_CONF_OFFSET)

#define NETC_NSS_QM1_LOAD_CONF_OFFSET				17
#define NETC_NSS_QM1_LOAD_CONF_MASK				(0x1 << NETC_NSS_QM1_LOAD_CONF_OFFSET)

/* Ports Control 0 */
#define MV_NETCOMP_PORTS_CONTROL_0			(MV_NET_COMPLEX_OFFSET + 0x10)

#define NETC_CLK_DIV_PHASE_OFFSET			31
#define NETC_CLK_DIV_PHASE_MASK				(0x1 << NETC_CLK_DIV_PHASE_OFFSET)

#define NETC_GIG_RX_DATA_SAMPLE_OFFSET			29
#define NETC_GIG_RX_DATA_SAMPLE_MASK			(0x1 << NETC_GIG_RX_DATA_SAMPLE_OFFSET)

#define NETC_BUS_WIDTH_SELECT_OFFSET			1
#define NETC_BUS_WIDTH_SELECT_MASK			(0x1 << NETC_BUS_WIDTH_SELECT_OFFSET)

/* Ports Control 1 */
#define MV_NETCOMP_PORTS_CONTROL_1			(MV_NET_COMPLEX_OFFSET + 0x14)

#define NETC_PORT_GIG_RF_RESET_OFFSET(port)		(28 + port)
#define NETC_PORT_GIG_RF_RESET_MASK(port)		(0x1 << NETC_PORT_GIG_RF_RESET_OFFSET(port))

#define NETC_PORTS_ACTIVE_OFFSET(port)			(0 + port)
#define NETC_PORTS_ACTIVE_MASK(port)			(0x1 << NETC_PORTS_ACTIVE_OFFSET(port))

/* Networking Complex Control 0 */
#define MV_NETCOMP_CONTROL_0				(MV_NET_COMPLEX_OFFSET + 0x20)

#define NETC_CTRL_ENA_XAUI_OFFSET			11
#define NETC_CTRL_ENA_XAUI_MASK				(0x1 << NETC_CTRL_ENA_XAUI_OFFSET)

#define NETC_CTRL_ENA_RXAUI_OFFSET			10
#define NETC_CTRL_ENA_RXAUI_MASK			(0x1 << NETC_CTRL_ENA_RXAUI_OFFSET)

#define NETC_GBE_PORT1_MODE_OFFSET			1
#define NETC_GBE_PORT1_MODE_MASK			(0x1 << NETC_GBE_PORT1_MODE_OFFSET)

/* Networking Complex AMB Access Control 0 */
#define MV_NETCOMP_AMB_ACCESS_CTRL_0			(MV_NET_COMPLEX_OFFSET + 0xC0)

#define NETC_AMB_ACCESS_CTRL_OFFSET			24
#define NETC_AMB_ACCESS_CTRL_MASK			(0xff << NETC_AMB_ACCESS_CTRL_OFFSET)

/* QSGMII Control 1 */
#define MV_NETCOMP_QSGMII_CTRL_1			(MV_IP_CONFIG_REGS_OFFSET + 0x94)

#define NETC_QSGMII_CTRL_RSTN_OFFSET			31
#define NETC_QSGMII_CTRL_RSTN_MASK			(0x1 << NETC_QSGMII_CTRL_RSTN_OFFSET)

#define NETC_QSGMII_CTRL_V3ACTIVE_OFFSET		29
#define NETC_QSGMII_CTRL_V3ACTIVE_MASK			(0x1 << NETC_QSGMII_CTRL_V3ACTIVE_OFFSET)

#define NETC_QSGMII_CTRL_VERSION_OFFSET			28
#define NETC_QSGMII_CTRL_VERSION_MASK			(0x1 << NETC_QSGMII_CTRL_VERSION_OFFSET)

/* Function Enable Control 1 */
#define MV_NETCOMP_FUNCTION_ENABLE_CTRL_1			(MV_MISC_REGS_OFFSET + 0x88)

#define NETC_PACKET_PROCESS_OFFSET			1
#define NETC_PACKET_PROCESS_MASK			(0x1 << NETC_PACKET_PROCESS_OFFSET)

/* ComPhy Selector */
#define COMMON_PHYS_SELECTORS_REG			(MV_COMMON_PHY_REGS_OFFSET + 0xFC)

#define COMMON_PHYS_SELECTOR_LANE_OFFSET(lane)		(4 * lane)
#define COMMON_PHYS_SELECTOR_LANE_MASK(lane)		(0xF << COMMON_PHYS_SELECTOR_LANE_OFFSET(lane))

MV_STATUS mvNetComplexInit(MV_U32 netCompConfig, MV_NETC_PHASE_CFG phase);
MV_VOID mvNetComplexNssSelect(MV_U32 val);