fix: thermal: a38x, a39x: change temperature band gap circuit curve
38x default used curve introduces temperature read to be
incorrectly high.
Change-Id: I62f8ab7a7fa74a1bf54aebc50e2642ad5b680321
Signed-off-by: Bassel Saba <basselsa@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24899
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
index 64ab410..c454f11 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
@@ -2225,8 +2225,14 @@
MV_32 reg = 0;
/* Initiates TSEN hardware reset once */
- if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0)
+ if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) {
MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
+ /* set TSEN TC Trim value */
+ reg = MV_REG_READ(TSEN_CONTROL_LSB_REG);
+ reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK;
+ reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET;
+ MV_REG_WRITE(TSEN_CONTROL_LSB_REG, reg);
+ }
mvOsDelay(10);
/* Check if the readout field is valid */
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
index ccccf95..140b24c 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
@@ -171,6 +171,8 @@
/* Termal Sensor Registers */
#define TSEN_CONTROL_LSB_REG 0xE4070
+#define TSEN_CONTROL_LSB_TC_TRIM_OFFSET 0
+#define TSEN_CONTROL_LSB_TC_TRIM_MASK (0x7 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET)
#define TSEN_CONTROL_MSB_REG 0xE4074
#define TSEN_CONTROL_MSB_RST_OFFSET 8
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
index e55296b..c60da34 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
@@ -39,6 +39,8 @@
/* Termal Sensor Registers */
#define TSEN_CONTROL_LSB_REG 0xE4070
+#define TSEN_CONTROL_LSB_TC_TRIM_OFFSET 0
+#define TSEN_CONTROL_LSB_TC_TRIM_MASK (0x7 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET)
#define TSEN_CONTROL_MSB_REG 0xE4074
#define TSEN_CONTROL_MSB_RST_OFFSET 8
#define TSEN_CONTROL_MSB_RST_MASK (0x1 << TSEN_CONTROL_MSB_RST_OFFSET)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 00e7946..6dc8e24 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -314,8 +314,14 @@
GT_32 reg = 0;
/* Initiates TSEN hardware reset once */
- if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0)
+ if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) {
MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
+ /* set TSEN TC Trim value */
+ reg = MV_REG_READ(TSEN_CONTROL_LSB_REG);
+ reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK;
+ reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET;
+ MV_REG_WRITE(TSEN_CONTROL_LSB_REG, reg);
+ }
mvOsDelay(10);
/* Check if the readout field is valid */
