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#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

typedef enum _boardMacSpeed {
	BOARD_MAC_SPEED_10M,
	BOARD_MAC_SPEED_100M,
	BOARD_MAC_SPEED_1000M,
	BOARD_MAC_SPEED_2000M,
	BOARD_MAC_SPEED_AUTO,
	BOARD_MAC_UNCONNECTED
} MV_BOARD_MAC_SPEED;

typedef struct _boardMacInfo {
	MV_BOARD_MAC_SPEED boardMacSpeed;
	MV_32 boardEthSmiAddr;
	MV_32 boardEthSmiAddr0;
	MV_BOOL boardMacEnabled;
} MV_BOARD_MAC_INFO;

enum {
	MV_PORT_TYPE_SGMII,
	MV_PORT_TYPE_QSGMII,
	MV_PORT_TYPE_RGMII,
	MV_PORT_TYPE_UNKNOWN = -1,
};

/* {{ConfigID,		     twsi-ID, Offset,	 ID,	isActiveForBoard[]}} */
#define MV_MODULE_INFO { \
{ MV_MODULE_MII,		0x1,	0,	 0x4,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_SLIC_TDM_DEVICE,	0x0,	0,	 0x1,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_I2S_DEVICE,		0x1,	0,	 0x3,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_SPDIF_DEVICE,	0x1,	0,	 0x2,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_NOR,		0x4,	0,	 0xF,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_NAND,		0x4,	0,	 0x1,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_SDIO,		0x4,	0,	 0x2,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_SGMII,		0x2,	0,	 0xF,	{ 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_DB381_SGMII,	0x0,	0,	 0x2,	{ 0, 0, 0, 0, 0, 1, 0} }, \
{ MV_MODULE_SWITCH,		0x5,	0,	 0xE,	{ 0, 1, 0, 0, 0, 0, 0} }, \
};

typedef enum _mvSatRTypeID {
/*  "Bios" Device  */
	MV_SATR_CPU_DDR_L2_FREQ,
	MV_SATR_CORE_CLK_SELECT,
	MV_SATR_CPU1_ENABLE,
	MV_SATR_SSCG_DISABLE,
	/*  SW parameters: */
	MV_SATR_DDR4_SELECT,
	MV_SATR_DDR_BUS_WIDTH,
	MV_SATR_DDR_ECC_ENABLE,
	MV_SATR_DDR_ECC_PUP_SEL,
	MV_SATR_SGMII_SPEED,
	MV_SATR_BOOT_DEVICE,
	MV_SATR_BOOT2_DEVICE,
	MV_SATR_BOARD_ID,
	MV_SATR_BOARD_ECO_VERSION,
	MV_SATR_DB_USB3_PORT0,
	MV_SATR_DB_USB3_PORT1,
	MV_SATR_RD_SERDES4_CFG,
	MV_SATR_GP_SERDES5_CFG,
	MV_SATR_DB_SERDES1_CFG,
	MV_SATR_DB_SERDES2_CFG,
	MV_SATR_SGMII_MODE,
	MV_SATR_DEVICE_ID,
	MV_SATR_DEVICE_ID2,
	MV_SATR_GP_SERDES1_CFG,
	MV_SATR_GP_SERDES2_CFG,
	MV_SATR_FULL_FLAVOR,
	MV_SATR_TDM_CONNECTED,
	MV_SATR_TDM_PLACE_HOLDER,
	MV_SATR_BOARD_SPEED,
	MV_SATR_MAX_OPTION,
} MV_SATR_TYPE_ID;

/*						bit    TWSI           Reg	board	*/
/*   name		SATR-ID			Mask  offset  devID   num	active	*/
#define MV_SAR_INFO { \
{"freq",	MV_SATR_CPU_DDR_L2_FREQ,	0x1F,	0,	1,	0,	{1, 1, 1, 1, 1, 0, 1}, SATR_SWAP_BIT},\
{"coreclock",	MV_SATR_CORE_CLK_SELECT,	0x04,	2,	3,	0,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"cpusnum",	MV_SATR_CPU1_ENABLE,		0x10,	4,	3,	0,	{0, 0, 0, 0, 0, 1, 0}, 0},\
{"sscg",	MV_SATR_SSCG_DISABLE,		0x08,	3,	3,	0,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"ddr4select",	MV_SATR_DDR4_SELECT,		0x20,	5,	4,	1,	{0, 1, 0, 0, 0, 0, 0}, SATR_READ_ONLY},\
{"ddrbuswidth",	MV_SATR_DDR_BUS_WIDTH,		0x08,	3,	0,	0,	{1, 1, 1, 1, 1, 0, 1}, 0},\
{"ddreccenable",	MV_SATR_DDR_ECC_ENABLE,	0x10,	4,	0,	0,	{1, 1, 1, 1, 1, 1, 1}, 0},\
{"ddreccpupselect",	MV_SATR_DDR_ECC_PUP_SEL, 0x20,	5,	0,	0,	{0, 1, 0, 0, 0, 0, 1}, 0},\
{"sgmiispeed", MV_SATR_SGMII_SPEED,		0x40,	6,	0,	0,	{1, 1, 1, 1, 1, 1, 0}, 0},\
{"bootsrc",	MV_SATR_BOOT_DEVICE,		0x3,	0,	3,	0,	{0, 1, 0, 0, 0, 1, 0}, SATR_SWAP_BIT},\
{"boarsrc2",	MV_SATR_BOOT2_DEVICE,		0x1E,	1,	2,	0,	{0, 1, 0, 0, 0, 1, 0}, SATR_SWAP_BIT},\
{"boardid",	MV_SATR_BOARD_ID,		0x7,	0,	0,	0,	{1, 1, 1, 1, 1, 1, 1}, 0},\
{"ecoversion",	MV_SATR_BOARD_ECO_VERSION,	0xff,	0,	0,	1,	{0, 1, 0, 0, 0, 0, 0}, SATR_READ_ONLY},\
{"usb3port0",	MV_SATR_DB_USB3_PORT0,		0x1,	0,	0,	2,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"usb3port1",	MV_SATR_DB_USB3_PORT1,		0x2,	1,	0,	2,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"rdserdes4",	MV_SATR_RD_SERDES4_CFG,		0x4,	2,	1,	1,	{1, 0, 1, 0, 0, 0, 0}, 0},\
{"gpserdes5",	MV_SATR_GP_SERDES5_CFG,		0x4,	2,	1,	1,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{"dbserdes1",	MV_SATR_DB_SERDES1_CFG,		0x7,	0,	0,	1,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"dbserdes2",	MV_SATR_DB_SERDES2_CFG,		0x38,	3,	0,	1,	{0, 1, 0, 0, 0, 1, 0}, 0},\
{"gpserdes1",	MV_SATR_GP_SERDES1_CFG,		0x4,	2,	0,	2,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{"gpserdes2",	MV_SATR_GP_SERDES2_CFG,		0x8,	3,	0,	2,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{"sgmiimode",	MV_SATR_SGMII_MODE,		0x40,	6,	0,	1,	{0, 1, 0, 0, 1, 1, 1}, 0},\
{"devid",	MV_SATR_DEVICE_ID,		0x1,	0,	2,	0,	{0, 1, 0, 0, 0, 0, 0}, 0},\
{"devid2",	MV_SATR_DEVICE_ID2,		0x10,	4,	3,	0,	{0, 1, 0, 0, 0, 0, 0}, 0},\
{"flavor",	MV_SATR_FULL_FLAVOR,		0x10,	4,	0,	2,	{0, 1, 0, 1, 1, 1, 0}, 0},\
{"tdm",		MV_SATR_TDM_CONNECTED,		0x20,	5,	0,	2,	{0, 1, 0, 0, 0, 0, 0}, 0},\
{"tdmplaceholder",	MV_SATR_TDM_PLACE_HOLDER,	0x40,	6,	0,	2,	{0, 0, 0, 0, 0, 0, 0}, 0},\
{"boardspeed",	MV_SATR_BOARD_SPEED,		0x3,	0,	0,	3,	{0, 1, 0, 1, 1, 0, 1}, SATR_READ_ONLY},\
{"max_option",	MV_SATR_MAX_OPTION,		0x0,	0,	0,	0,	{0, 0, 0, 0, 0, 0, 0}, 0},\
};
/* tdm place holder is used for future support for multiple tdm devices */

/* extra SAR table, for different board implementations:
 * in case a field is used on 2 boards with different i2c mapping */
#define MV_SAR_INFO2 { \
{"freq",	MV_SATR_CPU_DDR_L2_FREQ,	0x1E,	1,	1,	0,	{0, 0, 0, 0, 0, 1, 0},  SATR_SWAP_BIT},\
{"coreclock",	MV_SATR_CORE_CLK_SELECT,	0x08,	3,	2,	0,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{"sscg",	MV_SATR_SSCG_DISABLE,		0x10,	4,	2,	0,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{"devid",	MV_SATR_DEVICE_ID,		0x3,	0,	2,	0,	{0, 0, 0, 0, 1, 0, 0}, 0},\
{ "max_option",	MV_SATR_MAX_OPTION,		0x0,	0,	0,	0,	{0, 0, 0, 0, 0, 0, 0}, 0},\
};

#define MV_SATR_BOOT2_VALUE_MASK	0xF
#define MV_SATR_BOOT2_VALUE_OFFSET	2
#define MV_SATR_DEVICE_ID2_VALUE_MASK	1
#define MV_SATR_DEVICE_ID2_VALUE_OFFSET	1

#ifdef CONFIG_CMD_BOARDCFG
#define MV_BOARD_CONFIG_MAX_BYTE_COUNT	8
#define MV_BOARD_CONFIG_DEFAULT_VALUE	{0x1921d0a1, 0x4 }

typedef enum _mvConfigTypeID {
	MV_CONFIG_EXAMPLE0,
	MV_CONFIG_TYPE_MAX_OPTION,
	MV_CONFIG_TYPE_CMD_DUMP_ALL,
	MV_CONFIG_TYPE_CMD_SET_DEFAULT
} MV_CONFIG_TYPE_ID;

#define MV_EEPROM_CONFIG_INFO { \
{ MV_CONFIG_EXAMPLE0,	0x7,		0,	0,	{1, 1, 1, 1} }, \
};

#define MV_BOARD_CONFIG_CMD_STR "example0\n\n"
#define MV_BOARD_CONFIG_CMD_MAX_OPTS 5

/*MV_CMD_TYPE_ID,		command name,		Name,			numOfValues,	Possible Values */
#define MV_BOARD_CONFIG_CMD_INFO {\
{MV_CONFIG_EXAMPLE0,	"example0",	"Example #0",	5,					\
	{"Option0", "Option1", "Option2", "Option3", "Option4"} },				\
};

#endif /* CONFIG_CMD_BOARDCFG */

#ifdef __cplusplus
}
#endif  /* __cplusplus */