)]}' { "commit": "a75a5c01285b16422094739d9f4934e868058761", "tree": "10514412c8a4d0adf6b8ea9d36a83cbde846325b", "parents": [ "0476bf3eb06a58b764a0c58fd6e74ec4e23e4ad5" ], "author": { "name": "hayim", "email": "hayim@marvell.com", "time": "Tue Oct 20 10:50:57 2015 +0300" }, "committer": { "name": "Greg Poist", "email": "poist@google.com", "time": "Thu Mar 24 11:59:54 2016 -0700" }, "message": "ddr3libv2: fix: increas ODPG polling (again) x10 for DDR4\n\n the reason for the delay in the machine is because there\n is a jitter and it causes the machine to scan specific\n areas (which have jitter) man times\n\nChange-Id: I6de1d1bd02d58192ada84e976df78265559809a8\nSigned-off-by: hayim \u003chayim@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24076\nReviewed-on: http://vgitil04.il.marvell.com:8080/24177\nReviewed-by: Omri Itach \u003comrii@marvell.com\u003e\nTested-by: Omri Itach \u003comrii@marvell.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "8d8045aaaa45487440d2186640944c4fcb783bbd", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c", "new_id": "b51d5c0efc4ffe68004052fe44b46aa1a36a0451", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c" } ] }