)]}' { "commit": "a6a0ddb142dda6a9d6835aafde9ab20cc7bd48f5", "tree": "0609bda3d45162339a12319a9eb09b622c7a296f", "parents": [ "51b84fdaa0baa94760b896e5a4785012093ca7ba" ], "author": { "name": "Igor Petrik", "email": "igorp@marvell.com", "time": "Sun May 10 13:22:12 2015 +0300" }, "committer": { "name": "Greg Poist", "email": "poist@google.com", "time": "Thu Mar 24 11:59:54 2016 -0700" }, "message": "ddr4: Added DDR4 sublib compilation\n\n\told DDR4 lib \u003d new DDR4 lib + new DDR4 sublib.\n\t\u0027-m 4\u0027 will build U-Boot with existing training libs\n\t\u0027-m 4 -d 2\u0027 will rebuild DDR3 source and use existing DDR4 sublib\n\t\u0027-m 4 -d 4\u0027 will rebuild both DDR3 and DDR4 source.\n\tLib separation will allow to user rebuild open part(common with DDR3) of DDR4 training flow.\n\tnew lib will be named ddr4_training_\u003cSoC\u003esub.lib and placed in same place\n\tas existing ddr4_training_\u003cSoC\u003e.lib. Existing DDR4 lib will consist only ddr3libv2 code\n\nChange-Id: I8b4887713d655ed3e49b980ebc19fb767cf81c3c\nSigned-off-by: Igor Petrik \u003cigorp@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/19106\nReviewed-by: Omri Itach \u003comrii@marvell.com\u003e\nTested-by: Omri Itach \u003comrii@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24123\nTested-by: Star_Automation \u003cstar@marvell.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "11de2662a3e30d5c2f5861eff1b83022396cbaf3", "old_mode": 33261, "old_path": "build.pl", "new_id": "01f97bd93a9312aca0cb5ed2f708663358890e09", "new_mode": 33261, "new_path": "build.pl" }, { "type": "modify", "old_id": "2643fe25bdd5d7febaf6fc7158984a5d4acfc406", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/Makefile", "new_id": "7c3cfacaf68bb60936a7baeb8e85dbc2c9fa8aa5", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/Makefile" }, { "type": "modify", "old_id": "0dc79160433ad16790a006ab1781ac22dc119c08", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile", "new_id": "da5af0aa0caff42f91efd83ae41461838002fb3b", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile" }, { "type": "modify", "old_id": "0241646a2fed849dc044cef9de09a00e702141d5", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c", "new_id": "237ba019f1c356a923566c8e506b69ef42f1425c", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c" }, { "type": "modify", "old_id": "eae2829aac07a8801d32667b93d09d83a0fe432b", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a38x.lib", "new_id": "170b95bf1039a79cd9a9f1c1cbcc555dc09c0e5f", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a38x.lib" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "e02c0870e5f733764dba5eb638e15339a7ad9842", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a38xsub.lib" }, { "type": "modify", "old_id": "30f684630881f4dda8e98bd381b719b8007cc43e", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a39x.lib", "new_id": "d701989588196b395febe07ef3a34f305f15a56b", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a39x.lib" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "db2fef2a8e49fc3734f644c93b78b46499f79d23", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/lib/ddr4_training_a39xsub.lib" } ] }