/*
 * Copyright (c) 2000,2001 Epson Research and Development, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Generic Header information generated by 13704CFG.EXE (Build 10)
 * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
 */

static S1D_REGS regs_13705_320_240_8bpp[] =
{
	{ 0x00,             0x00 },       /* Revision Code Register */
	{ 0x01,             0x23 },       /* Mode Register 0 Register */
	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
	{ 0x0B,             0x00 },       /* MOD Rate Register */
	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
	{ 0x0E,             0x00 },       /* Not Used */
	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
	{ 0x11,             0x00 },       /* Not Used */
	{ 0x12,             0x00 },       /* Memory Address Offset Register */
	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
	{ 0x1A,             0x00 },       /* Scratch Pad Register */
	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
	{ 0x1C,             0xFF },       /* Line Byte Count Register */
	{ 0x1D,             0x00 },       /* Not Used */
	{ 0x1E,             0x00 },       /* Not Used */
	{ 0x1F,             0x00 },       /* Not Used */
};