bc2: set DFX window settings as a part of U-Boot windows management
- Added early init routine to set hardcoded DFX window configuration
(DFX registers are needed in early stage of U-Boot boot sequence)
- Added DFX window configuration settings to U-Boot windows table
- Removed mvBoardDfxConfig() routine
Change-Id: If626a60ed79c4a88c5f6cefb0f21aef56c5ad77f
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/5309
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Star_Automation <star@marvell.com>
diff --git a/board/mv_ebu/common/USP/mv_main.c b/board/mv_ebu/common/USP/mv_main.c
index ea2a881..120d3de 100755
--- a/board/mv_ebu/common/USP/mv_main.c
+++ b/board/mv_ebu/common/USP/mv_main.c
@@ -687,6 +687,17 @@
display_dram_config(1);
return 0;
}
+
+int board_early_init_f (void)
+{
+ /* Open window to DFX registers
+ * DFX registers are needed in early stage of U-Boot boot sequence
+ * This is done here once, before U-Boot sets its window configuration*/
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(1), 0x000f0081);
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(1), DFX_REGS_BASE);
+ return 0;
+}
+
int misc_init_r (void)
{
char *env;
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index b5c7e25..695c1e3 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -150,23 +150,6 @@
}
-MV_U32 mvBoardDfxConfig(MV_VOID)
-{
- MV_U32 I2C_conf;
-
- /* set acess to DFX */
- I2C_conf = MV_REG_READ(I2C_CONFIC_DEBUG_REG);
- I2C_conf &= ICDR_UINIT_ID_MASK;
- I2C_conf |= 8; /* acess to DFX */
- MV_REG_WRITE(I2C_CONFIC_DEBUG_REG,I2C_conf);
-
- /* open windows to DFX */
- MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(1), 0x000f0081);
- MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(1), 0xF5000000);
-
- return 0;
-}
-
/*******************************************************************************
* mvBoardModelGet - Get Board model
*
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
index 5521ebd..0fa4e51 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
@@ -253,7 +253,6 @@
} MV_BOARD_INFO;
MV_VOID mvBoardEnvInit(MV_VOID);
-MV_U32 mvBoardDfxConfig(MV_VOID);
MV_U16 mvBoardModelGet(MV_VOID);
MV_U16 mvBoardRevGet(MV_VOID);
MV_STATUS mvBoardNameGet(char *pNameBuff);
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index eb39ae4..cda0fe9 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -276,12 +276,13 @@
/* This enumerator defines the Marvell controller target ID (see Address map) */
typedef enum _mvTargetId {
- DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */
- DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */
- PEX0_TARGET_ID = 4, /* Port 4 -> PCI Express 0 */
- CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */
- PNC_BM_TARGET_ID = 12, /* Port 12 -> PNC + BM Unit */
- MAX_TARGETS_ID
+ DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */
+ DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */
+ PEX0_TARGET_ID = 4, /* Port 4 -> PCI Express 0 */
+ DFX_TARGET_ID = 8, /* Port 8 -> DFX Server */
+ CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */
+ PNC_BM_TARGET_ID = 12, /* Port 12 -> PNC + BM Unit */
+ MAX_TARGETS_ID
} MV_TARGET_ID;
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
index 97e4add..0e1276a 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -312,7 +312,7 @@
{0xE8, PEX0_TARGET_ID }, /* 8 PEX0_LANE0_MEM */ \
{0xE0, PEX0_TARGET_ID }, /* 9 PEX0_LANE0_IO */ \
{0xFF, 0xFF }, /* 10 INTER_REGS */ \
- {0x00, 8 }, /* 11 DFX_INTER_REGS */ \
+ {0x00, DFX_TARGET_ID }, /* 11 DFX_INTER_REGS */ \
{0x01, DEV_TARGET_ID }, /* 12 DMA_UART */ \
{0x1E, DEV_TARGET_ID }, /* 13 SPI_CS0 */ \
{0x5E, DEV_TARGET_ID }, /* 14 SPI_CS1 */ \
diff --git a/board/mv_ebu/msys/mvSysHwConfig.h b/board/mv_ebu/msys/mvSysHwConfig.h
index 28b04a1..b8a3aae 100644
--- a/board/mv_ebu/msys/mvSysHwConfig.h
+++ b/board/mv_ebu/msys/mvSysHwConfig.h
@@ -112,21 +112,18 @@
#define PEX0_IO_SIZE _1M
/***************** DFX base address ***********************/
#define DFX_REGS_BASE 0xF5000000
+#define DFX_REGS_SIZE _1M
#define MV_DFX_REG_READ(offset) \
- mvBoardDfxConfig() | \
(MV_MEMIO_LE32_READ(DFX_REGS_BASE | (offset))) \
-
#define MV_DFX_REG_WRITE(offset, val) \
{ \
- mvBoardDfxConfig(); \
MV_MEMIO_LE32_WRITE((DFX_REGS_BASE | (offset)), (val)); \
}
#define MV_DFX_REG_BIT_SET(offset, bitMask) \
{ \
- mvBoardDfxConfig(); \
(MV_MEMIO32_WRITE((DFX_REGS_BASE | (offset)), \
(MV_MEMIO32_READ(DFX_REGS_BASE | (offset)) | \
MV_32BIT_LE_FAST(bitMask)))); \
@@ -134,7 +131,6 @@
#define MV_DFX_REG_BIT_RESET(offset,bitMask) \
{ \
- mvBoardDfxConfig(); \
(MV_MEMIO32_WRITE((DFX_REGS_BASE | (offset)), \
(MV_MEMIO32_READ(DFX_REGS_BASE | (offset)) & \
MV_32BIT_LE_FAST(~bitMask)))); \
@@ -256,6 +252,7 @@
{ { PEX0_MEM_BASE, 0, PEX0_MEM_SIZE }, 0, EN }, /* PEX0_MEM */ \
{ { PEX0_IO_BASE, 0, PEX0_IO_SIZE }, TBL_UNUSED, DIS }, /* PEX0_IO */ \
{ { INTER_REGS_BASE, 0, INTER_REGS_SIZE }, MV_AHB_TO_MBUS_INTREG_WIN, EN }, /* INTER_REGS */ \
+ { { DFX_REGS_BASE, 0, DFX_REGS_SIZE }, 1, EN }, /* DFX_REGS */ \
{ { TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS }, /* DMA_UART */ \
{ { SPI_CS_BASE, 0, SPI_CS_SIZE }, 8, EN }, /* SPI_CS0 */ \
{ { TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS }, /* SPI_CS1 */ \
diff --git a/include/configs/msys.h b/include/configs/msys.h
index ed083d5..e14a53e 100644
--- a/include/configs/msys.h
+++ b/include/configs/msys.h
@@ -77,6 +77,7 @@
#define MV_DDR_64BIT
#define MV_MEM_FASTPATH
#define MV_BOOTROM
+#define CONFIG_BOARD_EARLY_INIT_F
/*********/
/* Debug */
