diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 9f04bc0..91011fe 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -48,7 +48,7 @@
 extern GT_U32 mode2T;
 
 GT_U32  pipeMulticastMask;
-
+GT_BOOL ddr3AsyncModeAtTF = GT_FALSE;
 #define A38X_NUM_BYTES                  (3)
 #define A38X_NUMBER_OF_INTERFACES		5
 
@@ -749,10 +749,17 @@
 		case 0x12:
 		    *freq = DDR_FREQ_900;
 		    break;
+#ifdef CONFIG_DDR3
+		case 0x13:
+		    *freq = DDR_FREQ_933;
+			ddr3AsyncModeAtTF = GT_TRUE;
+		    break;
+#else
 		case 0x13:
 		    *freq = DDR_FREQ_1000;
 			DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 1000Mhz configured(%d)\n", uiReg));
 		    break;
+#endif
 		default:
 		    *freq = 0;
 			return MV_NOT_SUPPORTED;
@@ -894,36 +901,53 @@
 	else{
     	divider = A38xVcoFreqPerSarRefClk40Mhz[sarVal]/freqVal[frequency];
 	}
-	/*Set Sync mode*/
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x20220, 0x0, 0x1000));
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE42F4, 0x0, 0x200));
 
-	/* cpupll_clkdiv_reset_mask */ 
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0x1f, 0xFF));
+	if( (ddr3AsyncModeAtTF == GT_TRUE) && (freqVal[frequency] > 400) ){
 
-	/* cpupll_clkdiv_reload_smooth */ 
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, (0x2 << 8), (0xFF << 8)));
+		/*Set Async Mode*/
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x20220, 0x1000, 0x1000));
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE42F4, 0x200, 0x200));
 
-	/* cpupll_clkdiv_relax_en */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, (0x2 << 24), (0xFF << 24)));
+		/*Wait for Asunc mode setup*/
+		mvOsDelay(5);
 
-	/* write the divider */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4268, (divider << 8), (0x3F << 8)));
+		/*Set KNL values*/
+		if( frequency == DDR_FREQ_933){
+			CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE42F0, 0x804A002, 0xFFFFFFFF));
+		}
+	}
+	else{
+		/*Set Sync mode*/
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x20220, 0x0, 0x1000));
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE42F4, 0x0, 0x200));
 
-	/* set cpupll_clkdiv_reload_ratio */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, (1 << 8), (1 << 8)));
+		/* cpupll_clkdiv_reset_mask */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0x1f, 0xFF));
 
-	/* undet cpupll_clkdiv_reload_ratio */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0, (1 << 8)));
+		/* cpupll_clkdiv_reload_smooth */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, (0x2 << 8), (0xFF << 8)));
 
-	/* clear cpupll_clkdiv_reload_force */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, 0, (0xFF << 8)));
+		/* cpupll_clkdiv_relax_en */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, (0x2 << 24), (0xFF << 24)));
 
-	/* clear cpupll_clkdiv_relax_en */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, 0, (0xFF << 24)));
+		/* write the divider */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4268, (divider << 8), (0x3F << 8)));
 
-	/* clear cpupll_clkdiv_reset_mask */
-	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0, 0xFF));
+		/* set cpupll_clkdiv_reload_ratio */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, (1 << 8), (1 << 8)));
+
+		/* undet cpupll_clkdiv_reload_ratio */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0, (1 << 8)));
+
+		/* clear cpupll_clkdiv_reload_force */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, 0, (0xFF << 8)));
+
+		/* clear cpupll_clkdiv_relax_en */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4260, 0, (0xFF << 24)));
+
+		/* clear cpupll_clkdiv_reset_mask */
+		CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE4264, 0, 0xFF));
+	}
 
 	/* Dunit training clock + 1:1/2:1 mode */
 	CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x18488, ((ddr3TipClockMode(frequency) & 0x1) << 16), (1 << 16)));