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*******************************************************************************/
#ifndef _DDR_TOPOLOGY_CONFIG_H
#define _DDR_TOPOLOGY_CONFIG_H

#include "mvDdr3TrainingIpDef.h"

#ifdef CONFIG_DDR3
#include "mvDdr3TopologyDef.h"
#elif defined(CONFIG_DDR4)
#include "mvDdr4TopologyDef.h"
#else
# error "CONFIG_DDR3 or CONFIG_DDR4 must be defined !!!"
#endif

/************************* Definitions *******************************************/

#if defined(CONFIG_BOBCAT2) || (defined(CHX_FAMILY) || defined(EXMXPM_FAMILY))
#define MAX_INTERFACE_NUM  		(5)
#else
#define MAX_INTERFACE_NUM  		(1)
#endif

#define MAX_BUS_NUM        		(5)

#define SDRAM_CS_SIZE				0xFFFFFFF
#define MV_PARAMS_UNDEFINED 		0xFFFFFFFF
/************************* Topology *******************************************/

/* bus width in bits */
typedef enum
{
   BUS_WIDTH_4,
   BUS_WIDTH_8,
   BUS_WIDTH_16,
   BUS_WIDTH_32

} MV_HWS_BUS_WIDTH;

typedef enum
{
   MV_HWS_TEMP_LOW,
   MV_HWS_TEMP_NORMAL,
   MV_HWS_TEMP_HIGH

}MV_HWS_TEMPERTURE;

typedef enum 
{
   MEM_512M,
   MEM_1G,
   MEM_2G,
   MEM_4G,
   MEM_8G,
   MEM_SIZE_LAST
}MV_HWS_MEM_SIZE;

typedef struct 
{
   /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
   GT_U8      csBitmask;

   /* mirror enable/disable (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)*/
   GT_BOOL      mirrorEnableBitmask;

   /* DQS Swap (polarity) - true if enable*/
   GT_BOOL      isDqsSwap;

   /* CK swap (polarity) - true if enable*/
   GT_BOOL      isCkSwap;

} BusParams;

typedef struct 
{
   /* bus configuration */
   BusParams   asBusParams[MAX_BUS_NUM];
      
   /* Speed Bin Table*/
   MV_HWS_SPEED_BIN      speedBinIndex;

   /* bus width of memory */
   MV_HWS_BUS_WIDTH   busWidth;

   /* Bus memory size (MBit) */
   MV_HWS_MEM_SIZE      memorySize;

   /* The DDR frequency for each interfaces */
   MV_HWS_DDR_FREQ      memoryFreq;

   /* delay CAS Write Latency - 0 for using default value (jedec suggested) */
   GT_U8      casWL;

   /* delay CAS Latency - 0 for using default value (jedec suggested) */
   GT_U8      casL;

   /* operation temperature */
   MV_HWS_TEMPERTURE   interfaceTemp;

} InterfaceParams;

/***********************************/

typedef struct
{
    /* Number of interfaces (default is 12)*/
    GT_U8              interfaceActiveMask;

   /* Controller configuration per interface */
   InterfaceParams      interfaceParams[MAX_INTERFACE_NUM];

   /* Bit mask for active buses*/
   GT_U8               activeBusMask;

} MV_HWS_TOPOLOGY_MAP;

/***********************************
DDR3 training global configuration parameters*/
typedef struct
{
	GT_U32	ckDelay;
	GT_U32	PhyReg3Val;

	GT_U32 gZpriData;
	GT_U32 gZnriData;
	GT_U32 gZpriCtrl;
	GT_U32 gZnriCtrl;
	GT_U32 gZpodtData;
	GT_U32 gZnodtData;
	GT_U32 gZpodtCtrl;
	GT_U32 gZnodtCtrl;
	GT_U32 gDic;
	GT_U32 uiODTConfig;
	GT_U32 gRttNom;
	GT_U32 gRttWR;
} GT_TUNE_TRAINING_PARAMS;

#endif /* _DDR_TOPOLOGY_CONFIG_H */