diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
index fe28f3e..71d24ca 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
@@ -83,6 +83,7 @@
     MV_ATTR_DELAY_ENABLE,
     MV_ATTR_CK_DELAY,
     MV_ATTR_CA_DELAY,
+    MV_ATTR_INTERLEAVE_WA,
     MV_ATTR_LAST
 } MV_DDR_DEV_ATTRIBUTE;
 
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 9d28f2c..592c691 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -586,6 +586,7 @@
 
 			/* Intrleave first command pre-charge enable (TBD) */
             CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, SDRAM_OPEN_PAGE_CONTROL_REG, (1 << 10), (1 << 10)));
+            CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, SDRAM_OPEN_PAGE_CONTROL_REG, 0x0, 0x3C0));
 
             /* PHY configuration*/
             /* Postamble Length = 1.5cc, Addresscntl to clk skew \BD, Preamble length normal, parralal ADLL enable*/
@@ -1781,9 +1782,16 @@
 			uiT2t = (csNum == 1) ? 0 : 1;
 		}
 
-		/*If configured 1:1 Ratio, use 1T mode*/
-		if(configFuncInfo[devNum].tipGetClockRatio(frequency) == 1){
-			uiT2t = 0;
+
+		if(ddr3TipDevAttrGet(devNum, MV_ATTR_INTERLEAVE_WA ) == GT_TRUE){
+			/*If configured 1:1 Ratio, use 1T mode*/
+			if(configFuncInfo[devNum].tipGetClockRatio(frequency) == 1){ /*Low freq*/
+				CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, SDRAM_OPEN_PAGE_CONTROL_REG, 0x0, 0x3C0));
+				uiT2t = 0;
+			}
+			else{/*medium or target FREQ*/
+				CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, SDRAM_OPEN_PAGE_CONTROL_REG, 0x3C0, 0x3C0));
+			}
 		}
 		CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DDR_CONTROL_LOW_REG, uiT2t << 3,0x3 << 3));
 
@@ -2601,6 +2609,7 @@
 			}
 		}
     }
+
     /*if (maskTuneFunc & ADJUST_DQS_MASK_BIT)
     {
         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("ADJUST_DQS_MASK_BIT\n"));
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
index 1fded4f..6eb24b8 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
@@ -426,6 +426,7 @@
 	ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_CPU);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
+	ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
 
 #ifdef STATIC_ALGO_SUPPORT
     ddr3TipInitStaticConfigDb(devNum, &staticConfig);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
index cd6ba7a..c45f640 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
@@ -783,6 +783,7 @@
 	ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_TIP);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, BC2_NUMBER_OF_PUP);
+	ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
 
 	maskTuneFunc = ( INIT_CONTROLLER_MASK_BIT |
                      SET_MEDIUM_FREQ_MASK_BIT |
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
index 7490b86..b8de52f 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
@@ -923,6 +923,7 @@
 	ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_TIP);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
+	ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
 
 #ifdef STATIC_ALGO_SUPPORT
     ddr3TipInitStaticConfigDb(devNum, &staticConfig);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 7026db5..28dac14 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -557,6 +557,11 @@
 	ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_CPU);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE);
 	ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
+#ifdef CONFIG_ARMADA_39X
+	ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_TRUE);
+#else
+	ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
+#endif
 
 #ifdef STATIC_ALGO_SUPPORT
 	{