bc2: Add support to new RD MTL BC2 board
- Update board scructures for RD MTL BC2 board:
* Remove second OOB port
* Add EEPROM and CPLD TWSI devices
- Allow reading board ID and revision information from CPLD
- Add DDR3 topology for supporting the new board
- For correct support of this board a 24C64 EEPROM should
be installed into socket U7 and programmed with board ID=2
Change-Id: I25f4f5e019630f0785fe3636fc51959b8b5f5c85
Signed-off-by: kostap <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19289
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
(cherry picked from commit 91eeeacc770dbd58af4ed00976b08417d78fd129)
Reviewed-on: http://vgitil04.il.marvell.com:8080/19717
Tested-by: Star_Automation <star@marvell.com>
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index b75e660..b231f58 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -799,30 +799,37 @@
MV_VOID mvBoardCpldConfigurationGet(char *str)
{
MV_U8 cpldTwsiDev, cpldConfig;
+ MV_U8 cpldBoardRevReg = CPLD_BOARD_REV_REG;
+ MV_U16 boardModel;
- /* CPLD board configuration print for AC3 */
- if (mvCtrlDevFamilyIdGet(0) != MV_ALLEYCAT3_DEV_ID)
- return;
+ /* Prevent the caller function from printing the same string twice if this function fails */
+ *str = 0;
+
cpldTwsiDev = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_PLD, 0);
/* verify that CPLD device is available on current board, else return*/
if (cpldTwsiDev == 0xff || mvTwsiProbe(cpldTwsiDev, mvBoardTclkGet()) != MV_TRUE)
return;
+ boardModel = mvBoardModelGet();
+ if (boardModel == RD_MTL_BC2_PCB_ID)
+ cpldBoardRevReg = CPLD_RD_MTL_BC2_BOARD_REV_REG;
+
/* Read Board Revision */
- if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_BOARD_REV_REG, &cpldConfig)) {
+ if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, cpldBoardRevReg, &cpldConfig)) {
mvOsPrintf("\n%s: Error: failed reading board Revision from CPLD.\n", __func__);
return;
}
sprintf(str, ", Rev %d" , cpldConfig & CPLD_BOARD_REV_MASK);
/* Read CPLD Revision */
- if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_REV_REG, &cpldConfig)) {
- mvOsPrintf("\n%s: Error: failed reading CPLD Revision from CPLD.\n", __func__);
- return;
+ if (boardModel != RD_MTL_BC2_PCB_ID) {
+ if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_REV_REG, &cpldConfig)) {
+ mvOsPrintf("\n%s: Error: failed reading CPLD Revision from CPLD.\n", __func__);
+ return;
+ }
+ sprintf(str, "%s, CPLD Rev %d", str, cpldConfig & CPLD_BOARD_REV_MASK);
}
-
- sprintf(str, "%s, CPLD Rev %d", str, cpldConfig & CPLD_BOARD_REV_MASK);
}
/* Board devices API managments */
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
index 8b7d4ec..fdae6b1 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
@@ -485,10 +485,15 @@
/*NAND care support for small page chips*/
#define RD_MTL_BC2_BOARD_NAND_CONTROL 0x01c00543
+MV_BOARD_TWSI_INFO bc2_rd_mtlInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x77, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Ini EPROM */
+};
+
MV_BOARD_MAC_INFO bc2_rd_mtlInfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
{BOARD_MAC_SPEED_1000M, 0x0, 0x0 },
- {BOARD_MAC_SPEED_1000M, 0x1, 0x1 },
};
MV_BOARD_MODULE_TYPE_INFO bc2_rd_mtlInfoBoardModTypeInfo[] = {
@@ -515,24 +520,24 @@
};
MV_BOARD_INFO bc2_rd_mtlInfo = {
- .boardName = "RD-BC2-MTL-PoE-2QSFP-6SFP",
+ .boardName = "RD-MTL-BC2-48G-12XG2XLG",
.numBoardMppTypeValue = ARRSZ(bc2_rd_mtlInfoBoardModTypeInfo),
- .pBoardModTypeValue = bc2_rd_mtlInfoBoardModTypeInfo,
+ .pBoardModTypeValue = bc2_rd_mtlInfoBoardModTypeInfo,
.numBoardMppConfigValue = ARRSZ(bc2_rd_mtlInfoBoardMppConfigValue),
.pBoardMppConfigValue = bc2_rd_mtlInfoBoardMppConfigValue,
.intsGppMaskLow = 0,
.intsGppMaskMid = 0,
.intsGppMaskHigh = 0,
.numBoardDeviceIf = ARRSZ(bc2_rd_mtlInfoBoardDeCsInfo),
- .pDevCsInfo = bc2_rd_mtlInfoBoardDeCsInfo,
- .numBoardTwsiDev = 0,
- .pBoardTwsiDev = NULL,
+ .pDevCsInfo = bc2_rd_mtlInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bc2_rd_mtlInfoBoardTwsiDev),
+ .pBoardTwsiDev = bc2_rd_mtlInfoBoardTwsiDev,
.numBoardMacInfo = ARRSZ(bc2_rd_mtlInfoBoardMacInfo),
.pBoardMacInfo = bc2_rd_mtlInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = NULL,
.activeLedsNumber = 0,
- .pLedGppPin = NULL,
+ .pLedGppPin = NULL,
.ledsPolarity = 0,
/* GPP values */
@@ -551,8 +556,8 @@
.switchInfoNum = 0,
/* NAND init params */
- .nandFlashReadParams = RD_MTL_BC2_BOARD_NAND_READ_PARAMS,
- .nandFlashWriteParams = RD_MTL_BC2_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashReadParams = RD_MTL_BC2_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = RD_MTL_BC2_BOARD_NAND_WRITE_PARAMS,
.nandFlashControl = RD_MTL_BC2_BOARD_NAND_CONTROL
};
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
index 7846724..5c3c218 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
@@ -106,6 +106,7 @@
#define INVALID_BOARD_ID 0xFFFF
#define BOARD_ID_INDEX_MASK 0x10 /* Mask used to return board index via board Id */
+#define RD_MTL_BC2_PCB_ID 0x70
#if defined CONFIG_ALLEYCAT3
#define MARVELL_BOARD_ID_BASE AC3_MARVELL_BOARD_ID_BASE
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index f1d2632..cbe536a 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -255,6 +255,7 @@
#define ICDR_UINIT_ID_MASK 0x0F
#define ICDR_UNIT_ID_4_DFX 0x0f
+#define CPLD_RD_MTL_BC2_BOARD_REV_REG 2
#define CPLD_BOARD_REV_REG 1
#define CPLD_BOARD_REV_MASK 0x7
#define CPLD_REV_REG 2
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_topology.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_topology.h
index 135e162..049fe80 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_topology.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_topology.h
@@ -124,7 +124,18 @@
{{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}, }, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
} ,
INTERFACE_BUS_MASK_32BIT /* Buses mask */
- }
+ },
+ /* 3rd Marvell board */
+{
+ 0x10, /* active interfaces #1*/
+ /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */
+ { {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16, MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH}} ,
+ INTERFACE_BUS_MASK_32BIT /* Buses mask */
+ },
};
#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
