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| *******************************************************************************/ |
| |
| |
| #ifndef _MV_CTRL_PEX_H |
| #define _MV_CTRL_PEX_H |
| |
| #include "mvSysEnvLib.h" |
| |
| /********************************* Definitions ********************************/ |
| |
| /* Sample at Reset */ |
| #define MPP_SAMPLE_AT_RESET(id) (0xE4200 + (id * 4)) |
| #define DEV_ID_REG 0x18238 |
| |
| #define DEVICE_ID_OFFS 16 |
| #define DEVICE_ID_MASK 0xFFFF0000 |
| |
| #define SATR_DEVICE_ID_2_0_OFFS 21 |
| #define SATR_DEVICE_ID_2_0_MASK (3 << SATR_DEVICE_ID_2_0_OFFS) |
| |
| /* PCI Express Control and Status Registers */ |
| #define MAX_PEX_BUSSES 256 |
| |
| #define PEX_CAPABILITIES_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x60) |
| #define PEX_LINK_CTRL_STATUS2_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x90) |
| #define PEX_CTRL_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A00) |
| #define PEX_STATUS_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A04) |
| #define PEX_DBG_CTRL_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A60) |
| #define PEX_DBG_STATUS_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x1A64) |
| #define PEX_LINK_CAPABILITY_REG 0x6C |
| #define PEX_LINK_CTRL_STAT_REG 0x70 |
| #define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ |
| #define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) |
| #define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ |
| #define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) |
| |
| /* SOC_CTRL_REG fields */ |
| #define MV_MISC_REGS_OFFSET (0x18200) |
| #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) |
| |
| /* PEX_CAPABILITIES_REG fields */ |
| #define PCIE0_ENABLE_OFFS 0 |
| #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) |
| #define PCIE1_ENABLE_OFFS 1 |
| #define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS) |
| #define PCIE2_ENABLE_OFFS 2 |
| #define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS) |
| #define PCIE3_ENABLE_OFFS 3 |
| #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS) |
| |
| /* Controller revision info */ |
| #define PEX_DEVICE_AND_VENDOR_ID 0x000 |
| |
| /* PCI Express Configuration Address Register */ |
| #define PXCAR_REG_NUM_OFFS 2 |
| #define PXCAR_REG_NUM_MAX 0x3F |
| #define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) |
| #define PXCAR_FUNC_NUM_OFFS 8 |
| #define PXCAR_FUNC_NUM_MAX 0x7 |
| #define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) |
| #define PXCAR_DEVICE_NUM_OFFS 11 |
| #define PXCAR_DEVICE_NUM_MAX 0x1F |
| #define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) |
| #define PXCAR_BUS_NUM_OFFS 16 |
| #define PXCAR_BUS_NUM_MAX 0xFF |
| #define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) |
| #define PXCAR_EXT_REG_NUM_OFFS 24 |
| #define PXCAR_EXT_REG_NUM_MAX 0xF |
| |
| #define PEX_CFG_ADDR_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x18F8) |
| #define PEX_CFG_DATA_REG(pexIf) ((MV_PEX_IF_REGS_BASE(pexIf)) + 0x18FC) |
| |
| #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 |
| #define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) |
| |
| #define PXCAR_CONFIG_EN BIT31 |
| #define PEX_STATUS_AND_COMMAND 0x004 |
| #define PXSAC_MABORT BIT29 /* Recieved Master Abort */ |
| |
| typedef enum { |
| MV_PCIE_POLARITY_EP = 0, |
| MV_PCIE_POLARITY_RC |
| } MV_PCIE_POLARITY; |
| |
| /*************************** Functions declarations ***************************/ |
| |
| /************************************************************************** |
| * mvHwsPexConfig - |
| * |
| * DESCRIPTION: Executes PEX MAC configuration |
| * INPUT: serdesMap - The board topology map |
| * OUTPUT: Configuration for PEX lanes. |
| * RETURNS: MV_OK - for success |
| ***************************************************************************/ |
| MV_STATUS mvHwsPexConfig(); |
| |
| #endif |
