tree eda994f6bcb810926734c06526fa92f08c26acf3
parent 76df89cd730acd229bc904767c0d153c5b2c748a
author hayim <hayim@marvell.com> 1446556699 +0200
committer Greg Poist <poist@google.com> 1458845994 -0700

fix: ddr3libv2: fix tWR timing parameter calculation

    - in controller init, tWR was set to 0 by default so
      it was fixed to be taken from speed bin table (according
      to tCKCLK).
    - in FreqSet the calculation was wrong and it was now
      updated to the same way as in controller init.

Change-Id: I3bc6bb04c77276581124c9c82663f869718f60dc
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24547
Reviewed-by: Margarita Granov <margra@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Tested-by: Star_Automation <star@marvell.com>