commit 797b00730d5e462a4ce97efd5871c90280b00815
author hayim <hayim@marvell.com> Tue Nov 03 15:18:19 2015 +0200
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree eda994f6bcb810926734c06526fa92f08c26acf3
parent 76df89cd730acd229bc904767c0d153c5b2c748a

fix: ddr3libv2: fix tWR timing parameter calculation

    - in controller init, tWR was set to 0 by default so
      it was fixed to be taken from speed bin table (according
      to tCKCLK).
    - in FreqSet the calculation was wrong and it was now
      updated to the same way as in controller init.

Change-Id: I3bc6bb04c77276581124c9c82663f869718f60dc
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24547
Reviewed-by: Margarita Granov <margra@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Tested-by: Star_Automation <star@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 50ab797..7a5f485 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -655,6 +655,8 @@
 	            cwlVal = topologyMap->interfaceParams[interfaceId].casWL;
 	            DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("clValue 0x%x cwlVal 0x%x \n", clValue, cwlVal));
 
+                tWR = TIME_2_CLOCK_CYCLES(speedBinTable(speedBinIndex,speedBinTableElements_tWR), tCKCLK);
+
 	            dataValue = ((clMaskTable[clValue] & 0x1) << 2) | ((clMaskTable[clValue] & 0xE)  <<  3);
 	            CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
 				CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, (twrMaskTable[tWR + 1] << 9), (0x7 << 9)));
@@ -1428,6 +1430,7 @@
 )
 {
     GT_U32 clValue = 0, cwlValue = 0, memMask = 0, dataValue = 0, tHCLK = 0, tWR = 0, refreshIntervalCnt = 0, cntId, interfaceIdx = 0;
+    GT_U32 tCKCLK = 0;
 	GT_U32 startIf, endIf;
     GT_U32 tREFI = 0;
     GT_BOOL isDllOff = GT_FALSE;
@@ -1502,8 +1505,9 @@
     /*DFS  - CL/CWL parameters after exiting SR*/
 
     /*DFS  - Enter Self-Refresh*/
-    tWR = speedBinTable(speedBinIndex,speedBinTableElements_tWR);
-    tWR = (tWR / 1000);
+    tCKCLK = (MEGA/freqVal[frequency]);
+    tWR = TIME_2_CLOCK_CYCLES(speedBinTable(speedBinIndex,speedBinTableElements_tWR), tCKCLK);
+
     /* dataValue = (clMaskTable[clValue] << 8) |  (cwlMaskTable[cwlValue] << 12) | (1 << 1) | (1 << 2) | (twrMaskTable[tWR+1] << 16);*/
     CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DFS_REG, (clMaskTable[clValue] << 8) , 0xF00));
     CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DFS_REG, (cwlMaskTable[cwlValue] << 12) , 0x7000));
@@ -1651,6 +1655,7 @@
 )
 {
     GT_U32 clValue = 0, cwlValue = 0, memMask = 0, dataValue = 0, busCnt = 0, tHCLK = 0, tWR = 0, refreshIntervalCnt = 0, cntId;
+    GT_U32 tCKCLK;
     GT_U32 endIf, startIf;
     GT_U32 tREFI = 0;
     GT_U32 busIndex = 0;
@@ -1809,8 +1814,10 @@
         /*DFS  - CL/CWL/WR parameters after exiting SR*/
         CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, DFS_REG, (clMaskTable[clValue] << 8) , 0xF00)); 
         CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, DFS_REG, (cwlMaskTable[cwlValue] << 12) , 0x7000));
-        tWR = speedBinTable(speedBinIndex,speedBinTableElements_tWR);
-        tWR = (tWR / 1000);
+
+        tCKCLK = (MEGA/freqVal[frequency]);
+        tWR = TIME_2_CLOCK_CYCLES(speedBinTable(speedBinIndex,speedBinTableElements_tWR), tCKCLK);
+
        /* dataValue = (clMaskTable[clValue] << 8) |  (cwlMaskTable[cwlValue] << 12) | (1 << 1) | (1 << 2) | (twrMaskTable[tWR+1] << 16);*/
         CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, DFS_REG, (twrMaskTable[tWR+1] << 16) , 0x70000));