fix: ddr3libv2: fix tWR timing parameter calculation
- in controller init, tWR was set to 0 by default so
it was fixed to be taken from speed bin table (according
to tCKCLK).
- in FreqSet the calculation was wrong and it was now
updated to the same way as in controller init.
Change-Id: I3bc6bb04c77276581124c9c82663f869718f60dc
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24547
Reviewed-by: Margarita Granov <margra@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Tested-by: Star_Automation <star@marvell.com>
1 file changed
