msys: preliminary compilation support for BOBK
-BOBK preliminary support (compilation only):
U-Boot:in msys_family
Binary_Header:
* src_phy, src_init, src_pm: msys
* src_ddr: generic libv2
-Serdes type and USB definitions are added per Silicon
-Single entry for BOARD name in makefiles
base.mk parse autoconf.mk to define unique BOARDNAME
that should be used as board SoC identifies.
Two additional files used autoconf.mk again -
changed to LIBNAME usage
-Preliminary board ID range for BobK Marvell and customer boards
Change-Id: I6ffd56afcf42a207e50aec4bbd897b52b2ed652f
Signed-off-by: Igor Petrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/20370
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24134
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
old mode 100644
new mode 100755
index c84f3cb..7e22b24
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
@@ -68,10 +68,10 @@
TIP_INC = $(BH_ROOT_DIR)/src_ddr/ddr3libv2/h
INCLUDE = -I$(TIP_INC)/Os -I$(TIP_INC)/Os/gtOs -I$(TIP_INC)/Os/common/siliconIf \
- -I$(TIP_INC)/SoC -I$(TIP_INC)/Silicon -I$(TIP_INC)/Os/common/configElementDb \
- -I$(TIP_INC)/Driver -I$(TIP_INC)/Driver/ddr3 -I$(BH_ROOT_DIR)/inc/common \
- -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME) \
- -I$(BH_ROOT_DIR)/src_ddr -I$(BH_ROOT_DIR)/platform/sysEnv/$(BOARD)
+ -I$(TIP_INC)/SoC -I$(TIP_INC)/Silicon -I$(TIP_INC)/Os/common/configElementDb \
+ -I$(TIP_INC)/Driver -I$(TIP_INC)/Driver/ddr3 -I$(BH_ROOT_DIR)/inc/common \
+ -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME) \
+ -I$(BH_ROOT_DIR)/src_ddr -I$(BH_ROOT_DIR)/platform/sysEnv/$(BOARD)
ifeq ($(DDRTYPE),ddr4)
INCLUDE += -I$(BH_ROOT_DIR)/src_ddr/ddr3libv2/src/Driver/ddr4/h
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
index 4557e06..7679aa3 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
@@ -195,7 +195,7 @@
/************************* Definitions *******************************************/
-#if defined(CONFIG_BOBCAT2) || (defined(CHX_FAMILY) || defined(EXMXPM_FAMILY))
+#if defined(CONFIG_BOBK) || defined(CONFIG_BOBCAT2) || (defined(CHX_FAMILY) || defined(EXMXPM_FAMILY))
#define MAX_INTERFACE_NUM (5)
#else
#define MAX_INTERFACE_NUM (1)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3BobK.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3BobK.h
new file mode 100755
index 0000000..60d2441
--- /dev/null
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3BobK.h
@@ -0,0 +1,151 @@
+/******************************************************************************
+* Copyright (c) Marvell International Ltd. and its affiliates
+*
+* This software file (the "File") is owned and distributed by Marvell
+* International Ltd. and/or its affiliates ("Marvell") under the following
+* alternative licensing terms.
+* If you received this File from Marvell, you may opt to use, redistribute
+* and/or modify this File under the following licensing terms.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* - Neither the name of Marvell nor the names of its contributors may be
+* used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* mvHwsDdr3BobK.h
+*
+* DESCRIPTION:
+*
+*
+* FILE REVISION NUMBER:
+* $Revision: 9 $
+*
+*******************************************************************************/
+
+#ifndef __mvHwsDdr3_BOBK_H
+#define __mvHwsDdr3_BOBK_H
+
+#include "config_marvell.h" /* Required to identify SOC and Board */
+#include "mvSysEnvLib.h"
+
+#include "mvDdr3TrainingIpStatic.h"
+#include "mvDdr3TrainingIp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************* Definitions ***********************************************/
+
+#define BOBK_NUMBER_OF_BOARDS (2)
+#define NUMBER_OF_PUP 5
+/************************* Enums ***********************************************/
+
+typedef enum {
+ TM_EN,
+ MSYS_EN
+}DDR_IF_ASSIGNMENT;
+
+/************************* Globals ***********************************************/
+
+#ifndef DEFINE_GLOBALS
+extern TripDelayElement bobKBoardRoundTripDelayArray[MAX_INTERFACE_NUM*MAX_BUS_NUM*BOBK_NUMBER_OF_BOARDS];
+#else
+/* this array hold the board round trip delay (DQ and CK) per <interfcae,bus> */
+TripDelayElement bobKBoardRoundTripDelayArray[MAX_INTERFACE_NUM*MAX_BUS_NUM*BOBK_NUMBER_OF_BOARDS] =
+{
+ /* 1st board */
+ /*interface bus DQS-delay CK-delay */
+ { 3012, 6715 },
+ { 2625, 6715 },
+ { 3023, 6458 },
+ { 2663, 6458 },
+ { 2596, 6691 },
+
+ /* 2nd board */
+ /*interface bus DQS-delay CK-delay */
+ { 3012, 6715 },
+ { 2625, 6715 },
+ { 3023, 6458 },
+ { 2663, 6458 },
+ { 2596, 6691 },
+};
+#endif
+
+
+#ifndef DEFINE_GLOBALS
+extern TripDelayElement bobKPackageRoundTripDelayArray[MAX_INTERFACE_NUM*MAX_BUS_NUM];
+#else
+/* package trace */
+TripDelayElement bobKPackageRoundTripDelayArray[MAX_INTERFACE_NUM*MAX_BUS_NUM] =
+{
+ /*IF BUS DQ_DELYA CK_DELAY */
+ { 362, 813 },
+ { 458, 813 },
+ { 405, 750 },
+ { 446, 750 },
+ { 393, 718 }
+};
+#endif
+
+#ifndef DEFINE_GLOBALS
+extern GT_32 bobKSiliconDelayOffset[];
+#else
+GT_32 bobKSiliconDelayOffset[] =
+{
+ /* board 0 */
+ 0,
+ /* board 1 */
+ 0,
+ /* board 2 */
+ 0
+};
+#endif
+
+/************************* Functions Declarations ***********************************************/
+
+/******************************************************************************
+* Name: ddr3TipInitBobK.
+* Desc: init Training SW DB and updates DDR topology.
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipInitBobK
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+) ;
+
+/******************************************************************************
+ * Name: ddr3GetSdramAssignment
+ * Desc: read S@R and return DDR3 assignment ( 0 = TM , 1 = MSYS )
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+DDR_IF_ASSIGNMENT ddr3GetSdramAssignment(GT_U8 devNum);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __mvHwsDdr3_BOBK_H */
+
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/SoC/ddr3_hws_sil.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/SoC/ddr3_hws_sil.h
index 5ed42a7..57e11e8 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/SoC/ddr3_hws_sil.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/SoC/ddr3_hws_sil.h
@@ -27,6 +27,9 @@
#if defined(MV_MSYS_BC2)
#include "ddr3_msys_bc2.h"
#include "ddr3_msys_bc2_config.h"
+#if defined(MV_MSYS_BOBK)
+#include "ddr3_msys_bobk.h"
+#include "ddr3_msys_bobk_config.h"
#elif defined(MV_MSYS_AC3)
#include "ddr3_msys_ac3.h"
#include "ddr3_msys_ac3_config.h"
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
new file mode 100755
index 0000000..a70ecd9
--- /dev/null
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -0,0 +1,1556 @@
+/*******************************************************************************
+* Copyright 2001, Marvell International Ltd.
+* This code contains confidential information of Marvell semiconductor, inc.
+* no rights are granted herein under any patent, mask work right or copyright
+* of Marvell or any third party.
+* Marvell reserves the right at its sole discretion to request that this code
+* be immediately returned to Marvell. This code is provided "as is".
+* Marvell makes no warranties, express, implied or otherwise, regarding its
+* accuracy, completeness or performance.
+********************************************************************************
+* mvHwsDdr3BobK.c
+*
+* DESCRIPTION: DDR3 BobK configuration
+*
+* DEPENDENCIES:
+******************************************************************************/
+
+#define DEFINE_GLOBALS
+#include "ddr3_msys_bobk.h"
+#include "mvHwsDdr3BobK.h"
+#include "mvDdr3TrainingIpStatic.h"
+#include "mvDdr3TrainingIpFlow.h"
+#include "mvDdrTrainingIpDb.h"
+#include "mvDdr3TrainingIp.h"
+#include "mvDdr3TrainingIpDef.h"
+#include "mvDdr3TrainingIpPrvIf.h"
+#include "mvDdr3LoggingDef.h"
+
+/************************** definitions ******************************/
+#define BOBK_NUM_BYTES (3)
+
+#define BOBK_CLIENT_FIELD(client) (client << 15)
+#define BOBK_GET_CLIENT_FIELD(interfaceAccess,interfaceId) ((interfaceAccess == ACCESS_TYPE_MULTICAST) ? BOBK_CLIENT_FIELD(MULTICAST_ID):BOBK_CLIENT_FIELD(interfaceId))
+#define BOBK_XSB_MAPPING(interfaceId, interfaceAccess, regaddr) (regaddr+ XSB_BASE_ADDR + BOBK_GET_CLIENT_FIELD(interfaceAccess,interfaceMap[interfaceId].client))
+#if 0
+#define CS_CBE_VALUE(csNum) (csCbeReg[csNum])
+#endif
+#define BOBK_CLIENT_MAPPING(interfaceId, regaddr) ((regaddr << 2)+ CLIENT_BASE_ADDR + BOBK_CLIENT_FIELD(interfaceMap[interfaceId].client))
+
+#define TM_PLL_REG_DATA(a,b,c) ((a << 12) + (b << 8) + (c << 2))
+#define R_MOD_W(writeData,readData,mask) ((writeData & mask) | (readData & (~mask)))
+
+
+/************************** pre-declaration ******************************/
+
+static GT_STATUS ddr3TipBobKGetMediumFreq
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ *freq
+);
+
+GT_STATUS ddr3TipBobKSetDivider
+(
+ GT_U8 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ freq
+);
+
+static GT_STATUS ddr3TipTmSetDivider
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ frequency
+);
+
+static GT_STATUS ddr3TipCpuSetDivider
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ frequency
+);
+
+GT_STATUS ddr3BobKUpdateTopologyMap
+(
+ GT_U32 devNum,
+ MV_HWS_TOPOLOGY_MAP* topologyMap
+);
+
+GT_STATUS ddr3TipBobKGetInitFreq
+(
+ GT_U8 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ* freq
+);
+
+GT_STATUS ddr3TipTmGetInitFreq
+(
+ GT_STATUS devNum,
+ MV_HWS_DDR_FREQ *freq
+);
+
+static GT_STATUS ddr3TipCpuGetInitFreq
+(
+ GT_STATUS devNum,
+ MV_HWS_DDR_FREQ *freq
+);
+
+GT_STATUS ddr3TipBobKRead
+(
+ GT_U8 devNum,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+);
+
+GT_STATUS ddr3TipBobKWrite
+(
+ GT_U8 devNum,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+);
+GT_STATUS ddr3TipBobKIFRead
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+);
+
+GT_STATUS ddr3TipBobKIFWrite
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+);
+
+GT_STATUS ddr3TipBobKIsfAccessDone
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId
+);
+
+GT_STATUS ddr3TipBobKGetDeviceInfo
+(
+ GT_U8 devNum,
+ MV_DDR3_DEVICE_INFO * infoPtr
+);
+
+/************************** Globals ******************************/
+
+extern GT_U32 maskTuneFunc;
+extern GT_U32 freqVal[];
+extern MV_HWS_DDR_FREQ mediumFreq;
+extern MV_HWS_TOPOLOGY_MAP *topologyMap;
+extern GT_U32 firstActiveIf;
+extern MV_HWS_DDR_FREQ initFreq;
+extern GT_U32 dfsLowFreq;
+extern GT_U32 dfsLowPhy1;
+extern GT_U32 PhyReg1Val;
+extern GT_U32 isPllBeforeInit;
+extern GT_U32 useBroadcast;
+extern GT_U32 isCbeRequired;
+extern GT_U32 delayEnable, ckDelay,caDelay;
+extern GT_U8 debugTrainingAccess;
+extern GT_U8 calibrationUpdateControl; /*2 external only, 1 is internal only*/
+extern GT_U32 dfsLowFreq;
+
+GT_U32 debugBobK = 0;
+GT_U32 pipeMulticastMask;
+
+#if 0
+static GT_U32 csCbeReg[]=
+{
+ 0xE , 0xD, 0xB, 0x7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+#endif
+static MV_DFX_ACCESS interfaceMap[] =
+{
+ /* Pipe Client*/
+ { 0, 17 },
+ { 1, 6 },
+ { 1, 10 },
+ { 0, 3 },
+ { 1, 18 }
+};
+
+static GT_U8 bobKBwPerFreq[DDR_FREQ_LIMIT] =
+{
+ 0x3, /*DDR_FREQ_LOW_FREQ*/
+ 0x4, /*DDR_FREQ_400*/
+ 0x4, /*DDR_FREQ_533*/
+ 0x5, /*DDR_FREQ_667*/
+ 0x5, /*DDR_FREQ_800*/
+ 0x5, /*DDR_FREQ_933,*/
+ 0x5, /*DDR_FREQ_1066*/
+ 0x3, /*DDR_FREQ_311*/
+ 0x3, /*DDR_FREQ_333*/
+ 0x4, /*DDR_FREQ_467*/
+ 0x5, /*DDR_FREQ_850*/
+ 0x5, /*DDR_FREQ_600*/
+ 0x3, /*DDR_FREQ_300*/
+ 0x5, /*DDR_FREQ_900*/
+ 0x3 /*DDR_FREQ_360*/
+};
+
+static GT_U8 bobKRatePerFreq[DDR_FREQ_LIMIT] =
+{
+ 0x1, /*DDR_FREQ_LOW_FREQ,*/
+ 0x2, /*DDR_FREQ_400,*/
+ 0x2, /*DDR_FREQ_533,*/
+ 0x2, /*DDR_FREQ_667,*/
+ 0x2, /*DDR_FREQ_800,*/
+ 0x3, /*DDR_FREQ_933,*/
+ 0x3, /*DDR_FREQ_1066,*/
+ 0x1, /*DDR_FREQ_311*/
+ 0x1, /*DDR_FREQ_333*/
+ 0x2, /*DDR_FREQ_467*/
+ 0x2, /*DDR_FREQ_850*/
+ 0x2, /*DDR_FREQ_600*/
+ 0x1, /*DDR_FREQ_300*/
+ 0x3, /*DDR_FREQ_900*/
+ 0x1 /*DDR_FREQ_360*/
+};
+
+GT_U32 phy1ValTable[DDR_FREQ_LIMIT] =
+{
+ 0, /* DDR_FREQ_LOW_FREQ */
+ 0xf, /* DDR_FREQ_400 */
+ 0xf, /* DDR_FREQ_533 */
+ 0xf, /* DDR_FREQ_667 */
+ 0xc, /* DDR_FREQ_800 */
+ 0x8, /* DDR_FREQ_933 */
+ 0x8, /* DDR_FREQ_1066 */
+ 0xf, /* DDR_FREQ_311 */
+ 0xf, /* DDR_FREQ_333 */
+ 0xf, /* DDR_FREQ_467 */
+ 0xc, /*DDR_FREQ_850*/
+ 0xf, /*DDR_FREQ_600*/
+ 0xf, /*DDR_FREQ_300*/
+ 0x8, /*DDR_FREQ_900*/
+ 0xf /*DDR_FREQ_360*/
+};
+
+/* Bit mapping (for PBS) */
+GT_U32 bobKDQbitMap2Phypin[] =
+{
+/*#warning "DQ mapping not updated!" !!!*/
+ /* Interface 0 */
+ 8, 1, 0, 7, 9, 2, 3, 6 , /* dq[0:7] */
+ 8, 1, 6, 3, 9, 7, 2, 0 , /* dq[8:15] */
+ 8, 1, 9, 2, 6, 7, 3, 0 , /* dq[16:23] */
+ 1, 6, 0, 8, 7, 3, 2, 9 , /* dq[24:31] */
+};
+
+#if defined(CHX_FAMILY) || defined(EXMXPM_FAMILY)
+MV_HWS_TOPOLOGY_MAP bobKTopologyMap[] =
+{
+ /* 1st board */
+ {
+ 0x1f, /* active interfaces */
+ /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_width mem_size frequency casL casWL temperature */
+ { {{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} },
+ 0xF /* Buses mask */
+ },
+
+ /* 2nd board */
+ {
+ 0x1f, /* active interfaces */
+ /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_width mem_size frequency casL casWL temperature */
+ { {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x1,0,0,0}, {0x1,0,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133N, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} },
+ 0xF /* Buses mask */
+ }
+};
+#endif
+
+GT_U8 ddr3TipClockMode( GT_U32 frequency );
+
+/************************** Server Access ******************************/
+GT_STATUS ddr3TipBobKServerRegWrite
+(
+ GT_U32 devNum,
+ GT_U32 regAddr,
+ GT_U32 dataValue
+)
+{
+#ifdef ASIC_SIMULATION
+ /* avoid warnings */
+ devNum = devNum;
+ regAddr = regAddr;
+ dataValue = dataValue;
+
+ return GT_OK;
+#else
+ return hwsServerRegSetFuncPtr(devNum, regAddr, dataValue);
+#endif
+}
+
+GT_STATUS ddr3TipBobKServerRegRead
+(
+ GT_U32 devNum,
+ GT_U32 regAddr,
+ GT_U32 *dataValue,
+ GT_U32 regMask
+)
+{
+#ifdef ASIC_SIMULATION
+ /* avoid warnings */
+ devNum = devNum;
+ regAddr = regAddr;
+ regMask = regMask;
+
+ *dataValue = 0;
+#else
+ hwsServerRegGetFuncPtr(devNum, regAddr, dataValue);
+
+
+ *dataValue = *dataValue & regMask;
+#endif
+ return GT_OK;
+}
+
+/**********************************************************************************/
+
+GT_STATUS ddr3TipBobKGetFreqConfig
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ freq,
+ MV_HWS_TIP_FREQ_CONFIG_INFO *freqConfigInfo
+)
+{
+ devNum = devNum; /* avoid warnings */
+
+ if (bobKBwPerFreq[freq] == 0xff)
+ {
+ return GT_NOT_SUPPORTED;
+ }
+
+ if (freqConfigInfo == NULL)
+ {
+ return GT_BAD_PARAM;
+ }
+
+ freqConfigInfo->bwPerFreq = bobKBwPerFreq[freq];
+ freqConfigInfo->ratePerFreq = bobKRatePerFreq[freq];
+
+ freqConfigInfo->isSupported = GT_TRUE;
+
+ return GT_OK;
+}
+
+/*****************************************************************************
+Enable Pipe
+******************************************************************************/
+GT_STATUS ddr3TipPipeEnable
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_BOOL enable
+)
+{
+ GT_U32 dataValue, pipeEnableMask = 0;
+
+
+ if (enable == GT_FALSE)
+ {
+ pipeEnableMask = 0;
+ }
+ else
+ {
+ if (interfaceAccess == ACCESS_TYPE_MULTICAST)
+ {
+ pipeEnableMask = pipeMulticastMask;
+ }
+ else
+ {
+ pipeEnableMask = (1 << interfaceMap[interfaceId].pipe);
+ }
+ }
+ CHECK_STATUS(ddr3TipBobKRead(devNum, PIPE_ENABLE_ADDR, &dataValue, MASK_ALL_BITS));
+ dataValue = (dataValue & (~0xFF)) | pipeEnableMask;
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, PIPE_ENABLE_ADDR, dataValue, MASK_ALL_BITS));
+
+ return GT_OK;
+}
+
+void ddr3TipIsUnicastAccess( GT_U8 devNum,GT_U32* interfaceId, MV_HWS_ACCESS_TYPE* interfaceAccess)
+{
+ GT_U32 indexCnt, totalCnt = 0 , interfaceTmp = 0;
+ MV_HWS_TOPOLOGY_MAP *topologyMap = ddr3TipGetTopologyMap(devNum);
+
+ if (*interfaceAccess == ACCESS_TYPE_MULTICAST)
+ {
+ for(indexCnt = 0; indexCnt < MAX_INTERFACE_NUM; indexCnt++)
+ {
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, indexCnt) != 0)
+ {
+ totalCnt++;
+ interfaceTmp = indexCnt;
+ continue;
+ }
+ }
+ if (totalCnt == 1) {
+ *interfaceAccess = ACCESS_TYPE_UNICAST;
+ *interfaceId = interfaceTmp;
+ }
+ }
+}
+
+/******************************************************************************
+* Name: ddr3TipBobKSelectTMDdrController.
+* Desc: Enable/Disable access to Marvell's server.
+* Args: devNum - device number
+* enable - whether to enable or disable the server
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKSelectTMDdrController
+(
+ GT_U8 devNum,
+ GT_BOOL enable
+)
+{
+ GT_U32 interfaceId = 0, dataValue = 0;
+ for(interfaceId=0; interfaceId <MAX_INTERFACE_NUM ;interfaceId++)
+ {
+ ddr3TipPipeEnable(devNum, ACCESS_TYPE_UNICAST, interfaceId, GT_TRUE);
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, interfaceId) == 0)
+ {
+ /*disable in-active interfaces (so they won't be accessed upon multicast)*/
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_CLIENT_MAPPING(interfaceId, CLIENT_CTRL_REG), &dataValue, MASK_ALL_BITS));
+ dataValue &= ~0x40;
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_CLIENT_MAPPING(interfaceId, CLIENT_CTRL_REG), dataValue));
+ continue;
+ }
+ /* Enable relevant Pipe */
+ pipeMulticastMask |= (1 << interfaceMap[interfaceId].pipe);
+ /* multicast Macro is subscribed to Multicast 0x1D */
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_CLIENT_MAPPING(interfaceId, CLIENT_CTRL_REG), &dataValue, MASK_ALL_BITS));
+ dataValue |= 0x40;
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_CLIENT_MAPPING(interfaceId, CLIENT_CTRL_REG), dataValue));
+
+ ddr3TipPipeEnable(devNum, ACCESS_TYPE_UNICAST, interfaceId, GT_FALSE);
+
+ }
+ /* enable access to relevant pipes (according to the pipe mask) */
+ ddr3TipPipeEnable(devNum, ACCESS_TYPE_MULTICAST, interfaceId, GT_TRUE);
+
+ if (enable)
+ {
+ /* Enable DDR Tuning */
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, READ_BUFFER_SELECT_REG, 0x8000, MASK_ALL_BITS));
+ /* configure duplicate CS */
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, CS_ENABLE_REG, 0x4A/*Haim 0x42*/, MASK_ALL_BITS));
+ }
+ else
+ {
+ /* Disable DDR Tuning Select */
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, CS_ENABLE_REG, 0x2, MASK_ALL_BITS));
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, READ_BUFFER_SELECT_REG, 0,MASK_ALL_BITS));
+ }
+ return GT_OK;
+}
+
+/*****************************************************************************
+Check if Dunit access is done
+******************************************************************************/
+
+GT_STATUS ddr3TipBobKIsAccessDone
+(
+ GT_U8 devNum,
+ GT_32 interfaceId
+)
+{
+ GT_U32 rdData = 1, cnt = 0;
+
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_CMD_REG), &rdData, MASK_ALL_BITS));
+ rdData &= 1;
+
+ while(rdData != 0)
+ {
+ if (cnt++ >= MAX_POLLING_ITERATIONS)
+ break;
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_CMD_REG), &rdData, MASK_ALL_BITS));
+ rdData &= 1;
+#ifdef ASIC_SIMULATION
+ rdData = 0;/* no more iterations needed */
+#endif /*ASIC_SIMULATION*/
+ }
+ if (cnt < MAX_POLLING_ITERATIONS)
+ {
+ return GT_OK;
+ }
+ else
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO,("AccessDone fail: if = %d\n",interfaceId));
+ return GT_FAIL;
+ }
+}
+
+/******************************************************************************/
+GT_STATUS ddr3TipBobKTMRead
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+)
+{
+ GT_U32 dataValue = 0, startIf, endIf;
+ MV_HWS_TOPOLOGY_MAP *topologyMap = ddr3TipGetTopologyMap(devNum);
+
+ ddr3TipIsUnicastAccess(devNum, &interfaceId, &interfaceAccess);
+
+ if (interfaceAccess == ACCESS_TYPE_UNICAST)
+ {
+ startIf = interfaceId;
+ endIf = interfaceId;
+ }
+ else
+ {
+ startIf = 0;
+ endIf = MAX_INTERFACE_NUM-1;
+ }
+
+ for(interfaceId = startIf; interfaceId <= endIf; interfaceId++)
+ {
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, interfaceId) == 0)
+ {
+ continue;
+ }
+ ddr3TipPipeEnable(devNum, ACCESS_TYPE_UNICAST, interfaceId, GT_TRUE);
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_CTRL_1_REG) ,TRAINING_ID));
+
+ /*working with XSB client InterfaceNum Write Interface ADDR as data to XSB address C*/
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_ADDRESS_REG), regAddr));
+ dataValue = ((GT_U32)(TARGET_INT << 19)) + (BYTE_EN << 11) + (BOBK_NUM_BYTES << 4) + (CMD_READ << 2) +(INTERNAL_ACCESS_PORT << 1) + EXECUTING;
+ /*Write Interface COMMAND as data to XSB address 8 */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_CMD_REG), dataValue));
+
+ CHECK_STATUS(ddr3TipBobKIsAccessDone(devNum, interfaceId));
+
+ /* consider that input data is always a vector, and for unicast the writing will be in the interface index in vector */
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_XSB_MAPPING(interfaceId, ACCESS_TYPE_UNICAST, XSB_DATA_REG), &data[interfaceId], mask));
+ if (debugBobK >= 2)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("DunitRead 0x%x: 0x%x (mask 0x%x)\n", regAddr, *data, mask));
+ }
+ /*ddr3TipPipeEnable(devNum, ACCESS_TYPE_UNICAST, interfaceId, GT_FALSE);*/
+ }
+ return GT_OK;
+}
+
+/******************************************************************************/
+GT_STATUS ddr3TipBobKTMWrite
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+)
+{
+ GT_U32 dataCmd = 0, uiDataRead = 0, uiReadInterfaceId=0;
+ GT_U32 dataRead[MAX_INTERFACE_NUM];
+ GT_U32 startIf, endIf;
+ MV_HWS_TOPOLOGY_MAP *topologyMap = ddr3TipGetTopologyMap(devNum);
+
+ ddr3TipIsUnicastAccess(devNum, &interfaceId, &interfaceAccess);
+ if (mask != MASK_ALL_BITS)
+ {
+ /* if all bits should be written there is no need for read-modify-write */
+ if (interfaceAccess == ACCESS_TYPE_MULTICAST)
+ {
+ CHECK_STATUS(ddr3TipGetFirstActiveIf(devNum, topologyMap->interfaceActiveMask, &uiReadInterfaceId));
+ }
+ else
+ {
+ uiReadInterfaceId = interfaceId;
+ }
+ if (debugBobK >= 2)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("ddr3TipBobKTMWrite active interface = %d\n",uiReadInterfaceId));
+ }
+ CHECK_STATUS(ddr3TipBobKRead(devNum, regAddr, dataRead,MASK_ALL_BITS));
+ uiDataRead = dataRead[uiReadInterfaceId];
+ dataValue = (uiDataRead & (~mask)) | (dataValue & mask);
+ }
+ ddr3TipPipeEnable(devNum, interfaceAccess, interfaceId, GT_TRUE);
+ /* set the ID */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, interfaceAccess, XSB_CTRL_1_REG) , TRAINING_ID));
+
+ /*working with XSB multicast client , Write Interface ADDR as data to XSB address C */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, interfaceAccess, XSB_ADDRESS_REG), regAddr));
+ /*Write Interface DATA as data to XSB address 0x10.*/
+ if (debugBobK >= 1)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("Dunit Write: interface %d access %d Address 0x%x Data 0x%x\n", interfaceId, interfaceAccess, regAddr, dataValue));
+ }
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, interfaceAccess, XSB_DATA_REG), dataValue));
+ dataCmd = ((GT_U32)(TARGET_INT << 19)) + (BYTE_EN << 11) + (BOBK_NUM_BYTES << 4) + (CMD_WRITE << 2) + (INTERNAL_ACCESS_PORT << 1);
+ /*Write Interface COMMAND as data to XSB address 8
+ Execute an internal write to xBar port1 */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, interfaceAccess, XSB_CMD_REG), dataCmd));
+ dataCmd |= EXECUTING;
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BOBK_XSB_MAPPING(interfaceId, interfaceAccess, XSB_CMD_REG), dataCmd));
+
+ /*check that write is completed; the test should be done per interface */
+ if (interfaceAccess == ACCESS_TYPE_MULTICAST)
+ {
+ startIf = 0;
+ endIf = MAX_INTERFACE_NUM-1;
+ }
+ else
+ {
+ startIf = interfaceId;
+ endIf = interfaceId;
+ }
+
+ for(interfaceId = startIf; interfaceId <= endIf; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ ddr3TipPipeEnable(devNum, ACCESS_TYPE_UNICAST, interfaceId, GT_TRUE);
+ CHECK_STATUS(ddr3TipBobKIsAccessDone(devNum, interfaceId));
+ }
+ /* ddr3TipPipeEnable(devNum, interfaceAccess, interfaceId, GT_FALSE);*/
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipBobKWrite.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKWrite
+(
+ GT_U8 devNum,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+)
+{
+ GT_U32 uiDataRead;
+#ifdef WIN32
+ return GT_OK;
+#endif
+ if (mask != MASK_ALL_BITS)
+ {
+ CHECK_STATUS(ddr3TipBobKRead(devNum, regAddr, &uiDataRead, MASK_ALL_BITS));
+ dataValue = (uiDataRead & (~mask)) | (dataValue & mask);
+ }
+
+ if (debugBobK >= 1)
+ {
+ mvPrintf("Dunit Write: Address 0x%x Data 0x%x\n", regAddr, dataValue);
+ }
+
+ MV_REG_WRITE(regAddr, dataValue);
+ if (debugBobK >= 2)
+ mvPrintf("write: 0x%x = 0x%x\n",regAddr,dataValue);
+
+ return GT_OK;
+}
+
+
+
+/******************************************************************************
+* Name: ddr3TipBobKRead.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKRead
+(
+ GT_U8 devNum,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+)
+{
+#ifdef WIN32
+ return GT_OK;
+#endif
+
+ *data = MV_REG_READ(regAddr) & mask;
+ if (debugBobK >= 2)
+ {
+ mvPrintf("DunitRead 0x%x: 0x%x (mask 0x%x)\n", regAddr, *data, mask);
+ }
+
+ return GT_OK;
+}
+/******************************************************************************
+* Name: ddr3TipBobKIFWrite.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKIFWrite
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+)
+{
+ interfaceAccess = interfaceAccess;
+ interfaceId = interfaceId;
+ return(ddr3TipBobKWrite(devNum,regAddr,dataValue,mask));
+}
+
+
+
+/******************************************************************************
+* Name: ddr3TipBobKIFRead.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKIFRead
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+)
+{
+ interfaceAccess = interfaceAccess;
+ interfaceId = interfaceId;
+ return(ddr3TipBobKRead(devNum,regAddr,data,mask));
+}
+
+
+/******************************************************************************
+* Name: ddr3TipBobKSelectCpuDdrController.
+* Desc: Enable/Disable access to Marvell's server.
+* Args: devNum - device number
+* enable - whether to enable or disable the server
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKSelectCPUDdrController
+(
+ GT_U8 devNum,
+ GT_BOOL enable
+)
+{
+ GT_U32 uiReg;
+ uiReg = MV_REG_READ(CS_ENABLE_REG);
+
+ if (enable)
+ {
+ uiReg |= (1 << 6);
+ }
+ else
+ {
+ uiReg &= ~(1 << 6);
+ }
+ MV_REG_WRITE(CS_ENABLE_REG, uiReg);
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipInitBobKSilicon.
+* Desc: init Training SW DB.
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+static GT_STATUS ddr3TipInitBobKSilicon
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+)
+{
+ MV_HWS_TIP_CONFIG_FUNC_DB configFunc;
+ MV_HWS_TOPOLOGY_MAP* topologyMap = ddr3TipGetTopologyMap(devNum);
+ GT_TUNE_TRAINING_PARAMS tuneParams;
+
+ if(topologyMap == NULL)
+ {
+ return GT_NOT_INITIALIZED;
+ }
+
+#if 0
+ ddr3TipBobKGetInterfaceMap((GT_U8)devNum);
+#endif
+
+ boardId = boardId; /* avoid warnings */
+
+#if defined(CHX_FAMILY) || defined(EXMXPM_FAMILY)
+ configFunc.tipDunitReadFunc = ddr3TipBobKTMRead;
+ configFunc.tipDunitWriteFunc = ddr3TipBobKTMWrite;
+ configFunc.tipDunitMuxSelectFunc = ddr3TipBobKSelectTMDdrController;
+#else
+ configFunc.tipDunitReadFunc = ddr3TipBobKIFRead;
+ configFunc.tipDunitWriteFunc = ddr3TipBobKIFWrite;
+ configFunc.tipDunitMuxSelectFunc = ddr3TipBobKSelectCPUDdrController;
+#endif
+ configFunc.tipGetFreqConfigInfoFunc = ddr3TipBobKGetFreqConfig;
+ configFunc.tipSetFreqDividerFunc = ddr3TipBobKSetDivider;
+ configFunc.tipGetDeviceInfoFunc = ddr3TipBobKGetDeviceInfo;
+ configFunc.tipGetTemperature = NULL;
+ configFunc.tipGetClockRatio = ddr3TipClockMode;
+
+ mvHwsDdr3TipInitConfigFunc(devNum, &configFunc);
+
+ /* register bit mapping (for PBS) */
+ ddr3TipRegisterDqTable(devNum, bobKDQbitMap2Phypin);
+
+ /*Set device attributes*/
+ ddr3TipDevAttrInit(devNum);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_2);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, NUMBER_OF_PUP);
+ /*ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);*/
+
+ maskTuneFunc = ( INIT_CONTROLLER_MASK_BIT |
+ SET_MEDIUM_FREQ_MASK_BIT |
+ WRITE_LEVELING_MASK_BIT |
+ LOAD_PATTERN_2_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ PBS_RX_MASK_BIT |
+ PBS_TX_MASK_BIT |
+ SET_TARGET_FREQ_MASK_BIT |
+ WRITE_LEVELING_TF_MASK_BIT |
+ READ_LEVELING_TF_MASK_BIT |
+ WRITE_LEVELING_SUPP_TF_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT |
+ CENTRALIZATION_TX_MASK_BIT);
+
+ /*Skip mid freq stages for 400Mhz DDR speed*/
+ if( (topologyMap->interfaceParams[firstActiveIf].memoryFreq == DDR_FREQ_400) ){
+ maskTuneFunc = (INIT_CONTROLLER_MASK_BIT |
+ WRITE_LEVELING_MASK_BIT |
+ LOAD_PATTERN_2_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT |
+ CENTRALIZATION_TX_MASK_BIT);
+ }
+
+ if( ckDelay == MV_PARAMS_UNDEFINED )
+ ckDelay = 150;
+ delayEnable = 1;
+ caDelay = 0;
+
+ /* update DGL parameters */
+ tuneParams.ckDelay = ckDelay;
+ tuneParams.PhyReg3Val = 0xA;
+ tuneParams.gRttNom = 0x44;
+ tuneParams.gDic = 0x2;
+ tuneParams.uiODTConfig = 0x120012;
+ tuneParams.gZpriData = 123;
+ tuneParams.gZnriData = 123;
+ tuneParams.gZpriCtrl = 74;
+ tuneParams.gZnriCtrl = 74;
+ tuneParams.gZpodtData = 45;
+ tuneParams.gZnodtData = 45;
+ tuneParams.gZpodtCtrl = 45;
+ tuneParams.gZnodtCtrl = 45;
+
+ CHECK_STATUS(ddr3TipTuneTrainingParams(devNum, &tuneParams));
+
+ /* frequency and general parameters */
+ ddr3TipBobKGetMediumFreq(devNum, firstActiveIf, &mediumFreq);
+ initFreq = topologyMap->interfaceParams[firstActiveIf].memoryFreq;
+ dfsLowFreq = 100;
+ dfsLowPhy1 = PhyReg1Val;
+ isPllBeforeInit = 0;
+ useBroadcast = GT_FALSE; /* multicast */
+ isCbeRequired = GT_TRUE;
+ calibrationUpdateControl = 2;
+
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3BobKUpdateTopologyMap.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3BobKUpdateTopologyMap(GT_U32 devNum, MV_HWS_TOPOLOGY_MAP* topologyMap)
+{
+ GT_U32 interfaceId;
+ MV_HWS_DDR_FREQ freq;
+
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("topologyMap->interfaceActiveMask is 0x%x\n", topologyMap->interfaceActiveMask));
+
+ #if defined(CHX_FAMILY) || defined(EXMXPM_FAMILY)
+ /* first check if TM is enabled. reading frequency will check if it's enabled or not
+ in case it's not, the function will exit with error */
+ CHECK_STATUS(ddr3TipTmGetInitFreq(devNum, &freq));
+
+ /* if interface 4 is active, check it's assignment and close it if it's for MSYS */
+ if(topologyMap->interfaceActiveMask & 0x10)
+ {
+ if(ddr3GetSdramAssignment((GT_U8)devNum) == MSYS_EN)
+ {
+ topologyMap->interfaceActiveMask &= ~0x10; /* remove interface 4 from mask */
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
+ ("Warning: DDR IF 4 is allocated to MSYS (and was removed from TM IF list)\n"));
+ }
+ }
+ #endif
+
+ for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM; interfaceId++) {
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, interfaceId) == GT_FALSE)
+ continue;
+ CHECK_STATUS(ddr3TipBobKGetInitFreq((GT_U8)devNum, interfaceId, &freq));
+ topologyMap->interfaceParams[interfaceId].memoryFreq = freq;
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Update topology frequency for interface %d to %d\n",interfaceId, freq));
+ }
+
+ /* re-calc topology parameters according to topology updates (if needed) */
+ CHECK_STATUS(mvHwsDdr3TipLoadTopologyMap(devNum, topologyMap));
+
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipInitBobK.
+* Desc: init Training SW DB and updates DDR topology.
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipInitBobK
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+)
+{
+ MV_HWS_TOPOLOGY_MAP* topologyMap = ddr3TipGetTopologyMap(devNum);
+
+ if(NULL == topologyMap)
+ {
+ #if defined(CHX_FAMILY) || defined(EXMXPM_FAMILY)
+ /* for CPSS, since topology is not always initialized, it is
+ needed to set it to default topology */
+ topologyMap = &bobKTopologyMap[0];
+ #else
+ return GT_FAIL;
+ #endif
+ }
+
+ CHECK_STATUS(ddr3BobKUpdateTopologyMap(devNum, topologyMap));
+
+ ddr3TipInitBobKSilicon(devNum, boardId);
+ return GT_OK;
+}
+
+
+/******************************************************************************
+* external read from memory
+*/
+GT_STATUS ddr3TipExtRead
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 numOfBursts,
+ GT_U32 *data
+)
+{
+ GT_U32 burstNum;
+
+ for(burstNum=0 ; burstNum < numOfBursts*8; burstNum++)
+ {
+ data[burstNum] = * (volatile unsigned int *) (regAddr + 4* burstNum);
+ }
+
+ return GT_OK;
+}
+
+
+/******************************************************************************
+* external write to memory
+*/
+GT_STATUS ddr3TipExtWrite
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 numOfBursts,
+ GT_U32 *data
+)
+{
+ GT_U32 burstNum;
+
+ for(burstNum=0 ; burstNum < numOfBursts*8; burstNum++)
+ {
+ *(volatile unsigned int *) (regAddr+4*burstNum) = data[burstNum];
+ }
+
+ return GT_OK;
+}
+
+#if 0
+/*****************************************************************************
+Data Reset
+******************************************************************************/
+static GT_STATUS ddr3TipDataReset
+(
+ GT_U32 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId
+)
+{
+ GT_STATUS retVal;
+ GT_U32 uiWordCnt;
+
+ for(uiWordCnt = 0; uiWordCnt < 8 ; uiWordCnt++)
+ {
+ /*Write Interface DATA as data to XSB address 0x10.*/
+ retVal = ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, interfaceAccess, XSB_DATA_REG+(uiWordCnt * 4)), 0xABCDEF12);
+ if (retVal != GT_OK)
+ {
+ return retVal;
+ }
+ }
+ return GT_OK;
+}
+/*****************************************************************************
+XSB External read
+******************************************************************************/
+GT_STATUS ddr3TipExtRead
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 numOfBursts,
+ GT_U32 *data
+)
+{
+ GT_U32 burstNum, wordNum , dataValue;
+ GT_U32 cntPoll;
+ MV_HWS_ACCESS_TYPE accessType = ACCESS_TYPE_UNICAST;
+ /*DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("=== EXTERNAL READ ==="));*/
+
+ ddr3TipPipeEnable((GT_U8)devNum, accessType, interfaceId, GT_TRUE);
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_CTRL_0_REG) ,EXT_TRAINING_ID));
+
+ for(burstNum=0 ; burstNum < numOfBursts; burstNum++)
+ {
+ ddr3TipDataReset(devNum, ACCESS_TYPE_UNICAST, interfaceId);
+ /*working with XSB client InterfaceNum Write Interface ADDR as data to XSB address C*/
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_ADDRESS_REG + (burstNum * 32)), regAddr));
+ if (isCbeRequired == GT_TRUE)
+ {
+ /*CS_CBE_VALUE(0)*/
+ dataValue = CS_CBE_VALUE(0) << 19;
+ }
+ else
+ {
+ dataValue = (GT_U32)(TARGET_EXT << 19);
+ }
+ dataValue |= (BYTE_EN << 11) + (NUM_BYTES_IN_BURST << 4) + (ACCESS_EXT << 3);
+ /*Write Interface COMMAND as data to XSB address 8 */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING( interfaceId, accessType, XSB_CMD_REG), dataValue));
+ dataValue |= EXECUTING;
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING( interfaceId, accessType, XSB_CMD_REG), dataValue));
+
+ for(cntPoll=0; cntPoll < MAX_POLLING_ITERATIONS; cntPoll++)
+ {
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BC2_XSB_MAPPING( interfaceId, accessType, XSB_CMD_REG), &dataValue, 0x1));
+
+ if (dataValue == 0)
+ break;
+ }
+
+ if (cntPoll >= MAX_POLLING_ITERATIONS)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("No Done indication for DDR Read\n", dataValue));
+ return GT_NOT_READY;
+ }
+
+ for(wordNum = 0; wordNum < EXT_ACCESS_BURST_LENGTH /*s_uiNumOfBytesInBurst/4*/; wordNum++)
+ {
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_DATA_REG + (wordNum * 4)), &data[wordNum], MASK_ALL_BITS));
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("ddr3TipExtRead data 0x%x \n",data[wordNum]));
+ }
+ }
+ return GT_OK;
+}
+
+
+
+/*****************************************************************************
+XSB External write
+******************************************************************************/
+GT_STATUS ddr3TipExtWrite
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 numOfBursts,
+ GT_U32 *addr
+)
+{
+ GT_U32 wordNum = 0, dataCmd = 0, burstNum=0, cntPoll = 0, dataValue = 0;
+ MV_HWS_ACCESS_TYPE accessType = ACCESS_TYPE_UNICAST;
+
+ ddr3TipPipeEnable((GT_U8)devNum, accessType, interfaceId, GT_TRUE);
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_CTRL_0_REG) ,EXT_TRAINING_ID ));
+ for(burstNum=0 ; burstNum < numOfBursts; burstNum++)
+ {
+ /*working with XSB multicast client , Write Interface ADDR as data to XSB address C */
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_ADDRESS_REG), regAddr + (burstNum * EXT_ACCESS_BURST_LENGTH * 4)));
+ for(wordNum = 0; wordNum < 8 ; wordNum++)
+ {
+ /*Write Interface DATA as data to XSB address 0x10.*/
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_DATA_REG + (wordNum * 4)), addr[wordNum]));
+ }
+ if (isCbeRequired == GT_TRUE)
+ {
+ dataCmd = CS_CBE_VALUE(0) << 19;
+ }
+ else
+ {
+ dataCmd = (GT_U32)(TARGET_EXT << 19);
+ }
+ dataCmd |= (BYTE_EN << 11) + (NUM_BYTES_IN_BURST << 4) + (ACCESS_EXT << 3) + EXT_MODE;
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_CMD_REG), dataCmd));
+ /* execute xsb write */
+ dataCmd |= 0x1;
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("ddr3TipExtWrite dataCmd 0x%x \n", dataCmd));
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, BC2_XSB_MAPPING(interfaceId, accessType, XSB_CMD_REG), dataCmd));
+
+ for(cntPoll=0; cntPoll < MAX_POLLING_ITERATIONS; cntPoll++)
+ {
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BC2_XSB_MAPPING( interfaceId, accessType, XSB_CMD_REG), &dataValue, 0x1));
+
+ if (dataValue == 0)
+ break;
+ }
+
+ if (cntPoll >= MAX_POLLING_ITERATIONS)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("No Done indication for DDR Write External\n", dataValue));
+ return GT_NOT_READY;
+ }
+
+ }
+ return GT_OK;
+}
+
+#endif
+/******************************************************************************
+ * Name: ddr3GetSdramAssignment
+ * Desc: read S@R and return DDR3 assignment ( 0 = TM , 1 = MSYS )
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+DDR_IF_ASSIGNMENT ddr3GetSdramAssignment(GT_U8 devNum)
+{
+#if 0
+ GT_U32 data = 0; /* initialized for simulation */
+
+ /* Read sample at reset setting */
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, BOBK_DEVICE_SAR1_REG_ADDR, &data, MASK_ALL_BITS));
+
+ data = (data >> BOBK_DEVICE_SAR1_MSYS_TM_SDRAM_SEL_OFFSET) & BOBK_DEVICE_SAR1_MSYS_TM_SDRAM_SEL_MASK;
+
+ return (data == 0) ? TM_EN : MSYS_EN;
+#endif
+ return MSYS_EN;
+}
+
+/******************************************************************************/
+/* PLL/Frequency Functionality */
+/******************************************************************************/
+
+/******************************************************************************
+* Name: ddr3TipBonKSetDivider.
+* Desc: Pll Divider
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKSetDivider
+(
+ GT_U8 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ frequency
+)
+{
+ if(interfaceId < 4)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("TM set divider for interface %d\n",interfaceId));
+ return ddr3TipTmSetDivider(devNum, frequency);
+ }
+
+ else
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("CPU set divider for interface 4\n"));
+ return ddr3TipCpuSetDivider(devNum, frequency);
+ }
+}
+
+/******************************************************************************
+* return 1 of core/DUNIT clock ration is 1 for given freq, 0 if clock ratios is 2:1
+*/
+GT_U8 ddr3TipClockMode(GT_U32 frequency)
+{
+ frequency = frequency; /* avoid warnings */
+
+ return 2;
+}
+
+/******************************************************************************
+* Name: ddr3TipTmSetDivider.
+* Desc: Pll Divider of The Trafic Manager Unit
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+static GT_STATUS ddr3TipTmSetDivider
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ frequency
+
+)
+{
+#if 0
+ GT_U32 data = 0, writeData; divider = 0, cntPoll;
+ GT_U32 version, regAddr;
+#endif
+ GT_U32 divider = 0;
+ MV_HWS_DDR_FREQ sarFreq;
+
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("TM PLL Config\n"));
+
+ /* Calc SAR */
+ CHECK_STATUS(ddr3TipTmGetInitFreq(devNum, &sarFreq));
+
+ divider = freqVal[sarFreq]/freqVal[frequency];
+
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("\tSAR value %d divider %d (freqVal[%d] %d freqVal[%d] %d\n",
+ sarFreq, divider, sarFreq, freqVal[sarFreq], frequency, freqVal[frequency]));
+
+#if 0
+ switch (divider)
+ {
+ case 1:
+ writeData = TM_PLL_REG_DATA(2,1,3);
+ break;
+ case 2:
+ writeData = TM_PLL_REG_DATA(4,2,3);
+ break;
+ case 3:
+ writeData = TM_PLL_REG_DATA(6,3,3);
+ break;
+ case 4:
+ writeData = TM_PLL_REG_DATA(8,4,3);
+ break;
+
+ default:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipTmSetDivider: %d divider is not supported\n", divider));
+ return GT_BAD_PARAM;
+ }
+
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, 0x000F8264, &data, MASK_ALL_BITS ));
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, 0x000F8264, R_MOD_W(writeData,data,0xFF0C)));
+
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, 0x000F8264, &data, MASK_ALL_BITS));
+ data |= (1<<16);
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, 0x000F8264, data));
+
+ /*hwsOsExactDelayPtr(devNum, 0, 10); */
+
+ CHECK_STATUS(ddr3TipBobKRevGet(devNum, &version));
+
+ regAddr = (version == 0 ) ? BC2_DEV_GENERAL_STATUS_REG1_ADDR_A0 : BC2_DEV_GENERAL_STATUS_REG1_ADDR_B0;
+
+ for(cntPoll=0; cntPoll < MAX_POLLING_ITERATIONS; cntPoll++)
+ {
+ /*
+ 0x000F82B4/0x000F8C84 20:19 ddr1_top_pll_clkdiv_clk_stable 0x3
+ 0x000F82B4/0x000F8C84 15:14 ddr0_top_pll_clkdiv_clk_stable 0x3
+ 0x000F82B4/0x000F8C84 10:9 ddr1_bot_pll_clkdiv_clk_stable 0x3
+ 0x000F82B4/0x000F8C84 5:4 ddr0_bot_pll_clkdiv_clk_stable 0x3
+ */
+
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, regAddr, &data, MASK_ALL_BITS));
+ if ((data & 0x18C630)== 0x18C630)
+ break;
+ }
+
+ if (cntPoll >= MAX_POLLING_ITERATIONS)
+ {
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipTmSetDivider data = 0x%x: PLL - No stable indication was received\n",data));
+ return GT_NOT_READY;
+
+ }
+
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, 0x000F8264, &data, MASK_ALL_BITS));
+ data &= ~(1<<16);
+ CHECK_STATUS(ddr3TipBobKServerRegWrite(devNum, 0x000F8264, R_MOD_W(0, data, (1<<16))));
+#endif
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipCpuSetDivider.
+* Desc: Pll Divider of the CPU(msys) Unit
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+static GT_STATUS ddr3TipCpuSetDivider
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ frequency
+)
+{
+ GT_U32 data = 0, writeData, divider = 0;
+ MV_HWS_DDR_FREQ sarFreq;
+#if 0
+ GT_U32 version, regAddr;
+#endif
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("CPU PLL Config\n"));
+
+ /* calc SAR */
+ ddr3TipCpuGetInitFreq(devNum, &sarFreq);
+ divider = freqVal[sarFreq]/freqVal[frequency];
+
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("\nSAR value %d divider %d freqVal[%d] %d freqVal[%d] %d\n",
+ sarFreq, divider, sarFreq, freqVal[sarFreq], frequency, freqVal[frequency]));
+
+ CHECK_STATUS(ddr3TipBobKRead(devNum, 0x000F82ec, &data, MASK_ALL_BITS ));
+ writeData = (0x1 << 9);
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, 0x000F82ec, R_MOD_W(writeData,data, (0x1 << 9)), MASK_ALL_BITS));
+
+ switch (divider)
+ {
+ case 1:
+ /*Not 800 is a 667 only*/
+ writeData = (sarFreq==DDR_FREQ_800)?(0x2):(0x1);
+ break;
+ case 2:
+ /*Not 800 is a 667 only*/
+ writeData = (sarFreq==DDR_FREQ_800)?(0x3):(0x2);
+ break;
+ default:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("Error: Wrong divider %d\n", divider));
+ return GT_BAD_PARAM;
+ break;
+ }
+
+ CHECK_STATUS(ddr3TipBobKRead(devNum, 0x000F82e8, &data, MASK_ALL_BITS ));
+ CHECK_STATUS(ddr3TipBobKWrite(devNum, 0x000F82e8, R_MOD_W(writeData,data, (0x7 << 0)), MASK_ALL_BITS));
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("\tCPU PLL config Done\n"));
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipBobKGetInitFreq.
+* Desc: choose from where to extract the frequency (TM or CPU)
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+GT_STATUS ddr3TipBobKGetInitFreq
+(
+ GT_U8 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ* sarFreq
+)
+{
+ GT_STATUS res;
+
+ if(interfaceId < 4)
+ {
+ res = ddr3TipTmGetInitFreq(devNum, sarFreq);
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("TM frequency for interface %d is %d\n",interfaceId, *sarFreq));
+ }
+ else
+ {
+ res = ddr3TipCpuGetInitFreq(devNum, sarFreq);
+ }
+ return res;
+}
+
+/*****************************************************************************
+TM interface frequency Get
+******************************************************************************/
+GT_STATUS ddr3TipTmGetInitFreq
+(
+ GT_STATUS devNum,
+ MV_HWS_DDR_FREQ *freq
+)
+{
+ GT_U32 data;
+
+ /* calc SAR */
+ CHECK_STATUS(ddr3TipBobKRead(devNum, 0x000F8204 , &data, MASK_ALL_BITS));
+ data = (data >> 15) & 0x7;
+#ifdef ASIC_SIMULATION
+ data = 2;
+#endif
+ switch(data)
+ {
+ case 0:
+ /* TM is disabled */
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("TM Disabled\n"));
+ *freq = DDR_FREQ_LIMIT;
+ return GT_NOT_INITIALIZED;
+
+ case 1:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("TM DDR_FREQ_800\n"));
+ *freq = DDR_FREQ_800;
+ break;
+
+ case 2:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("TM DDR_FREQ_933\n"));
+ *freq = DDR_FREQ_933;
+ break;
+
+ case 3:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("TM DDR_FREQ_667\n"));
+ *freq = DDR_FREQ_667;
+ break;
+
+ default:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipTmGetInitFreq: Unknown Freq SAR value 0x%x\n", data));
+ *freq = DDR_FREQ_LIMIT;
+ return GT_BAD_PARAM;
+ }
+ return GT_OK;
+}
+
+/*****************************************************************************
+CPU interface frequency Get
+******************************************************************************/
+static GT_STATUS ddr3TipCpuGetInitFreq
+(
+ GT_STATUS devNum,
+ MV_HWS_DDR_FREQ *freq
+)
+{
+ GT_U32 data;
+
+ /* calc SAR */
+ CHECK_STATUS(ddr3TipBobKRead(devNum, 0x000F8204 , &data, MASK_ALL_BITS ));
+ data = (data >> 18) & 0x7;
+#ifdef ASIC_SIMULATION
+ data = 3;
+#endif
+
+ switch(data)
+ {
+ case 0:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_400\n"));
+ *freq = DDR_FREQ_400;
+ break;
+
+ case 2:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_667\n"));
+ *freq = DDR_FREQ_667;
+ break;
+
+ case 3:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_800\n"));
+ *freq = DDR_FREQ_800;
+ break;
+
+ default:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipCpuGetInitFreq: Unknown SAR value 0x%x\n", data));
+ *freq = DDR_FREQ_LIMIT;
+ return GT_BAD_PARAM;
+ }
+
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: ddr3TipBobKGetMediumFreq.
+* Desc:
+* Args:
+* Notes:
+* Returns: GT_OK if success, other error code if fail.
+*/
+static GT_STATUS ddr3TipBobKGetMediumFreq
+(
+ GT_U32 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ *freq
+)
+{
+ GT_U32 sarFreq;
+
+ CHECK_STATUS(ddr3TipBobKRead((GT_U8)devNum, interfaceId, &sarFreq, MASK_ALL_BITS));
+
+ switch(sarFreq)
+ {
+ case DDR_FREQ_400:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("No medium freq supported for 400Mhz\n"));
+ *freq = DDR_FREQ_400;
+ break;
+
+ case DDR_FREQ_667:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_333\n"));
+ *freq = DDR_FREQ_333;
+ break;
+
+ case DDR_FREQ_800:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_400\n"));
+ *freq = DDR_FREQ_400;
+ break;
+
+ case DDR_FREQ_933:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_311\n"));
+ *freq = DDR_FREQ_311;
+ break;
+
+ default:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipBobKGetMediumFreq: Freq %d is not supported\n", sarFreq));
+ return GT_FAIL;
+ }
+ return GT_OK;
+}
+
+
+GT_STATUS ddr3TipBobKGetDeviceInfo
+(
+ GT_U8 devNum,
+ MV_DDR3_DEVICE_INFO * infoPtr
+)
+{
+ devNum = devNum; /* avoid warnings */
+
+ infoPtr->deviceId = 0xFC00;
+ infoPtr->ckDelay = ckDelay;
+
+ return GT_OK;
+}
+
+
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c
new file mode 100755
index 0000000..81a7a80
--- /dev/null
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c
@@ -0,0 +1,378 @@
+/*******************************************************************************
+* Copyright 2001, Marvell International Ltd.
+* This code contains confidential information of Marvell semiconductor, inc.
+* no rights are granted herein under any patent, mask work right or copyright
+* of Marvell or any third party.
+* Marvell reserves the right at its sole discretion to request that this code
+* be immediately returned to Marvell. This code is provided "as is".
+* Marvell makes no warranties, express, implied or otherwise, regarding its
+* accuracy, completeness or performance.
+********************************************************************************
+* ddr3_msys_training.c
+*
+* DESCRIPTION:
+*
+*
+* DEPENDENCIES:
+*
+* FILE REVISION NUMBER:
+* $Revision: 1 $
+***************************************************************************/
+
+#include "mv_os.h"
+#include "ddr3_msys_bobk.h"
+#include "ddr3_msys_bobk_config.h"
+#include "ddr3_hws_sil_training.h"
+#include "mvSiliconIf.h"
+#include "mvDdr3TrainingIpPrvIf.h"
+#include "mvHwsDdr3BobK.h"
+#include "printf.h"
+
+/************************** globals ***************************************/
+
+#if 0
+extern MV_SERVER_REG_ACCESS_SET hwsServerRegSetFuncPtr;
+extern MV_SERVER_REG_ACCESS_GET hwsServerRegGetFuncPtr;
+#endif
+
+GT_U32 serverBaseAddr = 0;
+/* the following global variables are set in ddr3TipDynamicReadLeveling */
+
+
+extern GT_U32 genericInitController;
+extern GT_U32 debugBobK;
+
+/************************** pre-declarations ******************************/
+GT_STATUS ddr3DunitAccessRead
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+);
+
+GT_STATUS ddr3DunitAccessWrite
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+);
+
+GT_STATUS ddr3DunitAccessInit
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+);
+
+MV_VOID configureServerWindows(void);
+
+extern GT_STATUS ddr3TipBobKGetFreqConfig
+(
+ GT_U8 devNum,
+ MV_HWS_DDR_FREQ freq,
+ MV_HWS_TIP_FREQ_CONFIG_INFO *freqConfigInfo
+);
+
+extern GT_STATUS ddr3TipBobKSetDivider
+(
+ GT_U8 devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ freq
+);
+
+extern GT_STATUS ddr3TipInitBobKSilicon
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+);
+extern GT_STATUS ddr3TipBobKGetInitFreq
+(
+ GT_STATUS devNum,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ *freq
+);
+
+GT_STATUS ddr3TipBobKSelectCPUDdrController
+(
+ GT_U8 devNum,
+ GT_BOOL enable
+);
+
+/***************************************************************************/
+
+#if 0
+/******************************************************************************
+* Name: serverRegSet.
+* Desc: definition of server write prototype
+* Args: TBD
+* Notes:
+* Returns: OK if success, other error code if fail.
+*/
+GT_STATUS serverRegSet
+(
+ GT_U8 devNum,
+ GT_U32 addr,
+ GT_U32 data
+)
+{
+ if(serverBaseAddr == 0) {
+ mvPrintf("Server windows were not initialized\n", 0);
+ return GT_NOT_INITIALIZED;
+ }
+
+ *((volatile unsigned int*)(serverBaseAddr+addr)) = data;
+ //mvPrintf("serverRegSet 0x%x =0x%x\n",addr,data);
+
+ return GT_OK;
+}
+
+/******************************************************************************
+* Name: serverRegGet.
+* Desc: definition of server read prototype
+* Args: TBD
+* Notes:
+* Returns: OK if success, other error code if fail.
+*/
+GT_STATUS serverRegGet
+(
+ GT_U8 devNum,
+ GT_U32 addr,
+ GT_U32 *data
+)
+{
+ if(serverBaseAddr == 0) {
+ mvPrintf("Server windows were not initialized\n", 0);
+ return GT_NOT_INITIALIZED;
+ }
+
+ *data = (*((volatile unsigned int*)(serverBaseAddr+addr)));
+ //mvPrintf("serverRegGet 0x%x =0x%x\n",addr,*data);
+
+ return GT_OK;
+}
+
+#endif
+
+MV_STATUS ddr3SiliconPreInit(void)
+{
+ MV_STATUS status;
+ MV_U8 devNum = 0;
+
+#if 0
+ /* initialize window to server */
+ configureServerWindows();
+#endif
+
+ if (ddr3GetSdramAssignment(devNum) == TM_EN) {
+ mvPrintf("Error: DDR3 interface is used by Traffic Manager\n", 0);
+ return MV_FAIL;
+ }
+
+#if 0
+ MV_U32 uiReg;
+ /* set dupicate CS configuration */
+ serverRegGet(0, 0xf8288, &uiReg);
+ uiReg |= (1 << 17);
+ serverRegSet(0, 0xf8288, uiReg);
+#endif
+
+ status = ddr3SiliconInit();
+ if (MV_OK != status) {
+ mvPrintf("DDR3 silicon init - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ CHECK_STATUS(ddr3TipBobKSelectCPUDdrController(0, GT_FALSE)); // set mux to msys
+
+ /* configure Dunit */
+ status = ddr3DunitAccessInit(0, 1);
+ if (MV_OK != status) {
+ mvPrintf("DDR3 Dunit Access Init - FAILED 0x%x\n", status);
+ return status;
+ }
+ return MV_OK;
+}
+
+MV_STATUS ddr3SiliconPostInit(void)
+{
+ MV_STATUS status;
+
+
+ status = ddr3SiliconInit();
+ if (MV_OK != status) {
+ mvPrintf("DDR3 silicon init - FAILED 0x%x\n", status);
+ return status;
+ }
+
+
+ CHECK_STATUS(ddr3TipBobKSelectCPUDdrController(0, GT_TRUE)); // set mux to tip
+
+ return MV_OK;
+}
+
+/******************************************************************************
+ * Name: ddr3TipInitSilicon
+ * Desc: initiate silicon parameters
+ * Args:
+ * Notes:
+ * Returns: required value
+ */
+MV_STATUS ddr3SiliconInit(void) {
+
+ MV_STATUS status;
+
+ genericInitController = 1;
+
+ status = ddr3TipInitBobK(0, 0);
+ if (MV_OK != status) {
+ mvPrintf("DDR3 Msys silicon init - FAILED 0x%x\n", status);
+ return status;
+ }
+
+ return MV_OK;
+}
+
+MV_STATUS ddr3PostRunAlg(void)
+{
+ MV_U32 readDelay[5];
+ GT_U32 gReadSampleDelay = 0x19191919;
+ GT_U32 gReadReadyDelay = 0x19191919;
+
+ CHECK_STATUS(mvHwsDdr3TipIFRead(0, ACCESS_TYPE_UNICAST, 4, REG_READ_DATA_SAMPLE_DELAYS_ADDR,
+ readDelay, MASK_ALL_BITS));
+
+ gReadSampleDelay = readDelay[4];
+
+ CHECK_STATUS(mvHwsDdr3TipIFRead(0, ACCESS_TYPE_UNICAST, 4, REG_READ_DATA_READY_DELAYS_ADDR,
+ readDelay, MASK_ALL_BITS));
+
+ gReadReadyDelay = readDelay[4];
+
+ CHECK_STATUS(ddr3TipBobKSelectCPUDdrController(0, GT_FALSE)); // set mux to msys
+
+ MV_REG_WRITE(REG_READ_DATA_SAMPLE_DELAYS_ADDR, gReadSampleDelay);
+ MV_REG_WRITE(REG_READ_DATA_READY_DELAYS_ADDR, gReadReadyDelay);
+ return MV_OK;
+}
+
+/********************************************/
+/*********** Msys D-Unit Access **********/
+/********************************************/
+
+
+GT_STATUS ddr3DunitAccessWrite
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 dataValue,
+ GT_U32 mask
+)
+{
+ GT_U32 uiDataRead;
+ GT_U32 dataRead[MAX_INTERFACE_NUM];
+#ifdef WIN32
+ mvPrintf(DEBUG_LEVEL_TRACE,"ddr3DunitAccessWrite 0x%x: 0x%x (mask 0x%x)\n", regAddr, dataValue);
+ return GT_OK;
+#endif
+ if (mask != MASK_ALL_BITS)
+ {
+ if (debugBobK >= 2)
+ {
+ mvPrintf("ddr3DunitAccessWrite active interface = %d\n",interfaceId);
+ }
+ CHECK_STATUS(ddr3DunitAccessRead(devNum, ACCESS_TYPE_UNICAST,interfaceId, regAddr, dataRead, MASK_ALL_BITS));
+ uiDataRead = dataRead[interfaceId];
+ dataValue = (uiDataRead & (~mask)) | (dataValue & mask);
+ }
+
+ if (debugBobK >= 1)
+ {
+ mvPrintf("0x%x: 0x%x\n", regAddr, dataValue);
+ }
+
+ MV_REG_WRITE(regAddr, dataValue);
+
+ return GT_OK;
+}
+
+GT_STATUS ddr3DunitAccessRead
+(
+ GT_U8 devNum,
+ MV_HWS_ACCESS_TYPE interfaceAccess,
+ GT_U32 interfaceId,
+ GT_U32 regAddr,
+ GT_U32 *data,
+ GT_U32 mask
+)
+{
+#ifdef WIN32
+ mvPrintf("ddr3DunitAccessRead 0x%x: 0x%x (mask 0x%x)\n", regAddr, *data);
+ return GT_OK;
+#endif
+
+ data[interfaceId] = MV_REG_READ(regAddr) & mask;
+
+ return GT_OK;
+}
+
+GT_STATUS ddr3DunitAccessInit
+(
+ GT_U32 devNum,
+ GT_U32 boardId
+)
+{
+ MV_HWS_TIP_CONFIG_FUNC_DB configFunc;
+
+ configFunc.tipDunitReadFunc = ddr3DunitAccessRead;
+ configFunc.tipDunitWriteFunc = ddr3DunitAccessWrite;
+ configFunc.tipDunitMuxSelectFunc = ddr3TipBobKSelectCPUDdrController;
+ configFunc.tipSetFreqDividerFunc = ddr3TipBobKSetDivider;
+ configFunc.tipGetFreqConfigInfoFunc = ddr3TipBobKGetFreqConfig;
+
+ mvHwsDdr3TipInitConfigFunc(devNum, &configFunc);
+
+ return GT_OK;
+}
+
+MV_VOID configureServerWindows(void)
+{
+ static MV_BOOL configDone = MV_FALSE;
+
+ if(configDone == MV_TRUE)
+ return;
+
+ MV_REG_WRITE(REG_XBAR_WIN_5_CTRL_ADDR, 0xF0081);
+
+ serverBaseAddr = MV_REG_READ(REG_XBAR_WIN_5_BASE_ADDR);
+
+#if 0
+ /* init server access */
+ hwsServerRegSetFuncPtr = serverRegSet;
+ hwsServerRegGetFuncPtr = serverRegGet;
+#endif
+
+ configDone = MV_TRUE;
+}
+
+/*****************************************************************************/
+GT_U32 ddr3TipGetInitFreq()
+{
+ MV_HWS_DDR_FREQ freq;
+
+ configureServerWindows();
+
+ ddr3TipBobKGetInitFreq(0, 0, &freq); /* In BobK interface 0 is the CPU interface*/
+
+ return freq;
+
+}
+
+
+
