diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
index a6dfb01..e37ab53 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
@@ -934,7 +934,7 @@
 MV_DEV_CS_INFO db78X60amcInfoBoardDeCsInfo[] = {
 	/*{deviceCS, params, devType, devWidth}*/
 #if defined(MV_INCLUDE_SPI)
-	{SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
+	{SPI_CS0_AXP, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
 #endif
 };
 
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
index a34dba4..711531f 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
@@ -91,7 +91,8 @@
 #endif
 
 /* Default Attributes array */
-MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY;
+MV_TARGET_ATTRIB mvTargetDefaultsArrayMsys[] = TARGETS_DEF_ARRAY;
+MV_TARGET_ATTRIB mvTargetDefaultsArrayAxp[] = TARGETS_DEF_ARRAY_AXP;
 
 /*******************************************************************************
 * mvCtrlAttribGet -
@@ -107,6 +108,13 @@
 *******************************************************************************/
 MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib)
 {
+	MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+	else
+		mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
 	targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib;
 	targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId;
 
@@ -115,6 +123,13 @@
 /*******************************************************************************/
 MV_STATUS mvCtrlAttribSet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib)
 {
+	MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+	else
+		mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
 	mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib  = targetAttrib->attrib;
 	mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId= targetAttrib->targetId;
 
@@ -137,6 +152,13 @@
 {
 	MV_TARGET target;
 	MV_TARGET x;
+	MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+	else
+		mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
 	for (target = SDRAM_CS0; target < MAX_TARGETS; target++) {
 		x = MV_CHANGE_BOOT_CS(target);
 		if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) &&
@@ -165,6 +187,13 @@
 {
 	MV_TARGET target;
 	MV_TARGET x;
+	MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+	else
+		mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
 	for (target = SDRAM_CS0; target < MAX_TARGETS; target++) {
 		x = MV_CHANGE_BOOT_CS(target);
 		if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) &&
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index 93e6e2c..659d689 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -901,7 +901,8 @@
 	}
 }
 
-static const char *cntrlName[] = TARGETS_NAME_ARRAY;
+static const char * const cntrlNameMsys[] = TARGETS_NAME_ARRAY;
+static const char * const cntrlNameAxp[] = TARGETS_NAME_ARRAY_AXP;
 
 /*******************************************************************************
 * mvCtrlTargetNameGet - Get Marvell controller target name
@@ -923,7 +924,10 @@
 	if (target >= MAX_TARGETS)
 		return "target unknown";
 
-	return cntrlName[target];
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		return cntrlNameAxp[target];
+	else
+		return cntrlNameMsys[target];
 }
 
 #if defined(MV_INCLUDE_PEX)
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index 0cd1a92..cb05eb4 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -428,7 +428,16 @@
 
 typedef enum {
 	PEX0_0x4	= 0,
-	PEXIF_MAX	= 1
+	PEX0_1x4	= 1,
+	PEX0_2x4	= 2,
+	PEX0_3x4	= 3,
+	PEX1_0x4	= 4,
+	PEX1_1x4	= 5,
+	PEX1_2x4	= 6,
+	PEX1_3x4	= 7,
+	PEX2_0x4	= 8,
+	PEX3_0x4	= 9,
+	PEXIF_MAX	= 10
 } MV_PEXIF_INDX;
 
 typedef struct {
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
index f922956..9ace2ff 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -70,6 +70,8 @@
 
 #include "ctrlEnv/sys/mvCpuIfRegs.h"
 
+#define MAX_TARGETS	(mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID ? \
+			 MAX_TARGETS_AXP : MAX_TARGETS_MSYS)
 
 #ifdef __cplusplus
 extern "C" {
@@ -321,9 +323,57 @@
 	DEV_BOOCS,	/* 23 DEV_BOOCS			*/
 	USB_REGS,	/* 24 USB Internal registers	*/
 	DRAGONITE,	/* 25 Dragonite co-processor	*/
-	MAX_TARGETS
+	MAX_TARGETS_MSYS
 } MV_TARGET;
 
+enum _mvTarget_axp {
+	SDRAM_CS0_AXP,	/*0 SDRAM chip select 0		*/
+	SDRAM_CS1_AXP,	/*1 SDRAM chip select 1		*/
+	SDRAM_CS2_AXP,	/*2 SDRAM chip select 2		*/
+	SDRAM_CS3_AXP,	/*3 SDRAM chip select 3		*/
+	DEVICE_CS0_AXP,	/*4 Device chip select 0	*/
+	DEVICE_CS1_AXP,	/*5 Device chip select 1	*/
+	DEVICE_CS2_AXP,	/*6 Device chip select 2	*/
+	DEVICE_CS3_AXP,	/*7 Device chip select 3	*/
+	PEX0_MEM_AXP,	/*8 PCI Express 0 Memory	*/
+	PEX0_IO_AXP,	/*9 PCI Express 0 IO		*/
+	PEX1_MEM,	/*10 PCI Express 1 Memory	*/
+	PEX1_IO,	/*11 PCI Express 1 IO		*/
+	PEX2_MEM,	/*12 PCI Express 2 Memory	*/
+	PEX2_IO,	/*13 PCI Express 2 IO		*/
+	PEX3_MEM,	/*14 PCI Express 3 Memory	*/
+	PEX3_IO,	/*15 PCI Express 3 IO		*/
+	PEX4_MEM,	/*16 PCI Express 4 Memory	*/
+	PEX4_IO,	/*17 PCI Express 4 IO		*/
+	PEX5_MEM,	/*18 PCI Express 5 Memory	*/
+	PEX5_IO,	/*19 PCI Express 5 IO		*/
+	PEX6_MEM,	/*20 PCI Express 6 Memory	*/
+	PEX6_IO,	/*21 PCI Express 6 IO		*/
+	PEX7_MEM,	/*22 PCI Express 7 Memory	*/
+	PEX7_IO,	/*23 PCI Express 7 IO		*/
+	PEX8_MEM,	/*24 PCI Express 8 Memory	*/
+	PEX8_IO,	/*25 PCI Express 8 IO		*/
+	PEX9_MEM,	/*26 PCI Express 9 Memory	*/
+	PEX9_IO,	/*27 PCI Express 9 IO		*/
+	INTER_REGS_AXP,	/*28 Internal registers		*/
+	DMA_UART_AXP,	/*29 DMA based UART request	*/
+	SPI_CS0_AXP,	/*30 SPI_CS0			*/
+	SPI_CS1_AXP,	/*31 SPI_CS1			*/
+	SPI_CS2_AXP,	/*32 SPI_CS2			*/
+	SPI_CS3_AXP,	/*33 SPI_CS3			*/
+	SPI_CS4_AXP,	/*34 SPI_CS4			*/
+	SPI_CS5_AXP,	/*35 SPI_CS5			*/
+	SPI_CS6_AXP,	/*36 SPI_CS6			*/
+	SPI_CS7_AXP,	/*37 SPI_CS7			*/
+	BOOT_ROM_CS_AXP, /*38 BOOT_ROM_CS		*/
+	DEV_BOOCS_AXP,	/*39 DEV_BOOCS			*/
+	PMU_SCRATCHPAD,	/*40 PMU Scratchpad		*/
+	CRYPT0_ENG,	/* 41 Crypto0 Engine		*/
+	CRYPT1_ENG,	/* 42 Crypto1 Engine		*/
+	PNC_BM,		/* 43 PNC + BM			*/
+	MAX_TARGETS_AXP
+};
+
 #ifdef AURORA_IO_CACHE_COHERENCY
 #define DRAM_CS0_ATTR		0x1E
 #define DRAM_CS1_ATTR		0x1D
@@ -397,6 +447,100 @@
 
 
 
+#define TARGETS_DEF_ARRAY_AXP	{			\
+	{DRAM_CS0_ATTR, DRAM_TARGET_ID	}, /* SDRAM_CS0 */	\
+	{DRAM_CS1_ATTR, DRAM_TARGET_ID	}, /* SDRAM_CS1 */	\
+	{DRAM_CS2_ATTR, DRAM_TARGET_ID	}, /* SDRAM_CS0 */	\
+	{DRAM_CS3_ATTR, DRAM_TARGET_ID	}, /* SDRAM_CS1 */	\
+	{0x3E, DEV_TARGET_ID	}, /* DEVICE_CS0 */	\
+	{0x3D, DEV_TARGET_ID	}, /* DEVICE_CS1 */	\
+	{0x3B, DEV_TARGET_ID	}, /* DEVICE_CS2 */	\
+	{0x37, DEV_TARGET_ID	}, /* DEVICE_CS3 */	\
+	{0xE8, PEX0_TARGET_ID	}, /* PEX0_LANE0_MEM */	\
+	{0xE0, PEX0_TARGET_ID	}, /* PEX0_LANE0_IO */	\
+	{0xD8, PEX0_TARGET_ID	}, /* PEX0_LANE1_MEM */	\
+	{0xD0, PEX0_TARGET_ID	}, /* PEX0_LANE1_IO */	\
+	{0xB8, PEX0_TARGET_ID	}, /* PEX0_LANE2_MEM */	\
+	{0xB0, PEX0_TARGET_ID	}, /* PEX0_LANE2_IO */	\
+	{0x78, PEX0_TARGET_ID	}, /* PEX0_LANE3_MEM */	\
+	{0x70, PEX0_TARGET_ID	}, /* PEX0_LANE3_IO */	\
+	{0xE8, DFX_TARGET_ID	}, /* PEX1_LANE0_MEM */	\
+	{0xE0, DFX_TARGET_ID	}, /* PEX1_LANE0_IO */	\
+	{0xD8, DFX_TARGET_ID	}, /* PEX1_LANE1_MEM */	\
+	{0xD0, DFX_TARGET_ID	}, /* PEX1_LANE1_IO */	\
+	{0xB8, DFX_TARGET_ID	}, /* PEX1_LANE2_MEM */	\
+	{0xB0, DFX_TARGET_ID	}, /* PEX1_LANE2_IO */	\
+	{0x78, DFX_TARGET_ID	}, /* PEX1_LANE3_MEM */	\
+	{0x70, DFX_TARGET_ID	}, /* PEX1_LANE3_IO */	\
+	{0xF8, PEX0_TARGET_ID	}, /* PEX2_LANE0_MEM */	\
+	{0xF0, PEX0_TARGET_ID	}, /* PEX2_LANE0_IO */	\
+	{0xF8, DFX_TARGET_ID	}, /* PEX3_LANE0_MEM */	\
+	{0xF0, DFX_TARGET_ID	}, /* PEX3_LANE0_IO */	\
+	{0xFF, 0xFF		}, /* INTER_REGS */	\
+	{0x01, DEV_TARGET_ID	}, /* DMA_UART */	\
+	{0x1E, DEV_TARGET_ID	}, /* SPI_CS0 */	\
+	{0x5E, DEV_TARGET_ID	}, /* SPI_CS1 */	\
+	{0x9E, DEV_TARGET_ID	}, /* SPI_CS2 */	\
+	{0xDE, DEV_TARGET_ID	}, /* SPI_CS3 */	\
+	{0x1F, DEV_TARGET_ID	}, /* SPI_CS4 */	\
+	{0x5F, DEV_TARGET_ID	}, /* SPI_CS5 */	\
+	{0x9F, DEV_TARGET_ID	}, /* SPI_CS6 */	\
+	{0xDF, DEV_TARGET_ID	}, /* SPI_CS7 */	\
+	{0x1D, DEV_TARGET_ID	}, /* Main Boot device */	\
+	{0x2F, DEV_TARGET_ID	}, /* Secondary Boot device, */	\
+	{0x2D, DEV_TARGET_ID	}, /* PMU_SCRATCHPAD */	\
+	{0x09, CRYPT_TARGET_ID	}, /* CRYPT_ENG0 */	\
+	{0x05, CRYPT_TARGET_ID	}, /* CRYPT_ENG1 */     \
+	{0x00, PNC_BM_TARGET_ID	}, /* PNC_BM */		\
+}
+
+#define TARGETS_NAME_ARRAY_AXP	{		\
+	"SDRAM_CS0",	/* SDRAM_CS0 */		\
+	"SDRAM_CS1",	/* SDRAM_CS1 */		\
+	"SDRAM_CS2",	/* SDRAM_CS1 */		\
+	"SDRAM_CS3",	/* SDRAM_CS1 */		\
+	"DEVICE_CS0",	/* DEVICE_CS0 */	\
+	"DEVICE_CS1",	/* DEVICE_CS1 */	\
+	"DEVICE_CS2",	/* DEVICE_CS2 */	\
+	"DEVICE_CS3",	/* DEVICE_CS3 */	\
+	"PEX0_MEM",	/* PEX0_MEM */		\
+	"PEX0_IO",	/* PEX0_IO */		\
+	"PEX1_MEM",	/* PEX1_MEM */		\
+	"PEX1_IO",	/* PEX1_IO */		\
+	"PEX2_MEM",	/* PEX2_MEM */		\
+	"PEX2_IO",	/* PEX2_IO */		\
+	"PEX3_MEM",	/* PEX3_MEM */		\
+	"PEX3_IO",	/* PEX3_IO */		\
+	"PEX4_MEM",	/* PEX4_MEM */		\
+	"PEX4_IO",	/* PEX4_IO */		\
+	"PEX5_MEM",	/* PEX5_MEM */		\
+	"PEX5_IO",	/* PEX5_IO */		\
+	"PEX6_MEM",	/* PEX6_MEM */		\
+	"PEX6_IO",	/* PEX6_IO */		\
+	"PEX7_MEM",	/* PEX7_MEM */		\
+	"PEX7_IO",	/* PEX7_IO */		\
+	"PEX8_MEM",	/* PEX8_MEM */		\
+	"PEX8_IO",	/* PEX8_IO */		\
+	"PEX9_MEM",	/* PEX9_MEM */		\
+	"PEX9_IO",	/* PEX9_IO */		\
+	"INTER_REGS",	/* INTER_REGS */	\
+	"DMA_UART",	/* DMA_UART */		\
+	"SPI_CS0",	/* SPI_CS0 */		\
+	"SPI_CS1",	/* SPI_CS1 */		\
+	"SPI_CS2",	/* SPI_CS2 */		\
+	"SPI_CS3",	/* SPI_CS3 */		\
+	"SPI_CS4",	/* SPI_CS4 */		\
+	"SPI_CS5",	/* SPI_CS5 */		\
+	"SPI_CS6",	/* SPI_CS6 */		\
+	"SPI_CS7",	/* SPI_CS7 */		\
+	"BOOT_ROM_CS",	/* BOOT_ROM_CS */	\
+	"DEV_BOOTCS",	/* DEV_BOOCS */		\
+	"PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */	\
+	"CRYPT1_ENG",	/* CRYPT1_ENG */	\
+	"CRYPT2_ENG",	/* CRYPT2_ENG */	\
+	"PNC_BM"	/* PNC_BM */		\
+}
+
 #endif /* MV_ASMLANGUAGE */
 
 #ifdef __cplusplus
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
index e4608ab..0229d22 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
@@ -255,7 +255,10 @@
 
 	if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) {
 		pAddrDecWin->addrWin.size = INTER_REGS_SIZE;
-		pAddrDecWin->target = INTER_REGS;
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+			pAddrDecWin->target = (MV_U8)INTER_REGS_AXP;
+		else
+			pAddrDecWin->target = INTER_REGS;
 		pAddrDecWin->enable = MV_TRUE;
 
 		return MV_OK;
@@ -301,7 +304,7 @@
 		return 0xffffffff;
 	}
 
-	if (INTER_REGS == target)
+	if (INTER_REGS == target || (MV_U8)INTER_REGS_AXP == target)
 		return MV_AHB_TO_MBUS_INTREG_WIN;
 
 	for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) {
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
index 6149eb9..c50a79b 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
@@ -156,7 +156,7 @@
 	/* Set IO Bypass base address and size according to the cpuAddrWinMap */
 	for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) {
 		if ((MV_TARGET_IS_DRAM(target)) || (DIS == cpuAddrWinMap[target].enable) ||
-		    (target == INTER_REGS))
+		    (target == INTER_REGS) || (target == (MV_U8)INTER_REGS_AXP))
 			continue;
 		if (cpuAddrWinMap[target].addrWin.baseLow == 0)
 			continue;
@@ -190,7 +190,8 @@
 
 	/* First disable all CPU target windows  */
 	for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) {
-		if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS))
+		if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS) ||
+		    (target == (MV_U8)INTER_REGS_AXP))
 			continue;
 
 #if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA)
diff --git a/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h b/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
index 413abd8..69bd8aa 100644
--- a/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
+++ b/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
@@ -76,6 +76,8 @@
 	switch (num) {
 	case (DEV_BOOCS):
 		return MV_DEV_BUS_REGS_OFFSET + 0x00;
+	case (DEV_BOOCS_AXP):
+		return MV_DEV_BUS_REGS_OFFSET + 0x00;
 	case (DEVICE_CS0):
 		return MV_DEV_BUS_REGS_OFFSET + 0x08;
 	case (DEVICE_CS1):