ddr4: ddr3libv2 compilation by default also for DDR4
by default all new TIP SoCs will recompiled ddr3libv2 source in DDR4 mode too.
This patch change( to brake dependency of ddr3libv2 from ddr4src code):
in tools added updated libs abd sublibs, changed name of mvDdrTopologyDef.h
in ddr3libv3 removed all includes to internal DDR4 headers,
all requered declaration set in ddr3libv2 headers
extern all DDR4 functions called from ddr3libv2 code.
Change-Id: I31e013f3a4101c5278c7c21017521c5ec9db893f
Signed-off-by: Igor Petrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19295
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Star_Automation <star@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24125
Reviewed-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/inc/common/mvDdrTopologyDef.h b/tools/marvell/bin_hdr/inc/common/mvDdrTopologyDef.h
new file mode 100644
index 0000000..65e44b3
--- /dev/null
+++ b/tools/marvell/bin_hdr/inc/common/mvDdrTopologyDef.h
@@ -0,0 +1,276 @@
+
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef _DDR3_TOPOLOGY_CONFIG_H
+#define _DDR3_TOPOLOGY_CONFIG_H
+
+#define ADDR_SIZE_512Mb 0x04000000
+#define ADDR_SIZE_1Gb 0x08000000
+#define ADDR_SIZE_2Gb 0x10000000
+#define ADDR_SIZE_4Gb 0x20000000
+#define ADDR_SIZE_8Gb 0x40000000
+
+
+/*************************TOPOLOGY*******************************************/
+#ifdef CONFIG_DDR3
+
+typedef enum
+{
+ SPEED_BIN_DDR_800D,
+ SPEED_BIN_DDR_800E,
+ SPEED_BIN_DDR_1066E,
+ SPEED_BIN_DDR_1066F,
+ SPEED_BIN_DDR_1066G,
+ SPEED_BIN_DDR_1333F,
+ SPEED_BIN_DDR_1333G,
+ SPEED_BIN_DDR_1333H,
+ SPEED_BIN_DDR_1333J,
+ SPEED_BIN_DDR_1600G,
+ SPEED_BIN_DDR_1600H,
+ SPEED_BIN_DDR_1600J,
+ SPEED_BIN_DDR_1600K,
+ SPEED_BIN_DDR_1866J,
+ SPEED_BIN_DDR_1866K,
+ SPEED_BIN_DDR_1866L,
+ SPEED_BIN_DDR_1866M,
+ SPEED_BIN_DDR_2133K,
+ SPEED_BIN_DDR_2133L,
+ SPEED_BIN_DDR_2133M,
+ SPEED_BIN_DDR_2133N,
+
+ SPEED_BIN_DDR_1333H_EXT,
+ SPEED_BIN_DDR_1600K_EXT,
+ SPEED_BIN_DDR_1866M_EXT
+}MV_HWS_SPEED_BIN;
+
+typedef enum
+{
+ DDR_FREQ_LOW_FREQ,
+ DDR_FREQ_400,
+ DDR_FREQ_533,
+ DDR_FREQ_667,
+ DDR_FREQ_800,
+ DDR_FREQ_933,
+ DDR_FREQ_1066,
+ DDR_FREQ_311,
+ DDR_FREQ_333,
+ DDR_FREQ_467,
+ DDR_FREQ_850,
+ DDR_FREQ_600,
+ DDR_FREQ_300,
+ DDR_FREQ_900,
+ DDR_FREQ_360,
+ DDR_FREQ_1000,
+ DDR_FREQ_LIMIT
+}MV_HWS_DDR_FREQ;
+
+#else
+typedef enum
+{
+ SPEED_BIN_DDR_1600J,
+ SPEED_BIN_DDR_1600K,
+ SPEED_BIN_DDR_1600L,
+ SPEED_BIN_DDR_1866L,
+ SPEED_BIN_DDR_1866M,
+ SPEED_BIN_DDR_1866N,
+ SPEED_BIN_DDR_2133N,
+ SPEED_BIN_DDR_2133P,
+ SPEED_BIN_DDR_2133R,
+ SPEED_BIN_DDR_2400P,
+ SPEED_BIN_DDR_2400R,
+ SPEED_BIN_DDR_2400U,
+}MV_HWS_SPEED_BIN;
+
+typedef enum
+{
+ DDR_FREQ_LOW_FREQ,
+ DDR_FREQ_667,
+ DDR_FREQ_800,
+ DDR_FREQ_933,
+ DDR_FREQ_1066,
+ DDR_FREQ_900,
+ DDR_FREQ_LIMIT
+}MV_HWS_DDR_FREQ;
+
+#endif
+
+typedef enum
+{
+ DDR_BOARD_ETP,
+ DDR_BOARD_FUNCTIONAL,
+ DDR_BOARD_CUSTOMER,
+ DDR_BOARD_MAX
+
+} MV_HWS_DDR_BOARD;
+
+/* bus width in bits */
+typedef enum
+{
+ BUS_WIDTH_4,
+ BUS_WIDTH_8,
+ BUS_WIDTH_16,
+ BUS_WIDTH_32
+
+} MV_HWS_BUS_WIDTH;
+
+typedef enum
+{
+ MEM_512M,
+ MEM_1G,
+ MEM_2G,
+ MEM_4G,
+ MEM_8G,
+
+ MEM_SIZE_LAST
+}MV_HWS_MEM_SIZE;
+
+typedef enum
+{
+ MV_HWS_TEMP_LOW,
+ MV_HWS_TEMP_NORMAL,
+ MV_HWS_TEMP_HIGH
+
+}MV_HWS_TEMPERTURE;
+
+typedef struct
+{
+ /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
+ MV_U8 csBitmask;
+
+ /* mirror enable/disable (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)*/
+ MV_BOOL mirrorEnableBitmask;
+
+ /* DQS Swap (polarity) - true if enable*/
+ MV_BOOL isDqsSwap;
+
+ /* CK swap (polarity) - true if enable*/
+ MV_BOOL isCkSwap;
+
+} BusParams;
+
+typedef struct
+{
+ /* bus configuration */
+ BusParams asBusParams[MAX_BUS_NUM];
+
+ /* Speed Bin Table*/
+ MV_HWS_SPEED_BIN speedBinIndex;
+
+ /* bus width of memory device*/
+ MV_HWS_BUS_WIDTH busWidth;
+
+ /* Bus memory size (MBit) */
+ MV_HWS_MEM_SIZE memorySize;
+
+ /* The DDR frequency for each interfaces */
+ MV_HWS_DDR_FREQ memoryFreq;
+
+ /* delay CAS Write Latency - 0 for using default value (jedec suggested) */
+ MV_U8 casWL;
+
+ /* delay CAS Latency - 0 for using default value (jedec suggested) */
+ MV_U8 casL;
+
+ /* operation temperature */
+ MV_HWS_TEMPERTURE interfaceTemp;
+
+} InterfaceParams;
+
+/***********************************/
+
+typedef struct
+{
+ /* Number of interfaces (default is 12)*/
+ MV_U8 interfaceActiveMask;
+
+ /* Controller configuration per interface */
+ InterfaceParams interfaceParams[MAX_INTERFACE_NUM];
+
+ /* Bit mask for active buses defined interface width and ECC configuration*/
+ MV_U8 activeBusMask;
+
+} MV_HWS_TOPOLOGY_MAP;
+
+typedef struct
+{
+ MV_U32 ckDelay; /*the delay between clock to C/A for by8 devices*/
+ MV_U32 PhyReg3Val; /*Initial value of RX centralization phy reg*/
+
+ MV_U32 gZpriData; /*Controller Data P drive strength*/
+ MV_U32 gZnriData; /*Controller Data N drive strength*/
+ MV_U32 gZpriCtrl; /*Controller C/A P drive strength*/
+ MV_U32 gZnriCtrl; /*Controller C/A N drive strength*/
+ MV_U32 gZpodtData; /*Controller Data P ODT at the receive*/
+ MV_U32 gZnodtData; /*Controller Data N ODT at the receive*/
+ MV_U32 gZpodtCtrl; /*Controller C/A P ODT at the receive*/
+ MV_U32 gZnodtCtrl; /*Controller C/A N ODT at the receive*/
+ MV_U32 gDic; /*Memory drive strength*/
+ MV_U32 uiODTConfig; /*ODT Pin Configuration*/
+ MV_U32 gRttNom; /*Memory ODT at the receive*/
+ MV_U32 gRttWR; /*Memory ODT at the receive during write*/
+} MV_TUNE_TRAINING_PARAMS;
+
+#endif /* _DDR3_TOPOLOGY_CONFIG_H */
+
+
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
index 60ca48e..38c7b60 100755
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
@@ -66,7 +66,7 @@
#define _INC_A38X_VARS_H
#include "ddr3_a38x_mc_static.h"
-#include "mvDdr3TopologyDef.h"
+#include "mvDdrTopologyDef.h"
/* to run DDR viewer tool (including BIST) uncomment the define
#define MV_RUN_WIN_VALIDATION_TEST */
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a39x/ddr3_a39x_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a39x/ddr3_a39x_vars.h
index bd575ee..d04d1f7 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a39x/ddr3_a39x_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a39x/ddr3_a39x_vars.h
@@ -66,7 +66,7 @@
#define _INC_A39X_VARS_H
#include "ddr3_a39x_mc_static.h"
-#include "mvDdr3TopologyDef.h"
+#include "mvDdrTopologyDef.h"
typedef struct __mvDramModes {
char *mode_name;
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
index e99532e..7f6959e 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
@@ -67,7 +67,7 @@
#include "ddr3_msys_ac3_config.h"
#include "ddr3_msys_ac3_mc_static.h"
-#include "mvDdr3TopologyDef.h"
+#include "mvDdrTopologyDef.h"
#if !defined(CONFIG_CUSTOMER_BOARD_SUPPORT)
#define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
index 78b6f3f..15d090c 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
@@ -66,7 +66,7 @@
#define _INC_MSYS_BC2_VARS_H
#include "ddr3_msys_bc2_config.h"
-#include "mvDdr3TopologyDef.h"
+#include "mvDdrTopologyDef.h"
/*Tune internal training params values*/
#define MV_TUNE_TRAINING_PARAMS_CK_DELAY 150
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TopologyDef.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TopologyDef.h
deleted file mode 100644
index da82e24..0000000
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TopologyDef.h
+++ /dev/null
@@ -1,140 +0,0 @@
-
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef _MV_DDR3_TOPOLOGY_DEF_H
-#define _MV_DDR3_TOPOLOGY_DEF_H
-
-
-/*************************TOPOLOGY*******************************************/
-#ifdef CONFIG_DDR3
-typedef enum
-{
- SPEED_BIN_DDR_800D,
- SPEED_BIN_DDR_800E,
- SPEED_BIN_DDR_1066E,
- SPEED_BIN_DDR_1066F,
- SPEED_BIN_DDR_1066G,
- SPEED_BIN_DDR_1333F,
- SPEED_BIN_DDR_1333G,
- SPEED_BIN_DDR_1333H,
- SPEED_BIN_DDR_1333J,
- SPEED_BIN_DDR_1600G,
- SPEED_BIN_DDR_1600H,
- SPEED_BIN_DDR_1600J,
- SPEED_BIN_DDR_1600K,
- SPEED_BIN_DDR_1866J,
- SPEED_BIN_DDR_1866K,
- SPEED_BIN_DDR_1866L,
- SPEED_BIN_DDR_1866M,
- SPEED_BIN_DDR_2133K,
- SPEED_BIN_DDR_2133L,
- SPEED_BIN_DDR_2133M,
- SPEED_BIN_DDR_2133N,
-
- SPEED_BIN_DDR_1333H_EXT,
- SPEED_BIN_DDR_1600K_EXT,
- SPEED_BIN_DDR_1866M_EXT
-}MV_HWS_SPEED_BIN;
-
-typedef enum
-{
- DDR_FREQ_LOW_FREQ,
- DDR_FREQ_400,
- DDR_FREQ_533,
- DDR_FREQ_667,
- DDR_FREQ_800,
- DDR_FREQ_933,
- DDR_FREQ_1066,
- DDR_FREQ_311,
- DDR_FREQ_333,
- DDR_FREQ_467,
- DDR_FREQ_850,
- DDR_FREQ_600,
- DDR_FREQ_300,
- DDR_FREQ_900,
- DDR_FREQ_360,
- DDR_FREQ_1000,
- DDR_FREQ_LIMIT
-}MV_HWS_DDR_FREQ;
-
-typedef enum
-{
- speedBinTableElements_tRCD,
- speedBinTableElements_tRP,
- speedBinTableElements_tRAS,
- speedBinTableElements_tRC,
- speedBinTableElements_tRRD1K,
- speedBinTableElements_tRRD2K,
- speedBinTableElements_tPD,
- speedBinTableElements_tFAW1K,
- speedBinTableElements_tFAW2K,
- speedBinTableElements_tWTR,
- speedBinTableElements_tRTP,
- speedBinTableElements_tWR,
- speedBinTableElements_tMOD
-}speedBinTableElements;
-#endif /*CONFIG_DDR3 */
-#endif /* _MV_DDR3_TOPOLOGY_DEF_H */
-
-
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpDb.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpDb.h
deleted file mode 100755
index 331fb11..0000000
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpDb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/******************************************************************************
-* Copyright (c) Marvell International Ltd. and its affiliates
-*
-* This software file (the "File") is owned and distributed by Marvell
-* International Ltd. and/or its affiliates ("Marvell") under the following
-* alternative licensing terms.
-* If you received this File from Marvell, you may opt to use, redistribute
-* and/or modify this File under the following licensing terms.
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* - Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* - Neither the name of Marvell nor the names of its contributors may be
-* used to endorse or promote products derived from this software without
-* specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************
-* mvDdr3TrainingIpDb.h
-*
-* DESCRIPTION:
-*
-*
-* FILE REVISION NUMBER:
-* $Revision: 3 $
-*
-*******************************************************************************/
-
-#ifndef _MV_DDR3_TRAININGIP_DB_H_
-#define _MV_DDR3_TRAININGIP_DB_H_
-
-#ifdef __cplusplus
- extern "C"
- {
-#endif
-
-/************************** enums ******************************/
-
-typedef enum
-{
- PATTERN_PBS1,
- PATTERN_PBS2,
- PATTERN_RL,
- PATTERN_STATIC_PBS,
- PATTERN_KILLER_DQ0,
- PATTERN_KILLER_DQ1,
- PATTERN_KILLER_DQ2,
- PATTERN_KILLER_DQ3,
- PATTERN_KILLER_DQ4,
- PATTERN_KILLER_DQ5,
- PATTERN_KILLER_DQ6,
- PATTERN_KILLER_DQ7,
- PATTERN_PBS3,
- PATTERN_RL2,
- PATTERN_TEST,
- PATTERN_FULL_SSO0,
- PATTERN_FULL_SSO1,
- PATTERN_FULL_SSO2,
- PATTERN_FULL_SSO3,
- PATTERN_VREF,
- PATTERN_LIMIT
-} MV_HWS_PATTERN;
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _MV_DDR3_TRAININGIP_DB_H_ */
-
-
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
index 0bacc9e..9955dd3 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
@@ -47,9 +47,6 @@
#include "mvDdr3TrainingIp.h"
#include "mvDdr3TrainingIpPbs.h"
-#ifdef CONFIG_DDR4
-#include "mvDdr4TrainingIpFlow.h"
-#endif
#ifdef __cplusplus
extern "C"
@@ -380,9 +377,23 @@
#define CS_PBS_GAP(csNum) (csNum*0x10)
#define ADLL_LENGTH (32)
+#ifdef CONFIG_DDR4
+/* DDR4 MRS */
+#define MRS4_CMD (0x10)
+#define MRS5_CMD (0X11)
+#define MRS6_CMD (0X12)
-/************************* Enums ***********************************************/
-
+/* DDR4 Registers */
+#define DDR4_MR0_REG (0x1900)
+#define DDR4_MR1_REG (0x1904)
+#define DDR4_MR2_REG (0x1908)
+#define DDR4_MR3_REG (0x190C)
+#define DDR4_MR4_REG (0x1910)
+#define DDR4_MR5_REG (0x1914)
+#define DDR4_MR6_REG (0x1918)
+#define DDR4_MPR_WR_REG (0x19D0)
+#define DRAM_PINS_MUX_REG (0x19D4)
+#endif
/************************* Structures ***********************************************/
@@ -403,6 +414,56 @@
/* Mask used in register */
}PageElement;
+#ifdef CONFIG_DDR4
+/******************************************************************************
+* Name: ddr4TipDynamicWriteLevelingSupp
+* Desc: Write leveling phase correction
+* Args: devNum - device number
+*
+* Notes:
+* Returns: OK if success, other error code if fail.
+*/
+GT_STATUS ddr4TipDynamicWriteLevelingSupp
+(
+ GT_U32 devNum
+);
+
+GT_STATUS ddr4TipConfigurePhy
+(
+ GT_U32 devNum
+);
+
+GT_STATUS ddr4TipSetTiming
+(
+ GT_U32 devNum,
+ MV_HWS_ACCESS_TYPE accessType,
+ GT_U32 interfaceId,
+ MV_HWS_DDR_FREQ frequency
+);
+
+GT_STATUS ddr4ModeRegsInit
+(
+ GT_U8 devNum
+);
+
+GT_STATUS ddr4SdramConfig
+(
+ GT_U32 devNum
+);
+
+GT_STATUS ddr4TipCalibrationAdjust
+(
+ GT_U32 devNum,
+ GT_U8 Vref_en,
+ GT_U8 POD_Only
+);
+
+GT_STATUS ddr3TipDDR4Ddr4TrainingMainFlow
+(
+ GT_U32 devNum
+);
+
+#endif
/******************************************************************************
* Name: ddr3TipWriteLevelingStaticConfig.
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
index a41b4dd..4557e06 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTopologyDef.h
@@ -69,9 +69,126 @@
#include "mvDdr3TrainingIpDef.h"
#ifdef CONFIG_DDR3
-#include "mvDdr3TopologyDef.h"
+typedef enum
+{
+ SPEED_BIN_DDR_800D,
+ SPEED_BIN_DDR_800E,
+ SPEED_BIN_DDR_1066E,
+ SPEED_BIN_DDR_1066F,
+ SPEED_BIN_DDR_1066G,
+ SPEED_BIN_DDR_1333F,
+ SPEED_BIN_DDR_1333G,
+ SPEED_BIN_DDR_1333H,
+ SPEED_BIN_DDR_1333J,
+ SPEED_BIN_DDR_1600G,
+ SPEED_BIN_DDR_1600H,
+ SPEED_BIN_DDR_1600J,
+ SPEED_BIN_DDR_1600K,
+ SPEED_BIN_DDR_1866J,
+ SPEED_BIN_DDR_1866K,
+ SPEED_BIN_DDR_1866L,
+ SPEED_BIN_DDR_1866M,
+ SPEED_BIN_DDR_2133K,
+ SPEED_BIN_DDR_2133L,
+ SPEED_BIN_DDR_2133M,
+ SPEED_BIN_DDR_2133N,
+
+ SPEED_BIN_DDR_1333H_EXT,
+ SPEED_BIN_DDR_1600K_EXT,
+ SPEED_BIN_DDR_1866M_EXT
+}MV_HWS_SPEED_BIN;
+
+typedef enum
+{
+ DDR_FREQ_LOW_FREQ,
+ DDR_FREQ_400,
+ DDR_FREQ_533,
+ DDR_FREQ_667,
+ DDR_FREQ_800,
+ DDR_FREQ_933,
+ DDR_FREQ_1066,
+ DDR_FREQ_311,
+ DDR_FREQ_333,
+ DDR_FREQ_467,
+ DDR_FREQ_850,
+ DDR_FREQ_600,
+ DDR_FREQ_300,
+ DDR_FREQ_900,
+ DDR_FREQ_360,
+ DDR_FREQ_1000,
+ DDR_FREQ_LIMIT
+}MV_HWS_DDR_FREQ;
+
+typedef enum
+{
+ speedBinTableElements_tRCD,
+ speedBinTableElements_tRP,
+ speedBinTableElements_tRAS,
+ speedBinTableElements_tRC,
+ speedBinTableElements_tRRD1K,
+ speedBinTableElements_tRRD2K,
+ speedBinTableElements_tPD,
+ speedBinTableElements_tFAW1K,
+ speedBinTableElements_tFAW2K,
+ speedBinTableElements_tWTR,
+ speedBinTableElements_tRTP,
+ speedBinTableElements_tWR,
+ speedBinTableElements_tMOD
+}speedBinTableElements;
+
#elif defined(CONFIG_DDR4)
-#include "mvDdr4TopologyDef.h"
+
+typedef enum
+{
+ SPEED_BIN_DDR_1600J,
+ SPEED_BIN_DDR_1600K,
+ SPEED_BIN_DDR_1600L,
+ SPEED_BIN_DDR_1866L,
+ SPEED_BIN_DDR_1866M,
+ SPEED_BIN_DDR_1866N,
+ SPEED_BIN_DDR_2133N,
+ SPEED_BIN_DDR_2133P,
+ SPEED_BIN_DDR_2133R,
+ SPEED_BIN_DDR_2400P,
+ SPEED_BIN_DDR_2400R,
+ SPEED_BIN_DDR_2400U,
+}MV_HWS_SPEED_BIN;
+
+typedef enum
+{
+ DDR_FREQ_LOW_FREQ,
+ DDR_FREQ_667,
+ DDR_FREQ_800,
+ DDR_FREQ_933,
+ DDR_FREQ_1066,
+ DDR_FREQ_900,
+ DDR_FREQ_1000,
+ DDR_FREQ_LIMIT
+}MV_HWS_DDR_FREQ;
+
+typedef enum
+{
+ speedBinTableElements_tRCD,
+ speedBinTableElements_tRP,
+ speedBinTableElements_tRAS,
+ speedBinTableElements_tRC,
+ speedBinTableElements_tRRD0_5K,
+ speedBinTableElements_tRRD1K,
+ speedBinTableElements_tRRD2K,
+ speedBinTableElements_tRRDL0_5K,
+ speedBinTableElements_tRRDL1K,
+ speedBinTableElements_tRRDL2K,
+ speedBinTableElements_tPD,
+ speedBinTableElements_tFAW0_5K,
+ speedBinTableElements_tFAW1K,
+ speedBinTableElements_tFAW2K,
+ speedBinTableElements_tWTR,
+ speedBinTableElements_tWTRL,
+ speedBinTableElements_tRTP,
+ speedBinTableElements_tWR,
+ speedBinTableElements_tMOD
+}speedBinTableElements;
+
#else
# error "CONFIG_DDR3 or CONFIG_DDR4 must be defined !!!"
#endif
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
index 3b78111..e2ba6e1 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
@@ -47,9 +47,73 @@
#include "mvDdrTopologyDef.h"
#ifdef CONFIG_DDR3
-#include "mvDdr3TrainingIpDb.h"
+typedef enum
+{
+ PATTERN_PBS1,
+ PATTERN_PBS2,
+ PATTERN_RL,
+ PATTERN_STATIC_PBS,
+ PATTERN_KILLER_DQ0,
+ PATTERN_KILLER_DQ1,
+ PATTERN_KILLER_DQ2,
+ PATTERN_KILLER_DQ3,
+ PATTERN_KILLER_DQ4,
+ PATTERN_KILLER_DQ5,
+ PATTERN_KILLER_DQ6,
+ PATTERN_KILLER_DQ7,
+ PATTERN_PBS3,
+ PATTERN_RL2,
+ PATTERN_TEST,
+ PATTERN_FULL_SSO0,
+ PATTERN_FULL_SSO1,
+ PATTERN_FULL_SSO2,
+ PATTERN_FULL_SSO3,
+ PATTERN_VREF,
+ PATTERN_LIMIT
+} MV_HWS_PATTERN;
#elif defined(CONFIG_DDR4)
-#include "mvDdr4TrainingIpDb.h"
+typedef enum
+{
+ PATTERN_PBS1,
+ PATTERN_PBS2,
+ PATTERN_RL,
+ PATTERN_STATIC_PBS,
+ PATTERN_KILLER_DQ0,
+ PATTERN_KILLER_DQ1,
+ PATTERN_KILLER_DQ2,
+ PATTERN_KILLER_DQ3,
+ PATTERN_KILLER_DQ4,
+ PATTERN_KILLER_DQ5,
+ PATTERN_KILLER_DQ6,
+ PATTERN_KILLER_DQ7,
+ PATTERN_KILLER_DQ0_INV,
+ PATTERN_KILLER_DQ1_INV,
+ PATTERN_KILLER_DQ2_INV,
+ PATTERN_KILLER_DQ3_INV,
+ PATTERN_KILLER_DQ4_INV,
+ PATTERN_KILLER_DQ5_INV,
+ PATTERN_KILLER_DQ6_INV,
+ PATTERN_KILLER_DQ7_INV,
+ PATTERN_VREF,
+ PATTERN_VREF_INV,
+ PATTERN_RESONANCE_1T,
+ PATTERN_RESONANCE_2T,
+ PATTERN_RESONANCE_3T,
+ PATTERN_RESONANCE_4T,
+ PATTERN_RESONANCE_5T,
+ PATTERN_RESONANCE_6T,
+ PATTERN_RESONANCE_7T,
+ PATTERN_RESONANCE_8T,
+ PATTERN_RESONANCE_9T,
+ PATTERN_PBS3,
+ PATTERN_RL2,
+ PATTERN_TEST,
+ PATTERN_FULL_SSO0,
+ PATTERN_FULL_SSO1,
+ PATTERN_FULL_SSO2,
+ PATTERN_FULL_SSO3,
+ PATTERN_LIMIT
+}MV_HWS_PATTERN;
#else
#error "CONFIG_DDR3 or CONFIG_DDR4 must be defined !!!"
#endif
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 237ba01..6009d82 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -31,10 +31,6 @@
#include "mvDdr3TrainingIpPrvIf.h"
#include "mvDdr3LoggingDef.h"
-#ifdef CONFIG_DDR4
-#include "mvHwsDdr4Training.h"
-#include "mvHwsDdr4MprPdaIf.h"
-#endif
/************************** definitions ******************************/
#ifdef FreeRTOS
#define DFX_BAR1_BASE (0x80000000)
@@ -50,7 +46,6 @@
/*#define TIME_2_CLOCK_CYCLES(prm, clk) ((prm-1)/clk)*/
#define TIME_2_CLOCK_CYCLES CEIL_DIVIDE
-
#define GET_CS_FROM_MASK(mask) (csMask2Num[mask])
#define CS_CBE_VALUE(csNum) (csCbeReg[csNum])
@@ -105,11 +100,6 @@
GT_U32 delayEnable = 0;
static GT_U32 freqMask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
GT_BOOL rlMidFreqWA = GT_FALSE;
-extern GT_U32 ddr4TipConfigurePhyVrefTap;
-
-#ifdef CONFIG_DDR4
-extern GT_U8 vrefCalibrationWA; /*1 means SSTL & POD gets the same Vref and a WA is needed*/
-#endif
GT_U32 vrefInitialValue = 0x4;
GT_U32 ckDelay = MV_PARAMS_UNDEFINED;
@@ -332,12 +322,7 @@
return DDR3_TIP_VERSION_STRING;
}
-#ifdef CONFIG_DDR4
-const GT_CHAR* mvHwsDdr4SubLibVersionGet(void)
-{
- return DDR4_TIP_SUBVERSION_STRING;
-}
-#endif
+extern const GT_CHAR* mvHwsDdr4SubLibVersionGet(void);
void ddr3PrintVersion()
{
@@ -755,14 +740,7 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, CALIB_MACHINE_CTRL_REG, calibrationUpdateControl<<3, 0x3<<3));
}
#ifdef CONFIG_DDR4
- if(vrefCalibrationWA == 0){
- CHECK_STATUS(ddr4TipCalibrationValidate(devNum));
- }
- else{
- CHECK_STATUS(ddr4TipCalibrationAdjust(devNum, ddr4TipConfigurePhyVrefTap,1,0));/*devNum,VrefTap,Vref_en,POD_Only*/
- }
- ddr4ModeRegsInit(devNum);
- ddr4SdramConfig(devNum);
+ CHECK_STATUS(ddr4TipCalibrationAdjust(devNum, 1,0));/*devNum,VrefTap,Vref_en,POD_Only*/
#endif
CHECK_STATUS(ddr3TipEnableInitSequence(devNum));
@@ -2673,46 +2651,6 @@
}
}
-#ifdef CONFIG_DDR4__NOT_USED
- if (maskTuneFunc & PER_BIT_READ_LEVELING_TF_MASK_BIT)
- {
- trainingStage = PER_BIT_READ_LEVELING_TF;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("PER_BIT_READ_LEVELING_TF_MASK_BIT \n"));
- retVal = ddr3TipDynamicPerBitReadLeveling(devNum, topologyMap->interfaceParams[firstActiveIf].memoryFreq);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr3TipDynamicPerBitReadLeveling TF failure \n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
- }
-
- if (maskTuneFunc & SW_READ_LEVELING_MASK_BIT)
- {
- trainingStage = SW_READ_LEVELING;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("SW_READ_LEVELING_MASK_BIT\n"));
- retVal = ddr4TipSoftwareReadLeveling(devNum, mediumFreq);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr4TipSoftwareReadLeveling failure \n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
- }
-#endif /* CONFIG_DDR4 */
-
#ifdef CONFIG_DDR3
if (maskTuneFunc & DM_PBS_TX_MASK_BIT)
{
@@ -2789,81 +2727,7 @@
#ifdef CONFIG_DDR4
for(effective_cs = 0; effective_cs < max_cs; effective_cs++){
- if (maskTuneFunc & RECEIVER_CALIBRATION_MASK_BIT)
- {
- trainingStage = RECEIVER_CALIBRATION;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("RECEIVER_CALIBRATION_MASK_BIT #%d\n", effective_cs));
- retVal = ddr4TipReceiverCalibration(devNum);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr4TipReceiverCalibration failure \n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
- }
-
- if (maskTuneFunc & WL_PHASE_CORRECTION_MASK_BIT)
- {
- trainingStage = WL_PHASE_CORRECTION;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("WL_PHASE_CORRECTION_MASK_BIT #%d\n", effective_cs));
- retVal = ddr4TipDynamicWriteLevelingSupp(devNum);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr4TipDynamicWriteLevelingSupp failure\n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
- }
-
- if (maskTuneFunc & DQ_VREF_CALIBRATION_MASK_BIT)
- {
- trainingStage = DQ_VREF_CALIBRATION;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DQ_VREF_CALIBRATION_MASK_BIT #%d\n", effective_cs));
- retVal = ddr4TipDqVrefCalibration(devNum);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr4TipDqVrefCalibration failure\n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
- }
- }
- effective_cs = 0;
- if (maskTuneFunc & DQ_MAPPING_MASK_BIT)
- {
- trainingStage = DQ_MAPPING;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DQ_MAPPING_MASK_BIT\n"));
- retVal = ddr4DqPinsMapping(devNum);
- if (isRegDump != 0)
- {
- ddr3TipRegDump(devNum);
- }
- if (retVal != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("ddr4DqPinsMapping failure\n"));
- if (debugMode == GT_FALSE)
- {
- return GT_FAIL;
- }
- }
+ CHECK_STATUS(ddr3TipDDR4Ddr4TrainingMainFlow(devNum));
}
#endif
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
index dcfbbb9..88fe281 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
@@ -29,10 +29,6 @@
#include "mvDdr3TrainingIpPrvIf.h"
#include "mvDdr3LoggingDef.h"
-#ifdef CONFIG_DDR4
-#include "mvHwsDdr4Training.h"
-#endif
-
extern MV_HWS_TOPOLOGY_MAP *topologyMap;
extern GT_U32 clampTbl[MAX_INTERFACE_NUM];
