| commit | 6506608adeab6ae211b1995770da420491e4ffab | [log] [tgz] |
|---|---|---|
| author | hayim <hayim@marvell.com> | Sat Oct 10 21:37:32 2015 +0300 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | 3d6029e4986994627949680e21b57762c763bba4 | |
| parent | c90e99bcd3eefaf9bf38637d71cf94f1ff74f533 [diff] |
ddr3libv2: fix: increas ODPG polling x10 for DDR4
this is done due to A390 DB-GP DDR4 failure
Change-Id: Ide56711a53c273dfdb1b3d83dfc46c35233f7660
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23914
Tested-by: Star_Automation <star@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24170
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c index 53bf008..55b429c 100755 --- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c +++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -306,11 +306,16 @@ MV_HWS_EdgeCompare trainEdgeCompare; GT_U32 trainCsNum; GT_U32 trainIfAcess, trainIfId, trainPupAccess; +#ifdef CONFIG_DDR4 +GT_U32 maxPollingForDone = 10000000; /* this counter was increased for DDR4 + due to A390 DB-GP DDR4 failure */ +#else /* DDR3 */ #ifdef CONFIG_BOBK -GT_U32 maxPollingForDone = 1000; /*1000000; oferb */ +GT_U32 maxPollingForDone = 1000; #else GT_U32 maxPollingForDone = 1000000; -#endif +#endif /* CONFIG_BOBK */ +#endif /* CONFIG_DDR4 */ extern MV_HWS_RESULT trainingResult[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]; extern AUTO_TUNE_STAGE trainingStage;