diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index 5c991f9..93e6e2c 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -101,22 +101,32 @@
 /* MSYS family linear id */
 #define MV_MSYS_BC2_INDEX		0
 #define MV_MSYS_AC3_INDEX		1
-#define MV_MSYS_INDEX_MAX		2
+#define MV_78460_INDEX			2
+#define MV_MSYS_AXP_INDEX_MAX		3
 
-MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MV_MSYS_INDEX_MAX] = {
-/*			    BC2		AC3 */
-/* DRAM_UNIT_ID         */ { 1,		1, },
-/* PEX_UNIT_ID          */ { 1,		1, },
-/* ETH_GIG_UNIT_ID      */ { 2,		2, },
-/* XOR_UNIT_ID          */ { 1,		1, },
-/* UART_UNIT_ID         */ { 2,		2, },
-/* SPI_UNIT_ID          */ { 2,		1, },
-/* SDIO_UNIT_ID         */ { 1,		1, },
-/* I2C_UNIT_ID          */ { 2,		2, },
-/* USB_UNIT_ID          */ { 0,		1, },
-/* USB3_UNIT_ID         */ { 0,		0, },
-/* NAND_UNIT_ID	        */ { 1,		1, },
-/* DEVBUS_UNIT_ID       */ { 0,		0, },
+MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MV_MSYS_AXP_INDEX_MAX] = {
+/*			     BC2	AC3		78460*/
+/* DRAM_UNIT_ID		*/ { 1,		1,		1,},
+/* PEX_UNIT_ID		*/ { 1,		1,		4,},
+/* ETH_GIG_UNIT_ID	*/ { 2,		2,		4,},
+/* XOR_UNIT_ID		*/ { 1,		1,		4,},
+/* UART_UNIT_ID		*/ { 2,		2,		4,},
+/* SPI_UNIT_ID		*/ { 2,		1,		2,},
+/* SDIO_UNIT_ID		*/ { 1,		1,		1,},
+/* I2C_UNIT_ID		*/ { 2,		2,		2,},
+/* USB_UNIT_ID		*/ { 0,		1,		3,},
+/* USB3_UNIT_ID		*/ { 0,		0,		0,},
+/* NAND_UNIT_ID		*/ { 1,		1,		1 },
+/* DEVBUS_UNIT_ID	*/ { 0,		0,		0 },
+/* IDMA_UNIT_ID		*/ { 0,		0,		4,},
+/* SATA_UNIT_ID		*/ { 0,		0,		2,},
+/* TDM_UNIT_ID		*/ { 0,		0,		1,},
+/* CESA_UNIT_ID		*/ { 0,		0,		2,},
+/* AUDIO_UNIT_ID	*/ { 0,		0,		0,},
+/* TS_UNIT_ID		*/ { 0,		0,		0,},
+/* XPON_UNIT_ID		*/ { 0,		0,		0,},
+/* BM_UNIT_ID		*/ { 0,		0,		1,},
+/* PNC_UNIT_ID		*/ { 0,		0,		1,},
 };
 
 static MV_U32 mvCtrlDevIdIndexGet(MV_U32 devId)
@@ -130,6 +140,9 @@
 	case MV_ALLEYCAT3_DEV_ID:
 		index = MV_MSYS_AC3_INDEX;
 		break;
+	case MV_78460_DEV_ID:
+		index = MV_78460_INDEX;
+		break;
 	default:
 		index = MV_MSYS_AC3_INDEX;
 	}
@@ -372,6 +385,8 @@
 *******************************************************************************/
 MV_U32 mvCtrlPexMaxIfGet(MV_VOID)
 {
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		return MV_PEX_MAX_IF_AXP;
 	return mvCtrlSocUnitInfoNumGet(PEX_UNIT_ID);
 }
 
@@ -461,6 +476,8 @@
 *******************************************************************************/
 MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID)
 {
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		return mvCtrlEthMaxPortGet();
 	return 2;
 }
 
@@ -582,6 +599,64 @@
 #endif
 
 /*******************************************************************************
+* mvCtrlModelGetAxp - Get Marvell controller device model (Id) for AXP devices
+*
+* DESCRIPTION:
+*       This function returns 16bit describing the device model (ID) as defined
+*       in PCI Device and Vendor ID configuration register offset 0x0.
+*
+* INPUT:
+*       None.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       16bit desscribing Marvell controller ID
+*
+*******************************************************************************/
+MV_U16 mvCtrlModelGetAxp(MV_VOID)
+{
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	MV_U32 pexPower;
+#endif
+	MV_U32 devId;
+	MV_U16 model = 0;
+	MV_U32 reg, reg2;
+	static MV_U16 modelId = 0xffff;
+
+	if (modelId != 0xffff)
+		return modelId;
+
+	/* if PEX0 clocks are disabled - enabled it to read */
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	/* Check pex power state */
+	pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0);
+	if (pexPower == MV_FALSE)
+		mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
+#endif
+	reg = MV_REG_READ(POWER_MNG_CTRL_REG);
+	if ((reg & AXP_PMC_PEXSTOPCLOCK_MASK(0)) == AXP_PMC_PEXSTOPCLOCK_STOP(0)) {
+		reg2 = ((reg & ~AXP_PMC_PEXSTOPCLOCK_MASK(0)) | AXP_PMC_PEXSTOPCLOCK_EN(0));
+		MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2);
+	}
+
+	devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID));
+
+	/* Reset the original value of the PEX0 clock */
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	/* Return to power off state */
+	if (pexPower == MV_FALSE)
+		mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
+#endif
+
+	model = (MV_U16) ((devId >> 16) & 0xFFFF);
+
+	modelId = model;
+	return model;
+}
+
+/*******************************************************************************
 * mvCtrlModelGet - Get Marvell controller device model (Id)
 *
 * DESCRIPTION:
@@ -602,6 +677,9 @@
 {
 	MV_U32	ctrlId = MV_REG_READ(DEV_ID_REG);
 
+	if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+		return mvCtrlModelGetAxp();
+
 	ctrlId = (ctrlId & (DEVICE_ID_MASK)) >> DEVICE_ID_OFFS;
 
 	switch (ctrlId & ~DEVICE_FLAVOR_MASK) {
@@ -633,8 +711,30 @@
 *******************************************************************************/
 MV_U8 mvCtrlRevGet(MV_VOID)
 {
-	MV_U32 value = MV_DFX_REG_READ(DEV_REV_ID_REG);
-	return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	MV_U32 pexPower;
+#endif
+	MV_U32 value;
+	MV_U8 revNum;
+
+	if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID) {
+		value = MV_DFX_REG_READ(DEV_REV_ID_REG);
+		return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
+	}
+
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	/* Check pex power state */
+	pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0);
+	if (pexPower == MV_FALSE)
+		mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
+#endif
+	revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID));
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+	/* Return to power off state */
+	if (pexPower == MV_FALSE)
+		mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
+#endif
+	return (revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
 }
 
 /*******************************************************************************
@@ -1306,32 +1406,66 @@
 *******************************************************************************/
 MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
 {
+	MV_U32 mask;
 
 	switch (unitId) {
 #if defined(MV_INCLUDE_PEX)
 	case PEX_UNIT_ID:
-		if (enable == MV_FALSE)
-			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+			mask = AXP_PMC_PEXSTOPCLOCK_MASK(index);
 		else
-			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+			mask = PMC_PEXSTOPCLOCK_MASK;
+
+		if (enable == MV_FALSE)
+			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+		else
+			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
 
 		break;
 #endif
 #if defined(MV_INCLUDE_GIG_ETH)
 	case ETH_GIG_UNIT_ID:
-		if (enable == MV_FALSE)
-			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+			mask = AXP_PMC_GESTOPCLOCK_MASK(index);
 		else
-			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+			mask = PMC_GESTOPCLOCK_MASK(index);
+
+		if (enable == MV_FALSE)
+			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+		else
+			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
 
 		break;
 #endif
 #if defined(MV_INCLUDE_SDIO)
 	case SDIO_UNIT_ID:
-		if (enable == MV_FALSE)
-			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+			mask = AXP_PMC_SDIOSTOPCLOCK_MASK;
 		else
-			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+			mask = PMC_SDIOSTOPCLOCK_MASK;
+
+		if (enable == MV_FALSE)
+			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+		else
+			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
+
+		break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+	case CESA_UNIT_ID:
+		if (enable == MV_FALSE)
+			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_CESASTOPCLOCK_MASK);
+		else
+			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_CESASTOPCLOCK_MASK);
+
+		break;
+#endif
+#if defined(MV_INCLUDE_USB)
+	case USB_UNIT_ID:
+		if (enable == MV_FALSE)
+			MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_USBSTOPCLOCK_MASK(index));
+		else
+			MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_USBSTOPCLOCK_MASK(index));
 
 		break;
 #endif
@@ -1355,13 +1489,22 @@
 {
 #if defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_SDIO)
 	MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG);
+	MV_U32 mask, stop;
 #endif
 	MV_BOOL state = MV_TRUE;
 
 	switch (unitId) {
 #if defined(MV_INCLUDE_PEX)
 	case PEX_UNIT_ID:
-		if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP)
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+			mask = AXP_PMC_PEXSTOPCLOCK_MASK(index);
+			stop = AXP_PMC_PEXSTOPCLOCK_STOP(index);
+		} else {
+			mask = PMC_PEXSTOPCLOCK_MASK;
+			stop = PMC_PEXSTOPCLOCK_STOP;
+		}
+
+		if ((reg & mask) == stop)
 			state = MV_FALSE;
 		else
 			state = MV_TRUE;
@@ -1369,7 +1512,15 @@
 #endif
 #if defined(MV_INCLUDE_GIG_ETH)
 	case ETH_GIG_UNIT_ID:
-		if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index))
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+			mask = AXP_PMC_GESTOPCLOCK_MASK(index);
+			stop = AXP_PMC_GESTOPCLOCK_STOP(index);
+		} else {
+			mask = PMC_GESTOPCLOCK_MASK(index);
+			stop = PMC_GESTOPCLOCK_STOP(index);
+		}
+
+		if ((reg & mask) == stop)
 			state = MV_FALSE;
 		else
 			state = MV_TRUE;
@@ -1377,7 +1528,33 @@
 #endif
 #if defined(MV_INCLUDE_SDIO)
 	case SDIO_UNIT_ID:
-		if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP)
+		if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+			mask = AXP_PMC_SDIOSTOPCLOCK_MASK;
+			stop = AXP_PMC_SDIOSTOPCLOCK_STOP;
+		} else {
+			mask = PMC_SDIOSTOPCLOCK_MASK;
+			stop = PMC_SDIOSTOPCLOCK_STOP;
+		}
+
+		if ((reg & mask) == stop)
+			state = MV_FALSE;
+		else
+			state = MV_TRUE;
+		break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+	case CESA_UNIT_ID:
+		if ((reg & AXP_PMC_CESASTOPCLOCK_MASK) == AXP_PMC_CESASTOPCLOCK_STOP)
+			state = MV_FALSE;
+		else
+			state = MV_TRUE;
+		break;
+#endif
+#if defined(MV_INCLUDE_USB)
+	case USB_UNIT_ID:
+		if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID)
+			state = MV_TRUE;
+		else if ((reg & AXP_PMC_USBSTOPCLOCK_MASK(index)) == AXP_PMC_USBSTOPCLOCK_STOP(index))
 			state = MV_FALSE;
 		else
 			state = MV_TRUE;
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index d414251..0cd1a92 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -151,6 +151,73 @@
 #define PMC_GESTOPCLOCK_EN(port)		(1 << PMC_GESTOPCLOCK_OFFS(port))
 #define PMC_GESTOPCLOCK_STOP(port)		(0 << PMC_GESTOPCLOCK_OFFS(port))
 
+/*  Power Management Clock Gating Control Register - AXP only */
+
+#define AXP_PMC_TDMSTOPCLOCK_OFFS		25
+#define AXP_PMC_TDMSTOPCLOCK_MASK		(1 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+#define AXP_PMC_TDMSTOPCLOCK_EN			(1 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+#define AXP_PMC_TDMSTOPCLOCK_STOP		(0 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+
+#define AXP_PMC_PEXSTOPCLOCK_OFFS(port)		((port) < 8 ? (5 + (port)) : (18 + (port)))
+#define AXP_PMC_PEXSTOPCLOCK_MASK(port)		(1 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+#define AXP_PMC_PEXSTOPCLOCK_EN(port)		(1 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+#define AXP_PMC_PEXSTOPCLOCK_STOP(port)		(0 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_USBSTOPCLOCK_OFFS(port)		((port) < 3 ? (18 + (port)) : 0)
+#define AXP_PMC_USBSTOPCLOCK_MASK(port)		(1 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+#define AXP_PMC_USBSTOPCLOCK_EN(port)		(1 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+#define AXP_PMC_USBSTOPCLOCK_STOP(port)		(0 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_SDIOSTOPCLOCK_OFFS		17
+#define AXP_PMC_SDIOSTOPCLOCK_MASK		(1 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+#define AXP_PMC_SDIOSTOPCLOCK_EN		(1 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+#define AXP_PMC_SDIOSTOPCLOCK_STOP		(0 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+
+#define AXP_PMC_RUNITSTOPCLOCK_OFFS		24
+#define AXP_PMC_RUNITSTOPCLOCK_MASK		(1 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+#define AXP_PMC_RUNITSTOPCLOCK_EN		(1 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+#define AXP_PMC_RUNITSTOPCLOCK_STOP		(0 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+
+#define AXP_PMC_XORSTOPCLOCK_OFFS		22
+#define AXP_PMC_XORSTOPCLOCK_MASK		(1 << AXP_PMC_XORSTOPCLOCK_OFFS)
+#define AXP_PMC_XORSTOPCLOCK_EN			(1 << AXP_PMC_XORSTOPCLOCK_OFFS)
+#define AXP_PMC_XORSTOPCLOCK_STOP		(0 << AXP_PMC_XORSTOPCLOCK_OFFS)
+
+#define AXP_PMC_SATASTOPCLOCK_OFFS(ch)		(ch == 0 ? 14 : 29)
+#define AXP_PMC_SATASTOPCLOCK_MASK(ch)		(3 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+#define AXP_PMC_SATASTOPCLOCK_EN(ch)		(3 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+#define AXP_PMC_SATASTOPCLOCK_STOP(ch)		(0 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+
+#define AXP_PMC_CESASTOPCLOCK_OFFS		23
+#define AXP_PMC_CESASTOPCLOCK_MASK		(1 << AXP_PMC_CESASTOPCLOCK_OFFS)
+#define AXP_PMC_CESASTOPCLOCK_EN		(1 << AXP_PMC_CESASTOPCLOCK_OFFS)
+#define AXP_PMC_CESASTOPCLOCK_STOP		(0 << AXP_PMC_CESASTOPCLOCK_OFFS)
+
+#define AXP_PMC_GESTOPCLOCK_OFFS(port)		((port) < 4 ? (4 - (port)) : 0)
+#define AXP_PMC_GESTOPCLOCK_MASK(port)		(1 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+#define AXP_PMC_GESTOPCLOCK_EN(port)		(1 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+#define AXP_PMC_GESTOPCLOCK_STOP(port)		(0 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_NETASTOPCLOCK_OFFS		13
+#define AXP_PMC_NETASTOPCLOCK_MASK		(1 << AXP_PMC_NETASTOPCLOCK_OFFS)
+#define AXP_PMC_NETASTOPCLOCK_EN		(1 << AXP_PMC_NETASTOPCLOCK_OFFS)
+#define AXP_PMC_NETASTOPCLOCK_STOP		(0 << AXP_PMC_NETASTOPCLOCK_OFFS)
+
+#define AXP_PMC_LCDSTOPCLOCK_OFFS		16
+#define AXP_PMC_LCDSTOPCLOCK_MASK		(1 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+#define AXP_PMC_LCDSTOPCLOCK_EN			(1 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+#define AXP_PMC_LCDSTOPCLOCK_STOP		(0 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+
+#define AXP_PMC_IDMASTOPCLOCK_OFFS		21
+#define AXP_PMC_IDMASTOPCLOCK_MASK		(1 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+#define AXP_PMC_IDMASTOPCLOCK_EN		(1 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+#define AXP_PMC_IDMASTOPCLOCK_STOP		(0 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+
+#define AXP_PMC_DDRSTOPCLOCK_OFFS		28
+#define AXP_PMC_DDRSTOPCLOCK_MASK		(1 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+#define AXP_PMC_DDRSTOPCLOCK_EN			(1 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+#define AXP_PMC_DDRSTOPCLOCK_STOP		(0 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+
 /* dummy defenition, used for SGMII capable interfaces */
 #define SGMII_SERDES_CFG_REG(port)		(0)
 
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
index b2eed16..f922956 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -259,6 +259,15 @@
 	USB3_UNIT_ID,
 	NAND_UNIT_ID,
 	DEVBUS_UNIT_ID,
+	IDMA_UNIT_ID,
+	SATA_UNIT_ID,
+	TDM_UNIT_ID,
+	CESA_UNIT_ID,
+	AUDIO_UNIT_ID,
+	TS_UNIT_ID,
+	XPON_UNIT_ID,
+	BM_UNIT_ID,
+	PNC_UNIT_ID,
 	MAX_UNITS_ID
 } MV_UNIT_ID;