tree 049354d5e1f2fac5642865ee2078e6b8d29b4449
parent 99dbd4efd6d5ecc37d7e8f28b20d9be8c83055c7
author Mike Nuss <mike@terascala.com> 1254760408 -0400
committer Stefan Roese <sr@denx.de> 1254899411 +0200

PPC4xx: Denali core: Fix incorrect DDR row bits

The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.

Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>