ddr3: Added usage of new DGL param - gRttWR
RTT WR is Dynamic ODT value.
This parameter should be set 'RZQ/4' for BC2, for other it remains 'Off'
Change-Id: I5600ac275dbc889c5bb5eca8225e2024be692c6c
Signed-off-by: Igor Petrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19408
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24129
Tested-by: Star_Automation <star@marvell.com>
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
index c191552..8130cd9 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
@@ -113,7 +113,9 @@
#define MV_TUNE_TRAINING_PARAMS_DIC_DDR4 0x0
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4 0x330012
#define MV_TUNE_TRAINING_PARAMS_RTT_NOM_DDR4 0x600 /*RZQ/3 = 0x600*/
-#define MV_TUNE_TRAINING_PARAMS_RTT_WR_DDR4 0x400 /*RZQ/1 = 0x400*/
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR 0x400 /*RZQ/1 = 0x400*/
+#else
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR 0x0 /*off*/
#endif
#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
index 7f6959e..f6d3bdf 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
@@ -92,6 +92,7 @@
#define MV_TUNE_TRAINING_PARAMS_DIC 0x2
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG 0x120012
#define MV_TUNE_TRAINING_PARAMS_RTT_NOM 0x44
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR 0x0 /*off*/
typedef struct __mvDramModes {
char *mode_name;
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
index 15d090c..07ff13d 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
@@ -85,6 +85,7 @@
#define MV_TUNE_TRAINING_PARAMS_DIC 0x2
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG 0x120012
#define MV_TUNE_TRAINING_PARAMS_RTT_NOM 0x44
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR 0x200 /*RZQ/4*/
typedef struct __mvDramMcInit {
MV_U32 reg_addr;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
index e5efe52..30b926f 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
@@ -842,13 +842,13 @@
params.gDic = MV_TUNE_TRAINING_PARAMS_DIC;
params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG;
params.gRttNom = MV_TUNE_TRAINING_PARAMS_RTT_NOM;
+ params.gRttWR = MV_TUNE_TRAINING_PARAMS_RTT_WR;
#ifdef CONFIG_DDR4
params.gZpodtData = MV_TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4;
params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4;
params.gRttNom = MV_TUNE_TRAINING_PARAMS_RTT_NOM_DDR4;
params.gDic = MV_TUNE_TRAINING_PARAMS_DIC_DDR4;
- params.gRttWR = MV_TUNE_TRAINING_PARAMS_RTT_WR_DDR4;
#endif
status = ddr3TipTuneTrainingParams(devNum, ¶ms);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 6009d82..64ef502 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -663,6 +663,7 @@
2)CAS Write Latency */
dataValue = (cwlMaskTable[cwlVal] << 3);
dataValue |= ((topologyMap->interfaceParams[interfaceId].interfaceTemp == MV_HWS_TEMP_HIGH) ? (1 << 7) : 0);
+ dataValue |= gRttWR;
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3) | (0x1<<7) | (0x3<<9)));
}
@@ -1591,12 +1592,8 @@
dataValue = ((clMaskTable[clValue] & 0x1) << 2) | ((clMaskTable[clValue] & 0xE) << 3);
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
/*MR2: CWL = 10 , Auto Self-Refresh - disable */
- dataValue = (cwlMaskTable[cwlValue] << 3);
- /*dataValue |= (1 << 9); removed by Ofer 31/10
- dataValue |= ((topologyMap->interfaceParams[interfaceId].interfaceTemp == MV_HWS_TEMP_HIGH) ? (1 << 7) : 0);
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3) | (0x1<<7) | (0x3<<9)));*/
-
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3)));
+ dataValue = (cwlMaskTable[cwlValue] << 3) | gRttWR;
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3) | (0x3 << 9)));
ddr3TipWriteOdt(devNum, accessType, interfaceId, clValue, cwlValue);
@@ -1606,9 +1603,9 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
/* re-write CWL */
- dataValue = (cwlMaskTable[cwlValue] << 3);
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS2_CMD, dataValue, (0x7 << 3) ));
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR2_REG, dataValue, (0x7 << 3)));
+ dataValue = (cwlMaskTable[cwlValue] << 3) | gRttWR;
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS2_CMD, dataValue, (0x7 << 3) | (0x3 << 9)));
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR2_REG, dataValue, (0x7 << 3) | (0x3 << 9)));
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_OPERATION_REG, 0xC00, 0xF00)); /* CS0 & CS1*/
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_OPERATION_REG, 0x3, 0x1F)); /* MR0 Update Command */
@@ -1867,12 +1864,12 @@
dataValue = ((clMaskTable[clValue] & 0x1) << 2) | ((clMaskTable[clValue] & 0xE) << 3);
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
/*MR2: CWL = 10 , Auto Self-Refresh - disable */
- dataValue = (cwlMaskTable[cwlValue] << 3);
+ dataValue = (cwlMaskTable[cwlValue] << 3) | gRttWR;
/* nklein 24.10.13 - should not be here - leave value as set in
the init configuration dataValue |= (1 << 9);
dataValue |= ((topologyMap->interfaceParams[interfaceId].interfaceTemp == MV_HWS_TEMP_HIGH) ? (1 << 7) : 0);
****/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3))); /* nklein 24.10.13 - see above comment*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, MR2_REG, dataValue , (0x7<<3) | (0x3 << 9))); /* nklein 24.10.13 - see above comment*/
/*ODT TIMING */
dataValue = ((clValue-cwlValue+1) << 4) | ((clValue-cwlValue+6) << 8) | ((clValue-1) << 12) | ((clValue+6) << 16);
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, ODT_TIMING_LOW, dataValue, 0xFFFF0));
@@ -1886,9 +1883,9 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
/* re-write CWL */
- dataValue = (cwlMaskTable[cwlValue] << 3);
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS2_CMD, dataValue, (0x7 << 3) ));
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR2_REG, dataValue, (0x7 << 3)));
+ dataValue = (cwlMaskTable[cwlValue] << 3) | gRttWR;
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS2_CMD, dataValue, (0x7 << 3) | (0x3 << 9)));
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR2_REG, dataValue, (0x7 << 3) | (0x3 << 9)));
/* CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, SDRAM_TIMING_HIGH_REG, 0x3E031F80, 0x3FFFFFFF));*/
if (memMask != 0)
@@ -2139,60 +2136,6 @@
/*****************************************************************************
-Dynamic ODT
-******************************************************************************/
-GT_STATUS ddr3TipDynamicOdt
-(
- GT_U32 devNum,
- GT_BOOL bIsSet
-)
-{
- GT_U32 mr1Value,mr2Value, interfaceId;
-
- if (bIsSet == GT_TRUE)
- {
- mr1Value = 0x24;
- mr2Value = 0;
- }
- else
- {
- mr1Value = 0;
- mr2Value = 0x200;
- }
-
- /* MR1: set RttNom to RZQ/6 */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR1_REG, mr1Value, 0x224));
- /* MR2: disable dynamic ODT*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, MR2_REG, mr2Value, 0x600));
- /*Operation command*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_OPERATION_REG, 0xC00, 0xF00));
- /* MR1 Command */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_OPERATION_REG, 0x4, 0x1F));
- /* check controller back to normal */
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0, 0x1F, SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("WL: DDR3 poll failed(1)"));
- }
- }
- /* MR2 Command */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_OPERATION_REG, 0x8, 0x1F));
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0, 0x1F, SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("WL: DDR3 poll failed(2)"));
- }
- }
- return GT_OK;
-}
-
-
-
-/*****************************************************************************
Reset XSB Read FIFO
******************************************************************************/
GT_STATUS ddr3TipResetFifoPtr
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
index 741a1fa..342ff07 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
@@ -828,6 +828,7 @@
tuneParams.gZnodtData = 45;
tuneParams.gZpodtCtrl = 45;
tuneParams.gZnodtCtrl = 45;
+ tuneParams.gRttWR = 0x200;
CHECK_STATUS(ddr3TipTuneTrainingParams(devNum, &tuneParams));
