fix: spi: msys_ac3: fix spi timing violation on 40/50MHz
There is a timing violation in Data when setting up
SCLK to 40MHz or 50MHz.
SPI_TMISO_SAMPLE defines the gap between SPI CLK sampling edge (as
determined by CPOL and CPHA) and the actual core clock cycle that
MISO is captured.
0x0 = MISO sample occurs upon SPI_CLK edge.
0x1 = MISO sample occurs 1 core_clk after SPI_CLK edge.
0x2 = MISO sample occurs 2 core_clk after SPI_CLK edge.
0x3 = MISO sample occurs 3 core_clk after SPI_CLK edge.
- double the value of SPI_TMISO_SAMPLE (from 0x1 to 0x2),
this will relax timing constraint.
Change-Id: I7e2870c920d208e6c7e069872a800695f3a91688
Signed-off-by: Bassel Saba <basselsa@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/17950
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
2 files changed
