sh: sh_eth: Add support SH7724
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 0692f8b..27fde05 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,8 +1,8 @@
/*
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (c) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008, 2011 Renesas Solutions Corp.
+ * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -162,6 +162,32 @@
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
+
+#elif defined(CONFIG_CPU_SH7724)
+#define BASE_IO_ADDR 0xA4600000
+
+#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
+#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x0000)
+#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
+#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
+#define EESR(port) (BASE_IO_ADDR + 0x0028)
+#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
+#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
+#define TFTR(port) (BASE_IO_ADDR + 0x0048)
+#define FDR(port) (BASE_IO_ADDR + 0x0050)
+#define RMCR(port) (BASE_IO_ADDR + 0x0058)
+#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
+#define ECMR(port) (BASE_IO_ADDR + 0x0100)
+#define RFLR(port) (BASE_IO_ADDR + 0x0108)
+#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
+#define PIR(port) (BASE_IO_ADDR + 0x0120)
+#define APR(port) (BASE_IO_ADDR + 0x0154)
+#define MPR(port) (BASE_IO_ADDR + 0x0158)
+#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
+#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
+#define MALR(port) (BASE_IO_ADDR + 0x01c8)
#endif
/*
@@ -183,7 +209,7 @@
EDMR_SRST = 0x03,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
-#elif defined CONFIG_CPU_SH7757
+#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
EDMR_SRST = 0x01,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
@@ -325,7 +351,8 @@
/* Transfer descriptor bit */
enum TD_STS_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
+ || defined(CONFIG_CPU_SH7724)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
@@ -350,6 +377,10 @@
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001,
+#ifdef CONFIG_CPU_SH7724
+ ECMR_RTM = 0x00000010,
+#endif
+
};
#ifdef CONFIG_CPU_SH7763
@@ -357,6 +388,8 @@
ECMR_TXF | ECMR_MCT)
#elif CONFIG_CPU_SH7757
#define ECMR_CHG_DM (ECMR_ZPF)
+#elif CONFIG_CPU_SH7724
+#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif
