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#ifndef _INC_A38X_TOPOLOGY_H
#define _INC_A38X_TOPOLOGY_H

#include "mvDdr3LoggingDef.h"

/*Bus mask variants*/
#define BUS_MASK_32BIT				0xF
#define BUS_MASK_32BIT_ECC			0x1F
#define BUS_MASK_16BIT				0x3
#define BUS_MASK_16BIT_ECC			0x13
#define BUS_MASK_16BIT_ECC_PUP3		0xB

#define  DYNAMIC_CS_SIZE_CONFIG
#define  DISABLE_L2_FILTERING_DURING_DDR_TRAINING

#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
/************************************* Customer Boards Topology *************************************/
MV_HWS_TOPOLOGY_MAP TopologyMap[] =
{
    /* 1st Customer board - reference from DB */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
    /* 2nd Customer board */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
    /* GFCH100 */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT_ECC  /* Buses mask */
    }
};

#else /* CONFIG_CUSTOMER_BOARD_SUPPORT */

/************************************* Marvell Boards Topology *************************************/
MV_HWS_TOPOLOGY_MAP TopologyMap[] =
{
    /* 1st Marvell board - RD_NAS */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                                                     speed_bin        memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
#ifdef CONFIG_DDR3
    /* 2nd Marvell board - DB (DDR3) */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
#else
    /* 2nd Marvell board - DB (DDR4) */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
    {{{{0x1,0,0,0},{ 0x1,0,0,0},{ 0x1,0,0,0},{ 0x1,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_2133P, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_667, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
#endif
    /* 3rd Marvell board - RD_AP */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
    /* 4rd Marvell board - DB_AP */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
    /* 5th Marvell board - DB_GP */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                                                     speed_bin        memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_32BIT  /* Buses mask */
    },
    /* 6th Marvell board - A381/2 DB-BP */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                                                     speed_bin        memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
    BUS_MASK_16BIT  /* Buses mask */
    },
	/* 6th Marvell board - DB_AMC */
    {
    0x1, /* active interfaces */
    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 ,   0 , MV_HWS_TEMP_LOW}},
    5, /* Num Of Bus Per Interface*/
	BUS_MASK_32BIT_ECC  /* Buses mask */
    },
};
#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */

#endif /* _INC_A38X_TOPOLOGY_H */