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#ifndef __INCethswitchregsh
#define __INCethswitchregsh

#include "eth-phy/mvEthPhyRegs.h"

#define MV_SWITCH_PORTS_OFFSET					0x10

#define MV_SWITCH_PORT_STATUS_REG				0x0
#define MV_SWITCH_PHYS_CONTROL_REG				0x1
#define MV_SWITCH_PORT_CONTROL_REG				0x4
#define MV_SWITCH_PORT_VMAP_REG					0x6
#define MV_SWITCH_PORT_VID_REG					0x7


#define MV_SWITCH_PORT_OFFSET(port) (MV_SWITCH_PORTS_OFFSET + port)

/* E6063 related */
#define MV_E6063_CPU_PORT						5
#define MV_E6063_PORTS_OFFSET					0x8
#define MV_E6063_MAX_PORTS_NUM					7
#define MV_E6063_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|	\
													(1 << 3)|(1 << 4)|(1 << 5))

/* E6065 related */
#define MV_E6065_CPU_PORT						5
#define MV_E6065_PORTS_OFFSET					0x8
#define MV_E6065_MAX_PORTS_NUM					6
#define MV_E6065_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5))

/* E6063 related */
#define MV_E6131_CPU_PORT						0x3
#define MV_E6131_PORTS_OFFSET					0x10
#define MV_E6131_MAX_PORTS_NUM					8
#define MV_E6131_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|	\
												(1 << 3)|(1 << 5)|(1 << 7))
/* E6161 related */
#define MV_E6161_CPU_PORT						0x5
#define MV_E6161_PORTS_OFFSET					0x10
#define MV_E6161_SMI_PHY_COMMAND				0x18
#define MV_E6161_SMI_PHY_DATA					0x19
#define MV_E6161_GLOBAL_2_REG_DEV_ADDR			0x1C
#define MV_E6161_MAX_PORTS_NUM					6
#define MV_E6161_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5))
#define E6161_PHY_TIMEOUT						10000
#define E6161_PHY_SMI_BUSY_BIT					15  /* Busy */
#define E6161_PHY_SMI_BUSY_MASK					(1 << ETH_PHY_SMI_BUSY_BIT)

/* E6171 related */
#define MV_E6171_CPU_PORT						0x6
#define MV_E6171_PORTS_OFFSET					0x10
#define MV_E6171_SWITCH_PHIYSICAL_CTRL_REG		0x1
#define MV_E6171_SWITCH_PORT_CTRL_REG		    0x4
#define MV_E6171_SMI_PHY_COMMAND				0x18
#define MV_E6171_SMI_PHY_DATA					0x19
#define MV_E6171_GLOBAL_2_REG_DEV_ADDR			0x1C
#define MV_E6171_MAX_PORTS_NUM					7
#define MV_E6171_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 6))
#define E6171_PHY_TIMEOUT					    10000
#define E6171_PHY_SMI_BUSY_BIT		    		15  /* Busy */
#define E6171_PHY_SMI_BUSY_MASK		    		(1 << ETH_PHY_SMI_BUSY_BIT)

/* Armada 370 internal related */
#define MV_SW_CPU_PORT							0x6
#define MV_SW_PORTS_OFFSET						0x10
#define MV_SW_SWITCH_PHIYSICAL_CTRL_REG			0x1
#define MV_SW_SWITCH_PORT_CTRL_REG				0x4
#define MV_SW_SMI_PHY_COMMAND					0x18
#define MV_SW_SMI_PHY_DATA						0x19
#define MV_SW_GLOBAL_2_REG_DEV_ADDR				0x1C
#define MV_SW_MAX_PORTS_NUM						7
#define MV_SW_ENABLED_PORTS						((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4))
#define MV_SW_PHY_TIMEOUT						10000
#define MV_SW_PHY_SMI_BUSY_BIT					15  /* Busy */
#define MV_SW_PHY_SMI_BUSY_MASK					(1 << MV_SW_PHY_SMI_BUSY_BIT)

/* KW2 internal related */
#define MV_KW2_SW_CPU_PORT						0x6
#define MV_KW2_SW_PORTS_OFFSET					0x10
#define MV_KW2_SW_SWITCH_PHIYSICAL_CTRL_REG		0x1
#define MV_KW2_SW_SWITCH_PORT_CTRL_REG			0x4
#define MV_KW2_SW_SMI_PHY_COMMAND				0x18
#define MV_KW2_SW_SMI_PHY_DATA					0x19
#define MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR			0x1C
#define MV_KW2_SW_MAX_PORTS_NUM					7
#define MV_KW2_SW_ENABLED_PORTS					((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4))
#define KW2_SW_PHY_TIMEOUT						10000
#define KW2_SW_PHY_SMI_BUSY_BIT					15  /* Busy */
#define KW2_SW_PHY_SMI_BUSY_MASK				(1 << ETH_PHY_SMI_BUSY_BIT)

/* ALP internal related */
#define MV_ALP_SW_PORTS_OFFSET					0x10
#define MV_ALP_SW_MAX_PORTS_NUM					7

#endif /* __INCethswitchregsh */