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#ifndef __INCmvBoardEnvLib39h
#define __INCmvBoardEnvLib39h

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

typedef enum _boardMacSpeed {
	BOARD_MAC_SPEED_10M,
	BOARD_MAC_SPEED_100M,
	BOARD_MAC_SPEED_1000M,
	BOARD_MAC_SPEED_2000M,
	BOARD_MAC_SPEED_AUTO,
	BOARD_MAC_UNCONNECTED
} MV_BOARD_MAC_SPEED;

typedef enum _eth_negotiation_port_type {
	SMI,
	XSMI
} MV_PHY_NEGOTIATION_PORT_TYPE;

typedef struct _boardMacInfo {
	MV_BOARD_MAC_SPEED boardMacSpeed;
	MV_32 boardEthSmiAddr;
	MV_32 boardEthSmiAddr0;
	MV_PHY_NEGOTIATION_PORT_TYPE negType;
} MV_BOARD_MAC_INFO;

typedef enum {
	MV_PORT_TYPE_RXAUI,
	MV_PORT_TYPE_XAUI,
	MV_PORT_TYPE_SGMII,
	MV_PORT_TYPE_QSGMII,
	MV_PORT_TYPE_RGMII,
	MV_PORT_TYPE_UNKNOWN = -1,
} MV_PORT_TYPE;

typedef enum {
	MV_NETCOMP_GE_MAC0_2_RXAUI	=	BIT0,
	MV_NETCOMP_GE_MAC0_2_XAUI	=	BIT1,
	MV_NETCOMP_GE_MAC0_2_SGMII_L0	=	BIT2,
	MV_NETCOMP_GE_MAC0_2_SGMII_L1	=	BIT3,
	MV_NETCOMP_GE_MAC0_2_QSGMII		=	BIT4,
	MV_NETCOMP_GE_MAC1_2_SGMII_L1	=	BIT5,
	MV_NETCOMP_GE_MAC1_2_RGMII1		=	BIT6,
	MV_NETCOMP_GE_MAC1_2_SGMII_L2	=	BIT7,
	MV_NETCOMP_GE_MAC1_2_SGMII_L4	=	BIT8,
	MV_NETCOMP_GE_MAC1_2_QSGMII		=	BIT9,
	MV_NETCOMP_GE_MAC2_2_SGMII_L3	=	BIT10,
	MV_NETCOMP_GE_MAC2_2_SGMII_L5	=	BIT11,
	MV_NETCOMP_GE_MAC2_2_QSGMII		=	BIT12,
	MV_NETCOMP_GE_MAC3_2_SGMII_L4	=	BIT13,
	MV_NETCOMP_GE_MAC3_2_SGMII_L6	=	BIT14,
	MV_NETCOMP_GE_MAC3_2_QSGMII		=	BIT15
} MV_NET_COMPLEX_TOPOLOGY;

#define MV_MODULE_INFO { \
{ MV_MODULE_MII,		0x1,	0,	 0x4,	{ 0, 1 } }, \
{ MV_MODULE_SLIC_TDM_DEVICE,	0x0,	0,	 0x1,	{ 0, 1 } }, \
{ MV_MODULE_I2S_DEVICE,		0x1,	0,	 0x3,	{ 0, 1 } }, \
{ MV_MODULE_SPDIF_DEVICE,	0x1,	0,	 0x2,	{ 0, 1 } }, \
{ MV_MODULE_NOR,		0x4,	0,	 0xF,	{ 0, 1 } }, \
{ MV_MODULE_NAND,		0x4,	0,	 0x1,	{ 0, 1 } }, \
{ MV_MODULE_SDIO,		0x4,	0,	 0x2,	{ 0, 1 } }, \
{ MV_MODULE_SGMII,		0x2,	0,	 0xF,	{ 0, 1 } }, \
{ MV_MODULE_DB381_SGMII,	0x0,	0,	 0x2,	{ 0, 0 } }, \
};

typedef enum _mvSatRTypeID {
/*  "Bios" Device  */
	MV_SATR_CPU_DDR_L2_FREQ,
	MV_SATR_CORE_CLK_SELECT,
	MV_SATR_BOOT_DEVICE,
	MV_SATR_BOOT2_DEVICE,
	MV_SATR_DEVICE_ID,
	MV_SATR_MAX_OPTION,
} MV_SATR_TYPE_ID;

/*					bit	TWSI	Reg	board	*/
/*   name		SATR-ID		Mask	offset	devID	num	active	*/
#define MV_SAR_INFO { \
{"freq",	MV_SATR_CPU_DDR_L2_FREQ, 0x1F,	0,	1,	0,	{1, 1}, 0},\
{"coreclock",	MV_SATR_CORE_CLK_SELECT, 0x02,	1,	3,	0,	{1, 1}, 0},\
{"bootsrc",	MV_SATR_BOOT_DEVICE,	 0x1F,	0,	2,	0,	{1, 1}, 0},\
{"bootsrc2",	MV_SATR_BOOT2_DEVICE,	 0x01,	0,	3,	0,	{1, 1}, 0},\
{"devid",	MV_SATR_DEVICE_ID,	 0x1C,	2,	3,	0,	{1, 1}, 0},\
{ "max_option",	MV_SATR_MAX_OPTION,	 0x0,	0,	0,	0,	{0, 0}, 0},\
};

/* extra SAR table, for different board implementations:
 * in case a field is used on 2 boards with different i2c mapping */
#define MV_SAR_INFO2 { \
{ "max_option",		MV_SATR_MAX_OPTION,		0x0,	0, 0, 0, {0, 0}, 0},\
};

#define MV_SATR_BOOT2_VALUE_MASK		0x1
#define MV_SATR_BOOT2_VALUE_OFFSET		5

#ifdef CONFIG_CMD_BOARDCFG
#define MV_BOARD_CONFIG_MAX_BYTE_COUNT	8

/* The defualt board configuration is -					*
* Serdes	0	1	2	3	4	5	6	*
* Type		PCIe0	SGMII1	PCIe1	SGMII2	PCIe2	RXAUI	RXAUI	*/

#define MV_BOARD_CONFIG_DEFAULT_VALUE		{0x00, 0x51, 0x41, 0x87, 0x04, 0x00, 0x00, 0x00}

typedef enum _mvConfigTypeID {
	MV_CONFIG_BOARDID,
	MV_CONFIG_LANE0,
	MV_CONFIG_LANE1,
	MV_CONFIG_LANE2,
	MV_CONFIG_LANE3,
	MV_CONFIG_LANE4,
	MV_CONFIG_LANE5,
	MV_CONFIG_LANE6,
	MV_CONFIG_NSS_EN,
	MV_CONFIG_DDR_BUSWIDTH,
	MV_CONFIG_DDR_ECC_EN,
	MV_CONFIG_BOARDCFG_EN,
	MV_CONFIG_TYPE_MAX_OPTION, /* limit for user read/write routines */
	MV_CONFIG_BOARDCFG_VALID,
	MV_CONFIG_TYPE_CMD_DUMP_ALL, /* limit for mvBoardConfigTypeGet routine */
	MV_CONFIG_TYPE_CMD_SET_DEFAULT,
} MV_CONFIG_TYPE_ID;

/* {{MV_CONFIG_TYPE_ID ConfigID, MV_U32 Mask,  Offset, byteNum,    isActiveForBoard[]}} */
#define MV_EEPROM_CONFIG_INFO { \
{ MV_CONFIG_BOARDID,		0xFF,	0,	0,	{1, 1} }, \
{ MV_CONFIG_LANE0,		0x0F,	0,	1,	{1, 1} }, \
{ MV_CONFIG_LANE1,		0xF0,	4,	1,	{1, 1} }, \
{ MV_CONFIG_LANE2,		0x0F,	0,	2,	{1, 1} }, \
{ MV_CONFIG_LANE3,		0xF0,	4,	2,	{1, 1} }, \
{ MV_CONFIG_LANE4,		0x0F,	0,	3,	{1, 1} }, \
{ MV_CONFIG_LANE5,		0xF0,	4,	3,	{1, 1} }, \
{ MV_CONFIG_LANE6,		0x0F,	0,	4,	{1, 1} }, \
{ MV_CONFIG_NSS_EN,		0x01,	0,	5,	{1, 1} }, \
{ MV_CONFIG_DDR_BUSWIDTH,	0x02,	1,	5,	{1, 1} }, \
{ MV_CONFIG_DDR_ECC_EN,		0x04,	2,	5,	{1, 1} }, \
{ MV_CONFIG_BOARDCFG_EN,	0x08,	3,	5,	{1, 1} }, \
{ MV_CONFIG_BOARDCFG_VALID,	0x03,	0,	6,	{1, 1} }, \
};


#define MV_BOARD_CONFIG_CMD_STR "serdes0, serdes1, serdes2, serdes3, serdes4, serdes5, serdes6, nss_en,\n"	\
				"\tddr_buswidth, ddr_ecc, eepromEnable\n\n"
#define MV_BOARD_CONFIG_CMD_MAX_OPTS 11

/*MV_CMD_TYPE_ID,		command name,		Name,			numOfValues,	Possible Values */
#define MV_BOARD_CONFIG_CMD_INFO {										\
{MV_CONFIG_BOARDID, "boardid",	"Board ID",			1,	{"DB Board"} },	\
{MV_CONFIG_LANE0,	"serdes0",	"SerDes Lane #0",	5,						\
	{"UnConnected", "PCI-e#0", "SATA3 #0", "SGMII #0", "SGMII(v3) #0"} },					\
{MV_CONFIG_LANE1,	"serdes1",	"SerDes Lane #1",	10,						\
	{"UnConnected", "PCI-e#0", "PCI-e#0-1", "SATA3 #0", "SGMII #0", "SGMII #1", "USB3-Host #0", "QSGMII",	\
	"SGMII(v3) #0", "SGMII(v3) #1"} },									\
{MV_CONFIG_LANE2,	"serdes2",	"SerDes Lane #2",	6,						\
	{"UnConnected", "PCI-e#1", "PCI-e#0-2", "SATA3 #1", "SGMII #1", "SGMII(v3) #1"} },			\
{MV_CONFIG_LANE3,	"serdes3",	"SerDes Lane #3",	9,						\
	{"UnConnected", "PCI-e#3", "PCI-e#0-3", "SATA3 #3", "SGMII #2", "USB3-Host #1", "USB-Device",		\
	"SGMII(v3) #2", "XAUI #3"} },										\
{MV_CONFIG_LANE4,	"serdes4",	"SerDes Lane #4",	10,						\
	{"UnConnected", "PCI-e#1", "UnConnected 1", "SGMII #3", "USB3-Host #0", "USB-Device", "SATA3 #2",	\
	"PCI-e#2", "SGMII(v3) #3", "XAUI #2"} },								\
{MV_CONFIG_LANE5,	"serdes5",	"SerDes Lane #5",	9,						\
	{"UnConnected", "PCI-e#2", "SATA3 #2", "SGMII #2", "USB3-Host #1", "USB-Device", "SGMII(v3) #2",	\
	"Reserved", "XAUI #1" } },										\
{MV_CONFIG_LANE6,	"serdes6",	"SerDes Lane #6",	5,						\
	{"UnConnected", "PCI-e#1", "SGMII(v3) #3", "Reserved", "XAUI #1"} },					\
{MV_CONFIG_NSS_EN,	"nss_en",	"NSS enable",		2,						\
	{"Disable", "Enable"} },										\
{MV_CONFIG_DDR_BUSWIDTH,	"ddr_buswidth",	"Buswidth enable",		2,				\
	{"32bit", "16bit"} },											\
{MV_CONFIG_DDR_ECC_EN,	"ddr_ecc",	"Dram ECC enable",		2,					\
	{"Disable", "Enable"} },										\
{MV_CONFIG_BOARDCFG_EN,	"eepromEnable",	"EEPROM enable",	2,					\
	{"Disable", "Enable"} },										\
};

#endif /* CONFIG_CMD_BOARDCFG */

MV_BOOL mvBoardIsPortInXaui(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInRxaui(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInQsgmii(MV_U32 ethPortNum);
MV_U32 mvBoardNetComplexConfigGet(MV_VOID);
MV_VOID mvBoardNetComplexConfigSet(MV_U32 ethConfig);
MV_PHY_NEGOTIATION_PORT_TYPE mvBoardPhyNegotiationTypeGet(MV_U32 ethPortNum);
#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif /* __INCmvBoardEnvLib39h */