fix: rtc: fixed rtc_set according to FE-3124064 (HW ERRATA 3124064)
According to FE-3124064:
- Description:
The device supports CPU write and read access to the RTC Time register
However, due to this erratum, Write to RTC TIME register may fail.
Read from RTC TIME register may fail.
Workaround:
Before writing to RTC TIME register, issue a dummy
write of 0x0 twice to RTC Status register.
RTC TIME register should be read twice, the second
read will return a proper value.
Configure maximum value (0x3FF) in write clock period in
RTC Mbus Bridge Timing Control register.
- Fixed rtc_set according to the workaround (write 0x0 to status register
twice before writing to RTC time register)
- Configure maximum value (0x3FF) in write clock period in
RTC Mbus Bridge Timing Control register.
- Fixed JIRA:1909, 1955
Change-Id: I11b36dc3fc20887dfdb8b59719c5cc868b1aa6c5
Signed-off-by: Bassel Saba <basselsa@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23309
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
diff --git a/board/mv_ebu/common/USP/mv_rtc2.c b/board/mv_ebu/common/USP/mv_rtc2.c
index be50d07..53a321e 100644
--- a/board/mv_ebu/common/USP/mv_rtc2.c
+++ b/board/mv_ebu/common/USP/mv_rtc2.c
@@ -77,7 +77,23 @@
void rtc_init(void)
{
/* Update RTC-MBUS bridge timing parameters */
+ #ifdef ERRATA_FE_3124064
+ /* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
+ * Description:
+ * The device supports CPU write and read access to the RTC Time register.
+ * However, due to this erratum, Write to RTC TIME register may fail.
+ * Read from RTC TIME register may fail.
+ * Workaround:
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
+ * RTC TIME register should be read twice, the second read will return a proper value.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
+ * Functional Impact After Workaround is applied:
+ * No functional impact after WA is applied
+ */
+ MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4FFF);
+#else
MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4CFA);
+#endif
rtc_ready = 1;
}
@@ -90,21 +106,23 @@
rtc_init();
time = RTC_READ_REG(RTC_TIME_REG_OFFS);
+#ifdef ERRATA_FE_3124064
/* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
* Description:
* The device supports CPU write and read access to the RTC Time register.
* However, due to this erratum, Write to RTC TIME register may fail.
* Read from RTC TIME register may fail.
* Workaround:
- * After writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
* RTC TIME register should be read twice, the second read will return a proper value.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
* Functional Impact After Workaround is applied:
* No functional impact after WA is applied
*/
time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
if ((time_check - time) > 1)
time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
- /* End of WA */
+#endif
to_tm(time_check, tm);
@@ -122,20 +140,22 @@
time = mktime(tm->tm_year, tm->tm_mon,
tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
+#ifdef ERRATA_FE_3124064
/* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
* Description:
* The device supports CPU write and read access to the RTC Time register.
* However, due to this erratum, Write to RTC TIME register may fail.
* Read from RTC TIME register may fail.
* Workaround:
- * After writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
* RTC TIME register should be read twice, the second read will return a proper value.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
* Functional Impact After Workaround is applied:
* No functional impact after WA is applied
*/
RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
- mdelay(100);
- /* End of SW WA */
+ RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
+#endif
RTC_WRITE_REG(time, RTC_TIME_REG_OFFS);
return 0;
diff --git a/include/configs/armada_38x.h b/include/configs/armada_38x.h
index 9ef8da3..a7b1624 100644
--- a/include/configs/armada_38x.h
+++ b/include/configs/armada_38x.h
@@ -727,4 +727,9 @@
#define CONFIG_STACKSIZE (1 << 20) /* regular stack - up to 4M (in case of exception)*/
+/*
+ * ERRATA
+ */
+#define ERRATA_FE_3124064
+
#endif /* __CONFIG_H */
