| ; initialize system |
| AREA.CLEAR |
| AREA |
| diag 16001 |
| |
| SYStem.RESet |
| |
| entry &coreMode |
| local &coreMode |
| |
| entry &core |
| local &core |
| |
| entry &ddrSpeed |
| local &ddrSpeed |
| |
| SYStem.CPU MV78460V7 |
| |
| if ("&coreMode"=="") |
| ( |
| area.res |
| area.c select |
| area.s select |
| w.area select |
| screen.always |
| |
| ; user selects core number |
| print "" |
| print "" |
| print "Please select SoC Mode:" |
| print "1) ARMv7 Single" |
| print "2) ARMv7 SMP" |
| print |
| enter &coreMode |
| area.res |
| wclear |
| ) |
| if &coreMode==1 |
| ( |
| ;First it is very importate to select the CPU first and then set the options, otherwise important options are cleared again |
| &core=1 |
| SYStem.CPU MV78460V7 |
| SYStem.CONFIG ETBBASE 0 |
| SYStem.MultiCore COREBASE 0xc2301000 |
| SYStem.MultiCore MEMORYACCESSPORT 0 |
| SYStem.MultiCore DEBUGACCESSPORT 1 |
| ) |
| else |
| ( |
| ;First it is very importate to select the CPU first and then set the options, otherwise important options are cleared again |
| ;&ncpus=2 |
| &core=1 |
| ;SYStem.RESet |
| |
| SYStem.CPU MV78460V7 |
| CORE.ASSIGN 1 ; first do a system.up with just one core to avoid a fatal error |
| SYStem.CONFIG ETBBASE 0 |
| SYStem.Up |
| |
| ; read the sample at reset high register to determine the number of active cpus |
| &ncpus=((data.long(SD:0xD0018234)>>3)&3)+1 |
| |
| if &ncpus==4 |
| ( |
| ; put cpu 1 in a loop and kick it out of reser |
| d.s 0xD0022224 %LONG 0xFFFF0040; |
| d.s 0xD0020808 %LONG 0x0; |
| |
| ; put cpu 2 in a loop and kick it out of reser |
| d.s 0xD0022324 %LONG 0xFFFF0040; |
| d.s 0xD0020810 %LONG 0x0; |
| |
| ; put cpu 3 in a loop and kick it out of reser |
| d.s 0xD0022424 %LONG 0xFFFF0040; |
| d.s 0xD0020818 %LONG 0x0; |
| SYStem.Down |
| CORE.ASSIGN 1,2,3,4 |
| |
| ) |
| else if &ncpus==2 ; it looks that when ncpus is set to 2 no system.up is possible |
| ( |
| ; put cpu 1 in a loop and kick it out of reser |
| d.s 0xD0022224 %LONG 0xFFFF0040; |
| d.s 0xD0020808 %LONG 0x0; |
| SYStem.Down |
| CORE.ASSIGN 1,2 |
| ) |
| system.option EnReset off |
| ) |
| |
| system.mode attach |
| system.Up |
| |
| ; set system settings according LE MMU |
| d.s C15:1 %LONG 0x00052078 |
| |
| if &core==1 |
| ( |
| if ("&ddrSpeed"=="") |
| ( |
| area.res |
| area.c select |
| area.s select |
| w.area select |
| screen.always |
| |
| ; user selects ddr speed |
| print "" |
| print "" |
| print "Please select DDR Speed:" |
| print "1) 400 Mhz" |
| print "2) 533 Mhz" |
| print "3) 667 Mhz" |
| print "4) 800 Mhz" |
| print "5) With trainning sequence" |
| print |
| enter &ddrSpeed |
| area.res |
| wclear |
| ) |
| if &ddrSpeed==1 |
| ( |
| ; 400MHZ DDR |
| print "" |
| print "Starting DRAM initialization:" |
| ; dram init |
| d.s 0xD0001400 %LONG 0x7300D03E ; DDR SDRAM Configuration Register |
| d.s 0xD0001404 %LONG 0x3630B840 ; Dunit Control Low Register |
| d.s 0xD0001408 %LONG 0x33137773 ; DDR SDRAM Timing (Low) Register |
| d.s 0xD000140C %LONG 0x36000C55 ; DDR SDRAM Timing (High) Register |
| d.s 0xD0001410 %LONG 0x04000000 ; DDR SDRAM Address Control Register |
| d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register |
| d.s 0xD0001418 %LONG 0x00000e00 ; DDR SDRAM Operation Register |
| d.s 0xD000141C %LONG 0x00000672 ; DDR SDRAM Mode Register |
| d.s 0xD0001420 %LONG 0x00000004 ; DDR SDRAM Extended Mode Register |
| d.s 0xD0001424 %LONG 0x0100F1FF ; Dunit Control High Register |
| d.s 0xD0001428 %LONG 0x000D6720 ; Dunit Control High Register |
| d.s 0xD000142C %LONG 0x014C2F38 ; Dunit Control High Register |
| d.s 0xD000147C %LONG 0x00006571 ; |
| |
| d.s 0xD0001494 %LONG 0x00010000 ; DDR SDRAM ODT Control (Low) Register |
| d.s 0xD0001498 %LONG 0x00000000 ; DDR SDRAM ODT Control (High) Register |
| d.s 0xD000149C %LONG 0x00000001 ; DDR Dunit ODT Control Register |
| ;d.s 0xD000149C %LONG 0x00000300 ; DDR Dunit ODT Control Register |
| |
| |
| ; First work with Mbus DRAM window at DRAM Init - 256MB in default |
| d.s 0xD00200EC %LONG 0x00000000 |
| |
| d.s 0xD00200E8 %LONG 0x1FFF0E00 |
| d.s 0xD0020184 %LONG 0x1FFFFFe1 |
| |
| ; Those registers should not be connected in this device, so just to be sure we will Zero them |
| d.s 0xD0001504 %LONG 0x1FFFFFF1 ; |
| d.s 0xD000150C %LONG 0x00000000 ; CS[1]n Size Register |
| d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register |
| d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register |
| |
| d.s 0xD0001538 %LONG 0x00000008 ; Read Data Sample Delays Register |
| d.s 0xD000153C %LONG 0x0000000A ; Read Data Ready Delay Register |
| |
| d.s 0xD00015D0 %LONG 0x00000830 ; MR0 |
| d.s 0xD00015D4 %LONG 0x00008044 ; MR1 |
| d.s 0xD00015D8 %LONG 0x00010208 ; MR2 |
| d.s 0xD00015DC %LONG 0x00018000 ; MR3 |
| |
| |
| d.s 0xD00015E4 %LONG 0x00203c18; ZQC Configuration Register |
| d.s 0xD00015EC %LONG 0xDE000025; DDR PHY |
| |
| print " [Done]" |
| LOCAL &status |
| LOCAL &bit |
| |
| print "Starting Read Leveling:" |
| &status=0 |
| &bit=31 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;read leveling values CL @ 400Mhz = 7 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ;PUP RdSampleDly (+CL) Phase RL ADLL value |
| ;0 2 1 0xC |
| d.s 0xD00016A0 %LONG 0xC002010C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 2 0 0x1C |
| d.s 0xD00016A0 %LONG 0xC042001C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 2 1 0x15 |
| d.s 0xD00016A0 %LONG 0xC0820115 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 2 0 0x19 |
| d.s 0xD00016A0 %LONG 0xC0C20019 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 2 1 0x8 |
| d.s 0xD00016A0 %LONG 0xC1020108 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 2 1 0 |
| d.s 0xD00016A0 %LONG 0xC1420100 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 2 1 0x11 |
| d.s 0xD00016A0 %LONG 0xC1820111 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 2 0 0x1B |
| d.s 0xD00016A0 %LONG 0xC1C2001B |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC2020117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| print " [Done]" |
| |
| print "Starting Write Leveling:" |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;write leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| |
| ;PUP |
| ;0 |
| |
| d.s 0xD00016A0 %LONG 0xC0005508 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 |
| |
| d.s 0xD00016A0 %LONG 0xC0409819 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 |
| |
| d.s 0xD00016A0 %LONG 0xC080650C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 |
| |
| d.s 0xD00016A0 %LONG 0xC0C0700F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 |
| |
| d.s 0xD00016A0 %LONG 0xC1004103 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 |
| |
| d.s 0xD00016A0 %LONG 0xC140A81D |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 |
| |
| d.s 0xD00016A0 %LONG 0xC180650C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 |
| |
| d.s 0xD00016A0 %LONG 0xC1C08013 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 |
| |
| d.s 0xD00016A0 %LONG 0xC2005D0A |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ; center DQS on read cycle |
| d.s 0xD00016A0 %LONG 0xC803000F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| print " [Done]" |
| |
| d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register |
| WAIT 2.s |
| print "Init Done ;-)" |
| ) |
| else if &ddrSpeed==2 |
| ( |
| ; 533 MHZ DDR |
| print "" |
| print "Starting DRAM initialization:" |
| ; dram init |
| d.s 0xD0001400 %LONG 0x7300D03E ; DDR SDRAM Configuration Register |
| d.s 0xD0001404 %LONG 0x3630B840 ; Dunit Control Low Register |
| d.s 0xD0001408 %LONG 0x33137773 ; DDR SDRAM Timing (Low) Register |
| d.s 0xD000140C %LONG 0x36000C55 ; DDR SDRAM Timing (High) Register |
| d.s 0xD0001410 %LONG 0x04000000 ; DDR SDRAM Address Control Register |
| d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register |
| d.s 0xD0001418 %LONG 0x00000e00 ; DDR SDRAM Operation Register |
| d.s 0xD000141C %LONG 0x00000672 ; DDR SDRAM Mode Register |
| d.s 0xD0001420 %LONG 0x00000004 ; DDR SDRAM Extended Mode Register |
| d.s 0xD0001424 %LONG 0x0100F1FF ; Dunit Control High Register |
| d.s 0xD0001428 %LONG 0x000D6720 ; Dunit Control High Register |
| d.s 0xD000142C %LONG 0x014C2F38 ; Dunit Control High Register |
| d.s 0xD000147C %LONG 0x00006571 ; |
| |
| d.s 0xD0001494 %LONG 0x00010000 ; DDR SDRAM ODT Control (Low) Register |
| d.s 0xD0001498 %LONG 0x00000000 ; DDR SDRAM ODT Control (High) Register |
| d.s 0xD000149C %LONG 0x00000001 ; DDR Dunit ODT Control Register |
| ;d.s 0xD000149C %LONG 0x00000300 ; DDR Dunit ODT Control Register |
| |
| |
| ; First work with Mbus DRAM window at DRAM Init - 256MB in default |
| d.s 0xD00200EC %LONG 0x00000000 |
| |
| d.s 0xD00200E8 %LONG 0x1FFF0E00 |
| d.s 0xD0020184 %LONG 0x1FFFFFe1 |
| |
| ; Those registers should not be connected in this device, so just to be sure we will Zero them |
| d.s 0xD0001504 %LONG 0x1FFFFFF1 ; |
| d.s 0xD000150C %LONG 0x00000000 ; CS[1]n Size Register |
| d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register |
| d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register |
| |
| d.s 0xD0001538 %LONG 0x00000008 ; Read Data Sample Delays Register |
| d.s 0xD000153C %LONG 0x0000000A ; Read Data Ready Delay Register |
| |
| d.s 0xD00015D0 %LONG 0x00000830 ; MR0 |
| d.s 0xD00015D4 %LONG 0x00008044 ; MR1 |
| d.s 0xD00015D8 %LONG 0x00010208 ; MR2 |
| d.s 0xD00015DC %LONG 0x00018000 ; MR3 |
| |
| |
| d.s 0xD00015E4 %LONG 0x00203c18; ZQC Configuration Register |
| d.s 0xD00015EC %LONG 0xDE000025; DDR PHY |
| |
| print " [Done]" |
| LOCAL &status |
| LOCAL &bit |
| |
| print "Starting Read Leveling:" |
| &status=0 |
| &bit=31 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;read leveling values CL @ 533Mhz = 7 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ;PUP RdSampleDly (+CL) Phase RL ADLL value |
| ;0 1 4 12 |
| d.s 0xD00016A0 %LONG 0xC002040C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC0420117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 1 4 27 |
| d.s 0xD00016A0 %LONG 0xC082041B |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC0C20117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 1 4 10 |
| d.s 0xD00016A0 %LONG 0xC102040A |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC1420117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 1 4 25 |
| d.s 0xD00016A0 %LONG 0xC1820419 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC1C20117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 1 1 23 |
| d.s 0xD00016A0 %LONG 0xC2020117 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| print " [Done]" |
| |
| print "Starting Write Leveling:" |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;write leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| |
| ;PUP |
| ;0 |
| |
| d.s 0xD00016A0 %LONG 0xC0008113 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 |
| |
| d.s 0xD00016A0 %LONG 0xC0404504 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 |
| |
| d.s 0xD00016A0 %LONG 0xC0808514 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 |
| |
| d.s 0xD00016A0 %LONG 0xC0C09418 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 |
| |
| d.s 0xD00016A0 %LONG 0xC1006D0E |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 |
| |
| d.s 0xD00016A0 %LONG 0xC1405508 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 |
| |
| d.s 0xD00016A0 %LONG 0xC1807D12 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 |
| |
| d.s 0xD00016A0 %LONG 0xC1C0b01F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 |
| |
| d.s 0xD00016A0 %LONG 0xC2005D0A |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ; center DQS on read cycle |
| d.s 0xD00016A0 %LONG 0xC803000F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| print " [Done]" |
| |
| d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register |
| WAIT 2.s |
| print "Init Done ;-)" |
| |
| ) |
| else if &ddrSpeed==3 |
| ( |
| ; 667 MHZ DDR |
| print "" |
| print "Starting DRAM initialization:" |
| ; dram init |
| d.s 0xD0001400 %LONG 0x7301D453 ; DDR SDRAM Configuration Register |
| d.s 0xD0001404 %LONG 0x3630B840 ; Dunit Control Low Register |
| d.s 0xD0001408 %LONG 0x5415a998 ; DDR SDRAM Timing (Low) Register |
| d.s 0xD000140C %LONG 0x36000C6A ; DDR SDRAM Timing (High) Register |
| d.s 0xD0001410 %LONG 0x04000000 ; DDR SDRAM Address Control Register |
| d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register |
| d.s 0xD0001418 %LONG 0x00000e00 ; DDR SDRAM Operation Register |
| d.s 0xD000141C %LONG 0x00000672 ; DDR SDRAM Mode Register |
| d.s 0xD0001420 %LONG 0x00000004 ; DDR SDRAM Extended Mode Register |
| d.s 0xD0001424 %LONG 0x0100D1FF ; Dunit Control High Register ( 2 :1 - bits 15:12 = 0xD ) |
| d.s 0xD0001428 %LONG 0x000F8830 ; Dunit Control High Register |
| d.s 0xD000142C %LONG 0x214C2F38 ; Dunit Control High Register ( 2:1 - bit 29 = '1' ) |
| d.s 0xD000147C %LONG 0x0000c871 ; |
| |
| ; 2:1 |
| d.s 0xD00014a8 %LONG 0x00000101 ; |
| d.s 0xD0020220 %LONG 0x00000007 ; |
| |
| d.s 0xD0001494 %LONG 0x00010000 ; DDR SDRAM ODT Control (Low) Register |
| d.s 0xD0001498 %LONG 0x00000000 ; DDR SDRAM ODT Control (High) Register |
| d.s 0xD000149C %LONG 0x00000001 ; DDR Dunit ODT Control Register |
| ;d.s 0xD000149C %LONG 0x00000300 ; DDR Dunit ODT Control Register |
| |
| |
| ; First work with Mbus DRAM window at DRAM Init - 256MB in default |
| d.s 0xD00200EC %LONG 0x00000000 |
| |
| d.s 0xD00200E8 %LONG 0x1FFF0E00 |
| d.s 0xD0020184 %LONG 0x1FFFFFe1 |
| |
| ; Those registers should not be connected in this device, so just to be sure we will Zero them |
| d.s 0xD0001504 %LONG 0x1FFFFFF1 ; |
| d.s 0xD000150C %LONG 0x00000000 ; CS[1]n Size Register |
| d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register |
| d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register |
| |
| d.s 0xD0001524 %LONG 0x0000C800 ; DDR I/O register |
| |
| d.s 0xD0001538 %LONG 0x0000000b ; Read Data Sample Delays Register |
| d.s 0xD000153C %LONG 0x0000000d ; Read Data Ready Delay Register |
| |
| ;d.s 0xD0001538 %LONG 0x0000000c ; Read Data Sample Delays Register CL=10 |
| ;d.s 0xD000153C %LONG 0x0000000e ; Read Data Ready Delay Register CL=10 |
| |
| d.s 0xD00015D0 %LONG 0x00000a50 ; MR0 |
| ;d.s 0xD00015D0 %LONG 0x00000a60 ; MR0 CL=10 |
| d.s 0xD00015D4 %LONG 0x00008044 ; MR1 |
| d.s 0xD00015D8 %LONG 0x00010210 ; MR2 |
| d.s 0xD00015DC %LONG 0x00018000 ; MR3 |
| |
| |
| d.s 0xD00015E4 %LONG 0x00203c18; ZQC Configuration Register |
| ;d.s 0xD00015EC %LONG 0xDE000025; DDR PHY |
| d.s 0xD00015EC %LONG 0xF800AA25; |
| |
| print " [Done]" |
| LOCAL &status |
| LOCAL &bit |
| |
| LOCAL &readlvl |
| &readlvl=1 |
| |
| if (&readlvl>0) |
| ( |
| |
| print "Starting Read Leveling:" |
| &status=0 |
| &bit=31 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;read leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ;PUP RdSampleDly (+CL) Phase RL ADLL value |
| ;0 2 1 3 |
| d.s 0xD00016A0 %LONG 0xC0020103 |
| ;d.s 0xD00016A0 %LONG 0xC0020108 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 2 0 18 |
| d.s 0xD00016A0 %LONG 0xC0420012 |
| ;d.s 0xD00016A0 %LONG 0xC042001C |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 2 1 19 |
| d.s 0xD00016A0 %LONG 0xC0820113 |
| ;d.s 0xD00016A0 %LONG 0xC082020b |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 2 0 18 |
| d.s 0xD00016A0 %LONG 0xC0C20012 |
| ;d.s 0xD00016A0 %LONG 0xC0C2001C |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 2 1 0 |
| d.s 0xD00016A0 %LONG 0xC1020100 |
| ;d.s 0xD00016A0 %LONG 0xC1020106 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 2 0 22 |
| d.s 0xD00016A0 %LONG 0xC1420016 |
| ;d.s 0xD00016A0 %LONG 0xC142001E |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 2 1 9 |
| d.s 0xD00016A0 %LONG 0xC1820109 |
| ;d.s 0xD00016A0 %LONG 0xC182010D |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 2 0 16 |
| d.s 0xD00016A0 %LONG 0xC1C20010 |
| ;d.s 0xD00016A0 %LONG 0xC1C20018 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 2 0 28 |
| d.s 0xD00016A0 %LONG 0xC2020112 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| print " [Done]" |
| ) |
| print "Starting Write Leveling:" |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;write leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| |
| ;PUP |
| ;0 |
| |
| d.s 0xD00016A0 %LONG 0xC000b11F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 |
| |
| d.s 0xD00016A0 %LONG 0xC040690D |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 |
| |
| d.s 0xD00016A0 %LONG 0xC0803600 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 |
| |
| d.s 0xD00016A0 %LONG 0xC0C0a81D |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 |
| |
| d.s 0xD00016A0 %LONG 0xC1009919 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 |
| |
| d.s 0xD00016A0 %LONG 0xC1407911 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 |
| |
| d.s 0xD00016A0 %LONG 0xC180ad1e |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 |
| |
| d.s 0xD00016A0 %LONG 0xC1C04d06 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 |
| |
| d.s 0xD00016A0 %LONG 0xC2008514 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ; center DQS on read cycle |
| d.s 0xD00016A0 %LONG 0xC803000F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| print " [Done]" |
| |
| d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register |
| WAIT 2.s |
| |
| print "Init Done ;-)" |
| ) |
| else if &ddrSpeed==4 |
| ( |
| ; 800 MHZ DDR |
| print "" |
| print "Starting DRAM initialization:" |
| ; dram init |
| d.s 0xD0001400 %LONG 0x7301D453 ; DDR SDRAM Configuration Register |
| d.s 0xD0001404 %LONG 0x3630B840 ; Dunit Control Low Register |
| d.s 0xD0001408 %LONG 0x5415a998 ; DDR SDRAM Timing (Low) Register |
| d.s 0xD000140C %LONG 0x36000C6A ; DDR SDRAM Timing (High) Register |
| d.s 0xD0001410 %LONG 0x04000000 ; DDR SDRAM Address Control Register |
| d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register |
| d.s 0xD0001418 %LONG 0x00000e00 ; DDR SDRAM Operation Register |
| d.s 0xD000141C %LONG 0x00000672 ; DDR SDRAM Mode Register |
| d.s 0xD0001420 %LONG 0x00000004 ; DDR SDRAM Extended Mode Register |
| d.s 0xD0001424 %LONG 0x0100D1FF ; Dunit Control High Register ( 2 :1 - bits 15:12 = 0xD ) |
| d.s 0xD0001428 %LONG 0x000F8830 ; Dunit Control High Register |
| d.s 0xD000142C %LONG 0x214C2F38 ; Dunit Control High Register ( 2:1 - bit 29 = '1' ) |
| d.s 0xD000147C %LONG 0x0000c871 ; |
| |
| ; 2:1 |
| d.s 0xD00014a8 %LONG 0x00000101 ; |
| d.s 0xD0020220 %LONG 0x00000007 ; |
| |
| d.s 0xD0001494 %LONG 0x00010000 ; DDR SDRAM ODT Control (Low) Register |
| d.s 0xD0001498 %LONG 0x00000000 ; DDR SDRAM ODT Control (High) Register |
| d.s 0xD000149C %LONG 0x00000001 ; DDR Dunit ODT Control Register |
| ;d.s 0xD000149C %LONG 0x00000300 ; DDR Dunit ODT Control Register |
| |
| |
| ; First work with Mbus DRAM window at DRAM Init - 256MB in default |
| d.s 0xD00200E8 %LONG 0x1FFF0E00 |
| d.s 0xD0020184 %LONG 0x1FFFFFe1 |
| |
| |
| |
| ; Those registers should not be connected in this device, so just to be sure we will Zero them |
| d.s 0xD0001504 %LONG 0x1FFFFFF1 ; |
| d.s 0xD000150C %LONG 0x00000000 ; CS[1]n Size Register |
| d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register |
| d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register |
| |
| d.s 0xD0001524 %LONG 0x0000C800 ; DDR I/O register |
| |
| d.s 0xD0001538 %LONG 0x0000000b; Read Data Sample Delays Register |
| ;d.s 0xD0001538 %LONG 0x0000000E ; Read Data Sample Delays Register |
| ;d.s 0xD000153C %LONG 0x0000000F; Read Data Ready Delay Register |
| d.s 0xD000153C %LONG 0x0000000d; Read Data Ready Delay Register |
| |
| ;d.s 0xD0001538 %LONG 0x0000000c ; Read Data Sample Delays Register CL=10 |
| ;d.s 0xD000153C %LONG 0x0000000e ; Read Data Ready Delay Register CL=10 |
| |
| d.s 0xD00015D0 %LONG 0x00000a50 ; MR0 |
| d.s 0xD00015D4 %LONG 0x00008044 ; MR1 |
| d.s 0xD00015D8 %LONG 0x00010210 ; MR2 |
| d.s 0xD00015DC %LONG 0x00018000 ; MR3 |
| |
| |
| d.s 0xD00015E4 %LONG 0x00203c18; ZQC Configuration Register |
| d.s 0xD00015EC %LONG 0xDE000025; DDR PHY |
| |
| print " [Done]" |
| LOCAL &status |
| LOCAL &bit |
| |
| LOCAL &readlvl |
| &readlvl=1 |
| |
| if (&readlvl>0) |
| ( |
| |
| print "Starting Read Leveling:" |
| &status=0 |
| &bit=31 |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;read leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ;PUP RdSampleDly (+CL) Phase RL ADLL value |
| ;0 2 1 29 |
| ;d.s 0xD00016A0 %LONG 0xC002011D |
| d.s 0xD00016A0 %LONG 0xC0020213 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 2 1 8 |
| d.s 0xD00016A0 %LONG 0xC0420108 |
| |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 2 2 16 |
| d.s 0xD00016A0 %LONG 0xC0820210 |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 2 0 8 |
| d.s 0xD00016A0 %LONG 0xC0C20108 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 2 1 26 |
| d.s 0xD00016A0 %LONG 0xC102011A |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 2 1 13 |
| ;d.s 0xD00016A0 %LONG 0xC142010D |
| d.s 0xD00016A0 %LONG 0xC1420300 |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 2 2 4 |
| d.s 0xD00016A0 %LONG 0xC1820204 |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 2 1 6 |
| d.s 0xD00016A0 %LONG 0xC1C20106 |
| |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 2 1 20 |
| d.s 0xD00016A0 %LONG 0xC2020112 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| print " [Done]" |
| ) |
| print "Starting Write Leveling:" |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;write leveling values |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| |
| ;PUP |
| ;0 |
| |
| d.s 0xD00016A0 %LONG 0xC000620B |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;1 |
| |
| d.s 0xD00016A0 %LONG 0xC0408D16 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;2 |
| |
| d.s 0xD00016A0 %LONG 0xC0806A0D |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;3 |
| |
| d.s 0xD00016A0 %LONG 0xC0C03D02 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;4 |
| |
| d.s 0xD00016A0 %LONG 0xC1004a05 |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;5 |
| |
| d.s 0xD00016A0 %LONG 0xC140A11B |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;6 |
| |
| d.s 0xD00016A0 %LONG 0xC1805E0A |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;7 |
| |
| d.s 0xD00016A0 %LONG 0xC1C06D0E |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;8 |
| |
| d.s 0xD00016A0 %LONG 0xC200AD1E |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| ; center DQS on read cycle |
| d.s 0xD00016A0 %LONG 0xC803000F |
| |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| WHILE (&status>0) |
| ( |
| &status=Data.Long(SD:0xD00016A0) |
| &status=&status&(1<<31) |
| ) |
| |
| print " [Done]" |
| |
| d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register |
| WAIT 2.s |
| |
| print "Init Done ;-)" |
| ) |
| else if &ddrSpeed==5 |
| ( |
| |
| |
| |
| ;Enable L2 Block => Set L2Exist |
| D.S SD:0xD0020200 %LE %LONG 0x01000102 |
| |
| ; Configure L@ ways 0-3 to be SRAM |
| D.S SD:0xD000878C %LE %LONG 0x40000000 |
| D.S SD:0xD000878C %LE %LONG 0x40010001 |
| D.S SD:0xD000878C %LE %LONG 0x40020002 |
| D.S SD:0xD000878C %LE %LONG 0x40030003 |
| |
| ; Open the SRAM window 0 to the 512K SRAM |
| D.S SD:0xD0020240 %LE %LONG 0x40000701 |
| print "Finished setting the L2 as SRAM" |
| |
| ; Close fastpath window |
| D.S SD:0xD0020184 %LE %LONG 0x0 |
| |
| ; Set stack |
| REGISTER.SET R13 0x40040000 |
| |
| WAIT 100.ms |
| |
| print "Init Done ;-)" |
| |
| D.LOAD bin_hdr\bin_hdr.elf |
| go |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ) |
| |
| |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ) |
| ; end of if core == 1 for dram init |
| |
| ; Set program counter at program start to be ready for start |
| ; Register.Set pc 0xffff0000 |
| ; R.S PC 670000 |
| enddo |
