/******************************************************************************
*              Copyright (c) Marvell International Ltd. and its affiliates
*
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* alternative licensing terms.
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* and/or modify this File under the following licensing terms.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*  -   Redistributions of source code must retain the above copyright notice,
*       this list of conditions and the following disclaimer.
*  -   Redistributions in binary form must reproduce the above copyright
*       notice, this list of conditions and the following disclaimer in the
*       documentation and/or other materials provided with the distribution.
*  -    Neither the name of Marvell nor the names of its contributors may be
*       used to endorse or promote products derived from this software without
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*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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*******************************************************************************
* mvDdr3TrainingIpStatic.h
*
* DESCRIPTION:
*
*
* FILE REVISION NUMBER:
*       $Revision: 11 $
*
*******************************************************************************/


#ifndef _MV_DDR3_TRAININGIP_STATIC_H_
#define _MV_DDR3_TRAININGIP_STATIC_H_

#include "mvDdr3TrainingIpDef.h"
#include "mvDdr3TrainingIp.h"

#ifdef __cplusplus
   extern "C"
   {
#endif


/******************************** defined ***************************************/

/******************************************************************************/
/* Definitions of INTERFACE registers                                             */
/******************************************************************************/


/******************************************************************************/
/* Definitions of PHY registers                                               */
/******************************************************************************/


/************************* Structures ***********************************************/

typedef struct 
{
   GT_U32 dqsDelay; /* DQS delay (mSec) */
   GT_U32 ckDelay;  /* CK Delay  (mSec) */
      
} TripDelayElement;

typedef struct
{
	GT_U32				siliconDelay;
	TripDelayElement	*packageTraceArr;
	TripDelayElement	*boardTraceArr;

} MV_HWS_TIP_STATIC_CONFIG_INFO;


/************************* Declarations ***********************************************/

GT_STATUS    ddr3TipRunStaticAlg
( 
    GT_U32  devNum,
    MV_HWS_DDR_FREQ freq
);

GT_STATUS ddr3TipInitStaticConfigDb
(
    GT_U32                          devNum,
	MV_HWS_TIP_STATIC_CONFIG_INFO*	staticConfigInfo
);

GT_STATUS ddr3TipInitSpecificRegConfig
(
    GT_U32              devNum,
	RegData				*regConfigArr
);

GT_STATUS    ddr3TipStaticPhyInitController
(
    GT_U32    devNum
);

#ifdef __cplusplus
}
#endif

#endif /* _MV_DDR3_TRAININGIP_STATIC_H_ */