diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingLeveling.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingLeveling.h
index c6682f2..8de6e9e 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingLeveling.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingLeveling.h
@@ -65,7 +65,7 @@
 );
 
 
-GT_U32 mvHwsDdr3TipMaxCSGet(void);
+GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum);
 
 #ifdef __cplusplus
    }
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
index b640b25..231643d 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
@@ -578,7 +578,7 @@
 	GT_U32 regData1;
 #endif
 	GT_U32 readData[MAX_INTERFACE_NUM];
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 
 	/*Title print*/
 	for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM; interfaceId++)
@@ -1432,7 +1432,7 @@
     GT_32 reg = (direction == 0) ? WRITE_CENTRALIZATION_PHY_REG : READ_CENTRALIZATION_PHY_REG;
     MV_HWS_ACCESS_TYPE  pupAccess;
     GT_U32 uiCs;
-    GT_U32 maxCs = mvHwsDdr3TipMaxCSGet();
+    GT_U32 maxCs = mvHwsDdr3TipMaxCSGet(devNum);
 	GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
 
     RepeatNum = RepeatNum;
@@ -1551,7 +1551,7 @@
     GT_32 reg = (direction == 0) ? WL_PHY_REG : RL_PHY_REG;
     MV_HWS_ACCESS_TYPE  pupAccess;
     GT_U32 uiCs;
-    GT_U32 maxCs = mvHwsDdr3TipMaxCSGet();
+    GT_U32 maxCs = mvHwsDdr3TipMaxCSGet(devNum);
 	GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
     RepeatNum = RepeatNum;
 	RepeatNum = 3;
@@ -1589,7 +1589,7 @@
 		}
 		/*Save Leveling value(after algorithm run)*/
 		readAdllValue(ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x1F );
-		readPhaseValue(ctrlLevelPhase, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x3<<6 );
+		readPhaseValue(ctrlLevelPhase, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x7<<6 );
 		if(direction == 0)
 		{
 			readAdllValue(ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index b31afae..d14ff58 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -2260,7 +2260,7 @@
     InitCntrParam   initCntrPrm;
     GT_STATUS retVal = GT_OK;
 	GT_U32 interfaceId;
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 
 #ifdef DDR_VIEWER_TOOL
 	if(debugTraining == DEBUG_LEVEL_TRACE)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
index 3bfca59..cdf4c6c 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
@@ -111,16 +111,26 @@
 /*****************************************************************************
 mvHwsDdr3TipMaxCSGet
 ******************************************************************************/
-GT_U32 mvHwsDdr3TipMaxCSGet(void)
+GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum)
 {
-  GT_U32 c_cs;
+  GT_U32 c_cs,interfaceId=0,busId=0;
+  GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
   static GT_U32 max_cs=0;
 
-  if (!max_cs){
-	 for(c_cs = 0;c_cs < NUM_OF_CS; c_cs++){
-		VALIDATE_IF_ACTIVE(topologyMap->interfaceParams[0].asBusParams[0].csBitmask, c_cs)
+  if (!max_cs)
+  {
+      CHECK_STATUS(ddr3TipGetFirstActiveIf((GT_U8)devNum, topologyMap->interfaceActiveMask, &interfaceId));
+ 	  for(busId=0; busId<octetsPerInterfaceNum; busId++)
+      {
+          VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, busId)
+          break;
+      }
+
+      for(c_cs = 0;c_cs < NUM_OF_CS; c_cs++)
+      {
+		VALIDATE_IF_ACTIVE(topologyMap->interfaceParams[interfaceId].asBusParams[busId].csBitmask, c_cs)
 		max_cs++;
-		}
+	  }
   }
   return max_cs;
 }
@@ -135,7 +145,7 @@
 )
 {
     GT_U32 data, mask;
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 	GT_U32 busNum, interfaceId, clVal;
     MV_HWS_SPEED_BIN speedBinIndex;
 	GT_U32 csEnableRegVal[MAX_INTERFACE_NUM] = {0}; /* save current CS value */
@@ -358,7 +368,7 @@
 )
 {
 	GT_U32 c_cs, interfaceId, cs_mask = 0;
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 
 /*	in TRAINIUNG reg (0x15b0) write 0x80000008 | cs_mask:
 	TrnStart
@@ -392,7 +402,7 @@
 )
 {
 	GT_U32 c_cs, interfaceId, cs_mask = 0;
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 
 	/* in TRAINIUNG reg (0x15b0) write 0x80000040 | cs_mask:
 	TrnStart
@@ -742,7 +752,7 @@
 	GT_U8   WLValues[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM];
 	GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
 	GT_U32 csMask0[MAX_INTERFACE_NUM]={0};
-	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+	GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 	GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
 
     for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
index ad206dd..358a674 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
@@ -57,7 +57,7 @@
 GT_U8 ADLL_SHIFT_val[MAX_INTERFACE_NUM][MAX_BUS_NUM] ;
 MV_HWS_PATTERN pbsPattern = PATTERN_VREF;
 
-extern GT_U32 mvHwsDdr3TipMaxCSGet(void);
+extern GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum);
 /************************** pre declarations ******************************/
 extern MV_HWS_TOPOLOGY_MAP *topologyMap;
 extern GT_U32 maskResultsDqRegMap[];
@@ -616,7 +616,7 @@
 )
 {
     GT_U32 currCs;
-    GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
+    GT_U32 max_cs = mvHwsDdr3TipMaxCSGet(devNum);
 
    for(currCs = 0; currCs < max_cs; currCs++)
    {
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
index 0ce3ac1..bae76b2 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
@@ -74,7 +74,7 @@
 static GT_U32 uiXorRegsBaseBackup[MAX_CS];
 static GT_U32 uiXorRegsMaskBackup[MAX_CS];
 
-extern GT_U32 mvHwsDdr3TipMaxCSGet(void);
+extern GT_U32 mvHwsDdr3TipMaxCSGet(GT_U32 devNum);
 
 GT_VOID mvSysXorInit(GT_U32 uiNumOfCS, GT_U32 uiCsEna, GT_U32 csSize, GT_U32 baseDelta)
 {
@@ -394,7 +394,7 @@
 	MV_U32 uiCsEna = 0;
     mvPrintf("DDR Training Sequence - Start scrubbing \n");
 
-	max_cs = mvHwsDdr3TipMaxCSGet();
+	max_cs = mvHwsDdr3TipMaxCSGet(0);
 	for (cs_c = 0; cs_c < max_cs; cs_c++)
 		uiCsEna |= 1 << cs_c;