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#ifndef __INCmvSFlashSpecH
#define __INCmvSFlashSpecH

#ifdef __cplusplus
extern "C" {
#endif

/* Constants */
#define		MV_SFLASH_READ_CMND_LENGTH		    5		/* 1B opcode + 3B address */
#define		MV_SFLASH_SE_CMND_LENGTH		    5		/* 1B opcode + 3B address */
#define		MV_SFLASH_BE_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_PP_CMND_LENGTH		    5		/* 1B opcode + 3B address */
#define		MV_SFLASH_WREN_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_WRDI_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_RDID_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_RDID_REPLY_LENGTH		    3		/* 1B manf ID and 2B device ID */
#define		MV_SFLASH_RDSR_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_RDSR_REPLY_LENGTH		    1		/* 1B status */
#define		MV_SFLASH_WRSR_CMND_LENGTH		    2		/* 1B opcode + 1B status value */
#define		MV_SFLASH_DP_CMND_LENGTH		    1		/* 1B opcode */
#define		MV_SFLASH_RES_CMND_LENGTH		    1		/* 1B opcode */

/* Status Register Bit Masks */
#define		MV_SFLASH_STATUS_REG_WIP_OFFSET	    0	    /* bit 0; write in progress */
#define		MV_SFLASH_STATUS_REG_WP_OFFSET	    2       /* bit 2-4; write protect option */
#define		MV_SFLASH_STATUS_REG_SRWD_OFFSET	7	    /* bit 7; lock status register write */
#define		MV_SFLASH_STATUS_REG_WIP_MASK	    (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET)
#define		MV_SFLASH_STATUS_REG_SRWD_MASK	    (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET)

#define		MV_SFLASH_MAX_WAIT_LOOP			    1000000
#define     MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP  0x50000000

#define		MV_SFLASH_DEFAULT_RDID_OPCD		    0x9F	/* Default Read ID */
#define     MV_SFLASH_DEFAULT_WREN_OPCD         0x06	/* Default Write Enable */
#define     MV_SFLASH_NO_SPECIFIC_OPCD          0x00

/********************************/
/*  ST M25Pxxx Device Specific  */
/********************************/

/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define     MV_M25PXXX_ST_MANF_ID               0x20
#define     MV_M25P32_DEVICE_ID                 0x2016
#define     MV_M25P32_MAX_SPI_FREQ              20000000    /* 20MHz */
#define     MV_M25P32_MAX_FAST_SPI_FREQ         50000000    /* 50MHz */
#define     MV_M25P32_FAST_READ_DUMMY_BYTES     1
#define	    MV_M25P32_ADDR_CYC_CNT	        3
#define     MV_M25P64_DEVICE_ID                 0x2017
#define     MV_M25P64_MAX_SPI_FREQ              20000000    /* 20MHz */
#define     MV_M25P64_MAX_FAST_SPI_FREQ         50000000    /* 50MHz */
#define     MV_M25P64_FAST_READ_DUMMY_BYTES     1
#define	    MV_M25P64_ADDR_CYC_CNT	        3
#define     MV_M25P128_DEVICE_ID                0x2018
#define     MV_M25P128_MAX_SPI_FREQ             20000000    /* 20MHz */
#define     MV_M25P128_MAX_FAST_SPI_FREQ        50000000    /* 50MHz */
#define     MV_M25P128_FAST_READ_DUMMY_BYTES    1
#define	    MV_M25P128_ADDR_CYC_CNT	        3
#define     MV_M25PX64_DEVICE_ID                 0x7117
#define     MV_M25PX64_MAX_SPI_FREQ              20000000    /* 20MHz */
#define     MV_M25PX64_MAX_FAST_SPI_FREQ         50000000    /* 50MHz */
#define     MV_M25PX64_FAST_READ_DUMMY_BYTES     1
#define	    MV_M25PX64_ADDR_CYC_CNT	         3


/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define     MV_M25Q128_DEVICE_ID                0xBA18
#define     MV_M25Q128_MAX_SPI_FREQ             20000000    /* 20MHz */
#define     MV_M25Q128_MAX_FAST_SPI_FREQ        50000000    /* 50MHz */
#define     MV_M25Q128_FAST_READ_DUMMY_BYTES    1
#define     MV_M25Q128_ADDR_CYC_CNT             3


/* Sector Sizes and population per device model*/
#define     MV_M25P32_SECTOR_SIZE               0x10000 /* 64K */
#define     MV_M25P64_SECTOR_SIZE               0x10000 /* 64K */
#define     MV_M25P128_SECTOR_SIZE              0x40000 /* 256K */
#define     MV_M25Q128_SECTOR_SIZE              0x10000 /* 64K */
#define     MV_M25P32_SECTOR_NUMBER             64
#define     MV_M25P64_SECTOR_NUMBER             128
#define     MV_M25P128_SECTOR_NUMBER            64
#define     MV_M25Q128_SECTOR_NUMBER            256
#define	    MV_M25P_PAGE_SIZE			0x100   /* 256 byte */
#define	    MV_M25Q_PAGE_SIZE			0x100   /* 256 byte */

#define		MV_M25P_WREN_CMND_OPCD			    0x06	/* Write Enable */
#define		MV_M25P_WRDI_CMND_OPCD			    0x04	/* Write Disable */
#define		MV_M25P_RDID_CMND_OPCD			    0x9F	/* Read ID */
#define		MV_M25P_RDSR_CMND_OPCD			    0x05	/* Read Status Register */
#define		MV_M25P_WRSR_CMND_OPCD			    0x01	/* Write Status Register */
#define		MV_M25P_READ_CMND_OPCD			    0x03	/* Sequential Read */
#define		MV_M25P_FAST_RD_CMND_OPCD		    0x0B	/* Fast Read */
#define		MV_M25P_PP_CMND_OPCD			    0x02	/* Page Program */
#define		MV_M25P_SE_CMND_OPCD			    0xD8	/* Sector Erase */
#define		MV_M25P_BE_CMND_OPCD			    0xC7	/* Bulk Erase */
#define		MV_M25P_RES_CMND_OPCD			    0xAB	/* Read Electronic Signature */
#define		MV_M25P_ADDR_CYC_CNT			3

/* Status Register Write Protect Bit Masks - 3bits */
#define		MV_M25P_STATUS_REG_WP_MASK	        (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_NONE              (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_64           (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_32           (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_16           (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_8            (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_4            (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_1_OF_2            (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_M25P_STATUS_BP_ALL               (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)

/************************************/
/*  MXIC MX25L6405 Device Specific  */
/************************************/

/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define     MV_MXIC_MANF_ID                     0xC2
#define     MV_MX25L1605_DEVICE_ID              0x2015
#define     MV_MX25L1605_MAX_SPI_FREQ           20000000    /* 20MHz */
#define     MV_MX25L1605_MAX_FAST_SPI_FREQ      50000000    /* 50MHz */
#define     MV_MX25L1605_FAST_READ_DUMMY_BYTES  1
#define	MV_MX25L1605_ADDR_CYC_CNT	    3
#define     MV_MX25L3205_DEVICE_ID              0x2016
#define     MV_MX25L3205_MAX_SPI_FREQ           20000000    /* 20MHz */
#define     MV_MX25L3205_MAX_FAST_SPI_FREQ      50000000    /* 50MHz */
#define     MV_MX25L3205_FAST_READ_DUMMY_BYTES  1
#define	MV_MX25L3205_ADDR_CYC_CNT	    3
#define     MV_MX25L6405_DEVICE_ID              0x2017
#define     MV_MX25L6405_MAX_SPI_FREQ           20000000    /* 20MHz */
#define     MV_MX25L6405_MAX_FAST_SPI_FREQ      50000000    /* 50MHz */
#define     MV_MX25L6405_FAST_READ_DUMMY_BYTES  1
#define	MV_MX25L6405_ADDR_CYC_CNT	    3
#define	MV_MX25L257_DEVICE_ID		    0x2019
#define	MV_MX25L257_MAX_SPI_FREQ      	    20000000    /* 20MHz */
#define	MV_MX25L257_MAX_FAST_SPI_FREQ       50000000    /* 104MHz */
#define	MV_MX25L257_FAST_READ_DUMMY_BYTES   1
#define	MV_MX25L257_ADDR_CYC_CNT	    4
#define     MV_MXIC_DP_EXIT_DELAY               30          /* 30 ms */

/* Sector Sizes and population per device model*/
#define     MV_MX25L1605_SECTOR_SIZE            0x10000 /* 64K */
#define     MV_MX25L3205_SECTOR_SIZE            0x10000 /* 64K */
#define     MV_MX25L6405_SECTOR_SIZE            0x10000 /* 64K */
#define	    MV_MX25L257_SECTOR_SIZE        	0x10000 /* 64K */
#define     MV_MX25L1605_SECTOR_NUMBER          32
#define     MV_MX25L3205_SECTOR_NUMBER          64
#define     MV_MX25L6405_SECTOR_NUMBER          128
#define     MV_MX25L257_SECTOR_NUMBER 		512
#define		MV_MXIC_PAGE_SIZE			        0x100   /* 256 byte */

#define		MV_MX25L_WREN_CMND_OPCD			    0x06	/* Write Enable */
#define		MV_MX25L_WRDI_CMND_OPCD			    0x04	/* Write Disable */
#define		MV_MX25L_RDID_CMND_OPCD			    0x9F	/* Read ID */
#define		MV_MX25L_RDSR_CMND_OPCD			    0x05	/* Read Status Register */
#define		MV_MX25L_WRSR_CMND_OPCD			    0x01	/* Write Status Register */
#define		MV_MX25L_READ_CMND_OPCD			    0x03	/* Sequential Read */
#define		MV_MX25L_FAST_RD_CMND_OPCD		    0x0B	/* Fast Read */
#define		MV_MX25L_PP_CMND_OPCD			    0x02	/* Page Program */
#define		MV_MX25L_SE_CMND_OPCD			    0xD8	/* Sector Erase */
#define		MV_MX25L_BE_CMND_OPCD			    0xC7	/* Bulk Erase */
#define     MV_MX25L_DP_CMND_OPCD               0xB9    /* Deep Power Down */
#define		MV_MX25L_RES_CMND_OPCD			    0xAB	/* Read Electronic Signature */

/* Status Register Write Protect Bit Masks - 4bits */
#define		MV_MX25L_STATUS_REG_WP_MASK	        (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_NONE             (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_128         (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_64          (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_32          (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_16          (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_8           (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_4           (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_1_OF_2           (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     MV_MX25L_STATUS_BP_ALL              (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)

/************************************/
/*  SPANSION S25FL128P Device Specific  */
/************************************/

/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define     MV_SPANSION_MANF_ID                     	0x01
#define     MV_S25FL128_DEVICE_ID              		0x2018
#define     MV_S25FL128_MAX_SPI_FREQ           		33000000    /* 33MHz */
#define     MV_S25FL128_MAX_FAST_SPI_FREQ        	104000000    /* 104MHz */
#define     MV_S25FL128_FAST_READ_DUMMY_BYTES    	1
#define	    MV_S25FL128_ADDR_CYC_CNT	        	3

/* Sector Sizes and population per device model*/
#define     MV_S25FL128_SECTOR_SIZE            			0x40000 /* 256K */
#define     MV_S25FL128_SECTOR_NUMBER          			64
#define	    MV_S25FL_PAGE_SIZE			        	0x100   /* 256 byte */

#define		MV_S25FL_WREN_CMND_OPCD			    0x06	/* Write Enable */
#define		MV_S25FL_WRDI_CMND_OPCD			    0x04	/* Write Disable */
#define		MV_S25FL_RDID_CMND_OPCD			    0x9F	/* Read ID */
#define		MV_S25FL_RDSR_CMND_OPCD			    0x05	/* Read Status Register */
#define		MV_S25FL_WRSR_CMND_OPCD			    0x01	/* Write Status Register */
#define		MV_S25FL_READ_CMND_OPCD			    0x03	/* Sequential Read */
#define		MV_S25FL_FAST_RD_CMND_OPCD		    0x0B	/* Fast Read */
#define		MV_S25FL_PP_CMND_OPCD			    0x02	/* Page Program */
#define		MV_S25FL_SE_CMND_OPCD			    0xD8	/* Sector Erase */
#define		MV_S25FL_BE_CMND_OPCD			    0xC7	/* Bulk Erase */
#define     	MV_S25FL_DP_CMND_OPCD               	    0xB9    	/* Deep Power Down */
#define		MV_S25FL_RES_CMND_OPCD			    0xAB	/* Read Electronic Signature */

/* Status Register Write Protect Bit Masks - 4bits */
#define		MV_S25FL_STATUS_REG_WP_MASK	        (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_NONE             	(0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_128         	(0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_64          	(0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_32          	(0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_16          	(0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_8           	(0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_4           	(0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_1_OF_2           	(0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define     	MV_S25FL_STATUS_BP_ALL              	(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)


/************************************/
/*  WINBOND W25Q32 Device Specific  */
/************************************/

/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
#define	MV_WINBOND_MANF_ID			0xEF
#define	MV_WB25Q32_DEVICE_ID			0x4016
#define	MV_WB25Q32_MAX_SPI_FREQ			50000000	/* 50MHz */
#define	MV_WB25Q32_MAX_FAST_SPI_FREQ		104000000	/* 104MHz */
#define	MV_WB25Q32_FAST_READ_DUMMY_BYTES	1
#define	MV_WB25Q32_ADDR_CYC_CNT			3

/* Sector Sizes and population per device model*/
#define	MV_WB25Q32_SECTOR_SIZE			0x1000	/* 4K */
#define	MV_WB25Q32_SECTOR_NUMBER		1024
#define	MV_WB25Q_PAGE_SIZE			0x100	/* 256 byte */

#define	MV_WB25Q_WREN_CMND_OPCD			0x06	/* Write Enable */
#define	MV_WB25Q_WRDI_CMND_OPCD			0x04	/* Write Disable */
#define	MV_WB25Q_RDID_CMND_OPCD			0x9F	/* Read ID */
#define	MV_WB25Q_RDSR_CMND_OPCD			0x05	/* Read Status Register */
#define	MV_WB25Q_WRSR_CMND_OPCD			0x01	/* Write Status Register */
#define	MV_WB25Q_READ_CMND_OPCD			0x03	/* Sequential Read */
#define	MV_WB25Q_FAST_RD_CMND_OPCD		0x0B	/* Fast Read */
#define	MV_WB25Q_PP_CMND_OPCD			0x02	/* Page Program */
#define	MV_WB25Q_SE_CMND_OPCD			0x20	/* Sector Erase */
#define	MV_WB25Q_BE_CMND_OPCD			0xC7	/* Bulk Erase */
#define	MV_WB25Q_DP_CMND_OPCD			0xB9	/* Deep Power Down */
#define	MV_WB25Q_RES_CMND_OPCD			0xAB	/* Read Electronic Signature */

/* Status Register Write Protect Bit Masks - 4bits */
#define	MV_WB25Q_STATUS_REG_WP_MASK		(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_NONE			(0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_128		(0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_64		(0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_32		(0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_16		(0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_8		(0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_4		(0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_1_OF_2		(0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
#define	MV_WB25Q_STATUS_BP_ALL			(0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)

#ifdef __cplusplus
}
#endif


#endif /* __INCmvSFlashSpecH */