Merge remote-tracking branch 'gfiber-internal/vendor_drops'
Merge Marvell patches-u-boot-2013.01-2015_T1.0p16 patchset.
Change-Id: Ice925c8accb490118d501a47f02651275deaf20c
diff --git a/.gitignore b/.gitignore
index df3f234..b10e919 100755
--- a/.gitignore
+++ b/.gitignore
@@ -3,10 +3,8 @@
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
#
-# Normal rules
+# Normal rules
#
-omri.pl
-comri.pl
.gitignore
*.rej
*.orig
diff --git a/Makefile b/Makefile
index 4d412d7..07debc4 100755
--- a/Makefile
+++ b/Makefile
@@ -178,7 +178,7 @@
# load ARCH, BOARD, and CPU configuration
include $(obj)include/config.mk
-export ARCH CPU BOARD VENDOR SOC DDR3LIB DDRTYPE
+export ARCH CPU BOARD VENDOR SOC DDR3LIB DDRTYPE DDR4SUBLIB
# set default to nothing for native builds
ifeq ($(HOSTARCH),$(ARCH))
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 5ff7719..c0a81e3 100755
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -91,13 +91,14 @@
}
#if defined (CONFIG_OF_LIBFDT) || defined (MV_DDR_L2_ALIGNMENT)
-u64 l2_base = (_4G - _1G); /* used for memory node update in Device tree or for memory tags */
+u64 l2_base = (_4G - _1G); /* used for memory node update in Device tree, or for memory tags */
#endif
#ifdef CONFIG_OF_LIBFDT
extern void mvCpuIfMbusWindowSet(u32 base, u32 size);
int fixup_memory_node(void *blob)
{
+ char *env;
#ifndef CONFIG_MARVELL
bd_t *bd = gd->bd;
#endif
@@ -105,23 +106,30 @@
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
+ /* - Binary header prioritize IO memory space via L2 filtering at 3.0GB, in order
+ * to ensure 'hit' on internal registers IO access (located at 0xd0000000 by default)
+ * - Although U-Boot updates internal register base to 0xf1000000 (3.75GB), Address
+ * decoding supports only windows size aligned to power of 2.
+ */
+ env = getenv("limit_dram_size");
+ if (env && ((strcmp(env, "yes") == 0) || (strcmp(env, "Yes") == 0)))
+ {
+ printf("\nLimit DDR size at 3GB due to power of 2 requirement of Address decoding\n");
+ l2_base = (_4G - _1G);
+ } else
+ l2_base = (_4G - _256M);
#ifdef CONFIG_MARVELL
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->dram_hw_info[bank].start;
size[bank] = gd->dram_hw_info[bank].size;
- /* - Binary header preserves IO memory space via L2 filtering at 3.25GB, in order
- * to avoid conflict with internal registers IO located 0xd0000000.
- * - U-Boot updates internal register base to 0xf1000000 (3.75GB)
- * - if DRAM CS size reaches 4G --> also limit CS memory node to 3.75GB */
-
- /* due to LSP issue with unaligned window sizes to power of 2 (3.75GB),
- * L2 is temporary set to 3GB: update DT memory node accordingly */
+ /* - If memory size reached 4GB, limit last CS size according to highest power of 2.
+ * (when using 2x2GB, last CS will be limited to 1GB) */
if ((start[bank] + size[bank]) == _4G) {
size[bank] = (l2_base - start[bank]);
- /* LSP is temporarily wrongly deriving DRAM windows limitation from MBus.
- * as a temp WA, align Mbus bridge with L2 base */
+ /* set IO area to higher priority than DRAM window, by aligning MBUS bridge with L2 base.
+ * (Linux mainline MBUS driver uses MBUS configuration to derive L2 filtering) */
mvCpuIfMbusWindowSet(l2_base, _4G - l2_base);
}
}
@@ -221,15 +229,15 @@
if ((start - 1 + size) == 0xFFFFFFFF) {
params->u.mem.start = start;
#ifdef MV_DDR_L2_ALIGNMENT
-/* - Binary header preserves IO memory space via L2 filtering at 3.25GB, in order
- * to avoid conflict with internal registers IO located 0xd0000000.
- * - U-Boot updates internal register base to 0xf1000000 (3.75GB)
- * - if DRAM CS size reaches 4G --> also limit memory tags to 3.75GB */
-
-/* Temporary: due to LSP (3.10) issue with unaligned window sizes to power of 2 (3.75GB),
- * L2 is set to 3GB: update memory tags accordingly */
+ /* - Binary header prioritize IO memory space via L2 filtering at 3.0GB, in order
+ * to ensure 'hit' on internal registers IO access (located at 0xd0000000 by default)
+ * - Although U-Boot updates internal register base to 0xf1000000 (3.75GB), Address
+ * decoding supports only windows size aligned to power of 2.
+ * - If memory size reached 4GB, limit last CS size according to highest power of 2.
+ * (when using 2x2GB, last CS will be limited to 1GB) */
params->u.mem.size = (l2_base - start);
-/* align Mbus bridge with L2 base */
+
+ /* set IO area to higher priority than DRAM window, by aligning MBUS bridge with L2 base*/
mvCpuIfMbusWindowSet(l2_base, _4G - l2_base);
#else
params->u.mem.size = (0xF0000000 - start);
diff --git a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.c
index c708e03..8282375 100644
--- a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.c
@@ -1487,6 +1487,28 @@
}
/*******************************************************************************
+* mvBoardIsSwitchConnected
+*
+* DESCRIPTION:
+* This routine returns port's connection status, this route provide a unified inerface
+* for other modules to call without care of the switch conntection mode - external or internal
+* if the switch is connected
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 1 - if ethPortNum is connected to switch, 0 otherwise
+*
+*******************************************************************************/
+MV_STATUS mvBoardIsSwitchConnected(void)
+{
+ return mvBoardIsInternalSwitchConnected();
+}
+
+/*******************************************************************************
* mvBoardFreqModesNumGet
*
* DESCRIPTION:
@@ -3050,7 +3072,8 @@
MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber)
{
MV_U32 i;
-
+ if (usbPortNumber >= mvCtrlUsbMaxGet())
+ return MV_FALSE;
/* Go over existing USB ports in board structures: test existence of requested USB Type/port */
for (i = 0; i < board->numBoardUsbInfo; i++)
if (board->pBoardUsbInfo[i].isActive && board->pBoardUsbInfo[i].usbType == usbTypeID &&
@@ -3085,3 +3108,40 @@
return board->numPicGpioInfo;
}
+/*******************************************************************************
+* mvBoardIsTdmConnected
+*
+* DESCRIPTION:
+* This routine returns MV_TRUE if TDM module is connected
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - TDM is connected
+* MV_FALSE - otherwise.
+*
+*******************************************************************************/
+MV_BOOL mvBoardIsTdmConnected()
+{
+ /* TDM is not supported on a375 */
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvBoardIsUsb3PortDevice
+* DESCRIPTION: return true USB3 port is in device mode
+*
+* INPUT: port - port number
+* OUTPUT: None.
+* RETURN: MV_TRUE: if port is set to device mode
+* MV_FALSE: otherwise
+*******************************************************************************/
+MV_BOOL mvBoardIsUsb3PortDevice(MV_U32 port)
+{
+ /* Since usb3 device is not supported on current board return false */
+ return MV_FALSE;
+}
diff --git a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.h
index 1f20e8a..e1739de 100644
--- a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvLib.h
@@ -493,6 +493,7 @@
MV_STATUS mvBoardIsInternalSwitchConnectedToPort(MV_U32 ethPortNum);
MV_STATUS mvBoardIsInternalSwitchConnected(void);
MV_U32 mvBoardSwitchPortForceLinkGet(MV_U32 switchIdx);
+MV_STATUS mvBoardIsSwitchConnected(void);
MV_BOOL mvBoardIsLvdsModuleConnected(void);
MV_BOOL mvBoardIsLcdDviModuleConnected(void);
MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum);
@@ -520,6 +521,8 @@
MV_NAND_IF_MODE mvBoardNandIfGet(void);
MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber);
MV_U8 mvBoardPICGpioGet(MV_U32 *picGpioMppInfo);
+MV_BOOL mvBoardIsTdmConnected(void);
+MV_BOOL mvBoardIsUsb3PortDevice(MV_U32 port);
#ifdef __cplusplus
}
diff --git a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvSpec.h
index b01b973..9494171 100644
--- a/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/a375/armada_375_family/boardEnv/mvBoardEnvSpec.h
@@ -148,7 +148,7 @@
#define DB_88F6720_GPP_POL_MID 0x0
#define DB_88F6720_GPP_POL_HIGH 0x0
-
+#define MV_TDM_OFFSET (0xB0000)
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvBoardEnvSpech */
diff --git a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.c
index 0ca1cea..3484236 100644
--- a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.c
@@ -228,7 +228,30 @@
boardPexInfo->boardPexIfNum = pexIfNum;
}
-
+/******************************************************************************
+* mvCtrlIsUsbSerDesConnected
+*
+* DESCRIPTION:detect usb3 port if connected to serdes.
+* check if SerDes lane is connected to USB3 host
+*
+*
+* INPUT: None
+*
+* OUTPUT: None
+*
+* RETURN:return true if usb physical port is connected , false otherwise.
+*
+*
+*******************************************************************************/
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort)
+{
+ int usb3HostNum = mvCtrlUsb3HostMaxGet();
+ int maxSerDesLanes = mvCtrlUsb3MaxGet();
+ if (usbPort >= maxSerDesLanes && usb3HostNum > maxSerDesLanes){
+ return MV_FALSE;
+ }
+ return MV_TRUE;
+}
MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MV_67xx_INDEX_MAX] = {
/* 6720 */
diff --git a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.h
index 5ad1090..1282dc0 100644
--- a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvLib.h
@@ -282,6 +282,7 @@
MV_VOID mvCtrlSysConfigInit(MV_VOID);
MV_U32 mvCtrlSysConfigGet(MV_CONFIG_TYPE_ID configField);
MV_U32 mvCtrlGetCpuNum(MV_VOID);
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort);
MV_U32 mvCtrlGetQuadNum(MV_VOID);
MV_STATUS mvCtrlUpdatePexId(MV_VOID);
MV_BOOL mvCtrlIsValidSatR(MV_VOID);
diff --git a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvSpec.h
index 5fbd31a..420deda 100644
--- a/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/a375/armada_375_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -130,6 +130,8 @@
#define MV_USB3_PHYS_OFFSET(dev) (0x58000)
#define MV_USB2_USB3_REGS_OFFSET(unitType, dev) (unitType == USB_UNIT_ID ? \
MV_USB_REGS_OFFSET(dev) : MV_USB3_PHYS_OFFSET(dev))
+#define MV_USB3_DEVICE_REGS_OFFSET MV_USB_REGS_OFFSET(0)
+#define MV_USB3_DEVICE_USB2_REGS_OFFSET (0x54100)
#define MV_XOR_REGS_OFFSET(unit) (0x60800)
#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000))
#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000))
diff --git a/board/mv_ebu/a375/mv_main_a375.c b/board/mv_ebu/a375/mv_main_a375.c
index b5f2a3e..3840113 100755
--- a/board/mv_ebu/a375/mv_main_a375.c
+++ b/board/mv_ebu/a375/mv_main_a375.c
@@ -294,7 +294,6 @@
*(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
mvBoardDebugLed(4);
- mv_print_map();
return 0;
}
@@ -311,7 +310,7 @@
env = getenv("mtdids");
if (!env) {
#if defined(MV_NAND) && defined(MV_INCLUDE_SPI)
- setenv("mtdids", "nand0=armada-nand;spi0=spi_flash");
+ setenv("mtdids", "nand0=armada-nand,spi0=spi_flash");
#elif defined(MV_NAND)
setenv("mtdids", "nand0=armada-nand");
#elif defined(MV_INCLUDE_SPI)
@@ -492,6 +491,12 @@
if (!env)
setenv("initrd_name", "uInitrd");
+#ifdef CONFIG_CMD_SOURCE
+ env = getenv("run_script");
+ if (!env)
+ setenv("run_script", "no");
+#endif
+
/* netbsd boot arguments */
env = getenv("netbsd_en");
if ( !env || ( ((strcmp(env, "no") == 0) || (strcmp(env, "No") == 0) )))
@@ -1024,6 +1029,7 @@
#endif
/* init the units decode windows */
misc_init_r_dec_win();
+ mv_print_map();
memset((void*)CONFIG_SYS_LOAD_ADDR, 0, CONFIG_SYS_MIN_HDR_DEL_SIZE);
mvBoardDebugLed(6);
@@ -1044,7 +1050,12 @@
#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH)
mvBoardEgigaPhyInit();
#endif
-
+#ifdef CONFIG_CMD_SOURCE
+ /* run saved script */
+ env = getenv("run_script");
+ if (env && strcmp(env, "yes") == 0)
+ run_command("mvsource run", 0);
+#endif
return 0;
}
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
index ddb356e..766ec4d 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
@@ -214,6 +214,10 @@
MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT0); // 88x2011_RST_n
MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT15); // SD_RST_n
#endif
+
+ /* Call callback function for board specific post GPP configuration */
+ if (board->gppPostConfigCallBack)
+ board->gppPostConfigCallBack(board);
}
/*******************************************************************************
@@ -570,7 +574,10 @@
tclk = ((tclk & (1 << 15)) >> 15);
switch (tclk) {
case 0:
- return MV_BOARD_TCLK_250MHZ;
+ if (mvCtrlModelGet() == MV_6811_DEV_ID)
+ return MV_BOARD_TCLK_166MHZ; /* device 381/2 (6811/21) use 166MHz instead of 250MHz */
+ else
+ return MV_BOARD_TCLK_250MHZ;
case 1:
return MV_BOARD_TCLK_200MHZ;
default:
@@ -664,7 +671,7 @@
for (i = 0; i < board->numBoardGppInfo; i++) {
if (board->pBoardGppInfo[i].devClass == gppClass) {
- if (indexFound == index)
+ if (indexFound == index && (MV_U32)board->pBoardGppInfo[i].gppPinNum != -1)
return (MV_U32)board->pBoardGppInfo[i].gppPinNum;
else
indexFound++;
@@ -725,6 +732,110 @@
return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0);
}
+#ifdef MV_USB_VBUS_CYCLE
+/*******************************************************************************
+* mvBoardIoExpanderTypeGet
+*
+* DESCRIPTION:
+* Return the Config type fields information for a given Config type class.
+*
+* INPUT:
+* configClass - The Config type field to return the information for.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BOARD_CONFIG_TYPE_INFO struct with mask, offset and register number.
+*
+*******************************************************************************/
+MV_STATUS mvBoardIoExpanderTypeGet(MV_IO_EXPANDER_TYPE_ID ioClass,
+ MV_BOARD_IO_EXPANDER_TYPE_INFO *ioInfo)
+{
+ MV_U32 i;
+
+ /* verify existence of requested config type, pull its data */
+ for (i = 0; i < board->numBoardIoExpPinInfo; i++)
+ if (board->pBoardIoExpPinInfo[i].ioFieldid == ioClass) {
+ *ioInfo = board->pBoardIoExpPinInfo[i];
+ return MV_OK;
+ }
+
+ DB(mvOsPrintf("%s: Error: requested IO expander ID was not found (%d)\n",
+ __func__, ioClass));
+ return MV_ERROR;
+}
+
+/*******************************************************************************
+* mvBoardIoExpValSet - write a specified value to IO Expanders
+*
+* DESCRIPTION:
+* This function writes specified value to IO Expanders
+*
+* INPUT:
+* ioInfo - relevant IO Expander information
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_U8 :return requested value , if TWSI read was succesfull, else 0xFF.
+*
+*******************************************************************************/
+MV_STATUS mvBoardIoExpValSet(MV_BOARD_IO_EXPANDER_TYPE_INFO *ioInfo, MV_U8 value, MV_BOOL isOutput)
+{
+ MV_U8 readVal, configVal;
+
+ if (ioInfo == NULL) {
+ mvOsPrintf("%s: Error: Write to IO Expander failed (invalid Expander info)\n", __func__);
+ return MV_ERROR;
+ }
+
+ /* Read direction (output/input) Value */
+ if (mvBoardTwsiGet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum,
+ ioInfo->regNum + 4, &configVal, 1) != MV_OK) {
+ mvOsPrintf("%s: Error: Read Configuration from IO Expander failed\n", __func__);
+ return MV_ERROR;
+ }
+
+ /* Modify direction (output/input) value of requested pin */
+ if (isOutput)
+ configVal &= ~(1 << ioInfo->offset); /* output marked as 0: clean bit of old value */
+ else
+ configVal |= (1 << ioInfo->offset); /* input marked as 1: set bit of old value */
+ if (mvBoardTwsiSet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum,
+ ioInfo->regNum + 4, &configVal, 1) != MV_OK) {
+ mvOsPrintf("%s: Error: Enable Write to IO Expander at 0x%x failed\n", __func__
+ , mvBoardTwsiAddrGet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum));
+ return MV_ERROR;
+ }
+
+ /* configure output value, only for output directed IO */
+ if (!isOutput)
+ return MV_OK;
+
+ /* Read Output Value */
+ if (mvBoardTwsiGet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum,
+ ioInfo->regNum, &readVal, 1) != MV_OK) {
+ mvOsPrintf("%s: Error: Read Output value from IO Expander failed\n", __func__);
+ return MV_ERROR;
+ }
+
+ /* Modify */
+ readVal &= ~(1 << ioInfo->offset); /* clean bit of old value */
+ readVal |= (value << ioInfo->offset);
+
+ /* Write output value*/
+ if (mvBoardTwsiSet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum,
+ ioInfo->regNum, &readVal, 1) != MV_OK) {
+ mvOsPrintf("%s: Error: Write to IO Expander at 0x%x failed\n", __func__
+ , mvBoardTwsiAddrGet(BOARD_TWSI_IO_EXPANDER, ioInfo->expanderNum));
+ return MV_ERROR;
+ }
+
+ return MV_OK;
+}
+
/*******************************************************************************
* mvBoardUSBVbusGpioPinGet - return Vbus input GPP
*
@@ -746,26 +857,68 @@
}
/*******************************************************************************
-* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP
+* mvUsbVbusGppSet - SET USB VBUS signal via GPIO
*
* DESCRIPTION:
-*
-* INPUT:
-* int devNo.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* GPIO pin number. The function return -1 for bad parameters.
-*
+** INPUT: gppNo - gpp pin Number.
+** OUTPUT: None.
+** RETURN: None.
*******************************************************************************/
-MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId)
+MV_VOID mvUsbVbusGppSet(int gppNo)
{
- return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId);
+ MV_U32 regVal;
+
+ /* MPP Control Register - set mpp as GPP (value = 0)*/
+ regVal = MV_REG_READ(mvCtrlMppRegGet((unsigned int)(gppNo / 8)));
+ regVal &= ~(0xf << ((gppNo % 8) * 4));
+ MV_REG_WRITE(mvCtrlMppRegGet((unsigned int)(gppNo / 8)), regVal);
+
+ if (gppNo < 32) {
+ /* GPIO Data Out Enable Control Register - set to output */
+ mvGppTypeSet(0, (1 << gppNo), MV_GPP_OUT & (1 << gppNo));
+ /* GPIO output Data Value Register - set as high */
+ mvGppValueSet(0, (1 << gppNo), (1 << gppNo));
+ } else {
+ /* GPIO Data Out Enable Control Register - set to output */
+ mvGppTypeSet(1, (1 << (gppNo - 32)), MV_GPP_OUT & (1 << (gppNo - 32)));
+ /* GPIO output Data Value Register - set as high */
+ mvGppValueSet(1, (1 << (gppNo - 32)), (1 << (gppNo - 32)));
+ }
}
/*******************************************************************************
+* mvBoardUsbVbusSet - Set USB VBUS signal before detection
+*
+* DESCRIPTION:
+* this routine sets VBUS signal via GPIO or via I2C IO expander
+*
+** INPUT: int dev - USB Host number
+** OUTPUT: None.
+** RETURN: None.
+*******************************************************************************/
+MV_VOID mvBoardUsbVbusSet(int dev)
+{
+ MV_32 gppNo = mvBoardUSBVbusGpioPinGet(dev);
+
+ /* Some of Marvell boards control VBUS signal via I2C IO expander unit */
+#ifndef CONFIG_CUSTOMER_BOARD_SUPPORT
+ MV_BOARD_IO_EXPANDER_TYPE_INFO ioInfo;
+
+ /* if VBUS signal is Controlled via I2C IO Expander on board*/
+ if (mvBoardIoExpanderTypeGet(MV_IO_EXPANDER_USB_VBUS, &ioInfo) != MV_ERROR) {
+ mvBoardIoExpValSet(&ioInfo, 1, MV_TRUE);
+ return;
+ }
+#endif
+
+ /* else if VBUS signal is Controlled via GPIO on board*/
+ if (gppNo != MV_ERROR)
+ mvUsbVbusGppSet(gppNo);
+
+}
+#endif /* MV_USB_VBUS_CYCLE */
+
+/*******************************************************************************
* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins
*
* DESCRIPTION:
@@ -931,8 +1084,14 @@
bootSrc = mvBoardBootDeviceGroupSet();
if (MSAR_0_BOOT_NAND_NEW == bootSrc)
mvBoardModuleConfigSet(MV_MODULE_NAND_ON_BOARD);
- else if (MSAR_0_BOOT_SDIO == bootSrc)
+ else if (MSAR_0_BOOT_SDIO == bootSrc) {
mvBoardModuleConfigSet(MV_MODULE_DB381_MMC_8BIT_ON_BOARD);
+ /* Enable NAND access if the SDIO is not using NAND MPPs.
+ The SDIO MPPs overlap NAND ones in SDIO-8bit access mode,
+ when boot attr2 == 40 */
+ if (mvBoardBootAttrGet(mvBoardBootDeviceGet(), 2) != 40)
+ mvBoardModuleConfigSet(MV_MODULE_NAND_ON_BOARD);
+ }
}
/*******************************************************************************
@@ -1009,8 +1168,7 @@
struct _mvBoardMppModule nandModule[6] = MPP_NAND_MODULE;
struct _mvBoardMppModule sdioModule[4] = MPP_SDIO_MODULE;
struct _mvBoardMppModule tdmModule[2] = MPP_TDM_MODULE;
- struct _mvBoardMppModule i2sModule = MPP_I2S_MODULE;
- struct _mvBoardMppModule spdifModule = MPP_SPDIF_MODULE;
+ struct _mvBoardMppModule audioModule = MPP_AUDIO_MODULE;
struct _mvBoardMppModule nandOnBoard[4] = MPP_NAND_ON_BOARD;
struct _mvBoardMppModule mini_pcie0_OnBoard = MPP_GP_MINI_PCIE0;
struct _mvBoardMppModule mini_pcie1_OnBoard = MPP_GP_MINI_PCIE1;
@@ -1038,17 +1196,20 @@
if (mvBoardIsModuleConnected(MV_MODULE_SDIO))
mvModuleMppUpdate(4, sdioModule);
+ /* Microsemi LE88266DLC (VE880 series) */
if (mvBoardIsModuleConnected(MV_MODULE_SLIC_TDM_DEVICE))
mvModuleMppUpdate(2, tdmModule);
- if (mvBoardIsModuleConnected(MV_MODULE_I2S_DEVICE))
- mvModuleMppUpdate(1, &i2sModule);
-
- if (mvBoardIsModuleConnected(MV_MODULE_SPDIF_DEVICE))
- mvModuleMppUpdate(1, &spdifModule);
+ if (mvBoardIsModuleConnected(MV_MODULE_I2S_DEVICE) ||
+ mvBoardIsModuleConnected(MV_MODULE_SPDIF_DEVICE))
+ mvModuleMppUpdate(1, &audioModule);
if (mvBoardIsModuleConnected(MV_MODULE_NAND_ON_BOARD))
mvModuleMppUpdate(4, nandOnBoard);
+
+ /* Sillab SI32261-F */
+ if (mvBoardIsTdmConnected() == MV_TRUE)
+ mvModuleMppUpdate(2, tdmModule);
break;
case DB_GP_68XX_ID:
miniPcie0_sata0_selector = mvBoardSatRRead(MV_SATR_GP_SERDES1_CFG); /* 0 = SATA0 , 1 = PCIe0 */
@@ -1281,7 +1442,7 @@
}
/*******************************************************************************
-* mvBoardIsInternalSwitchConnected
+* mvBoardIsSwitchConnected
*
* DESCRIPTION:
* This routine returns port's connection status
@@ -1296,9 +1457,12 @@
* 1 - if ethPortNum is connected to switch, 0 otherwise
*
*******************************************************************************/
-MV_STATUS mvBoardIsInternalSwitchConnected(void)
+MV_STATUS mvBoardIsSwitchConnected(void)
{
- return MV_FALSE;
+ if ((board == ((MV_BOARD_INFO *)-1)) || (board->switchInfoNum == 0) || (board->pSwitchInfo == NULL))
+ return MV_FALSE;
+
+ return board->pSwitchInfo[0].isEnabled;
}
/*******************************************************************************
@@ -1402,10 +1566,11 @@
*******************************************************************************/
MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum)
{
- /* port is connected, if it's identified as R/SGMII, and has a valid corresponding MAC info entry */
+ /* port is connected, if it's enabled, identified as R/SGMII, and has a valid corresponding MAC info entry */
if ((ethPortNum <= board->numBoardMacInfo) &&
+ (board->pBoardMacInfo[ethPortNum].boardMacEnabled == MV_TRUE) &&
((mvCtrlPortIsSerdesSgmii(ethPortNum) ||
(mvCtrlPortIsRgmii(ethPortNum) && mvBoardPhyAddrGet(ethPortNum) != -1)) ||
(mvCtrlPortIsSerdesRxaui(ethPortNum) && mvBoardPhyAddrGet(ethPortNum) != -1)))
@@ -2075,6 +2240,8 @@
gBoardId = CUSTOMER_BOARD_ID0;
#elif CONFIG_CUSTOMER_BOARD_1
gBoardId = CUSTOMER_BOARD_ID1;
+ #elif CONFIG_CLEARFOG_BOARD
+ gBoardId = A38X_CLEARFOG_BOARD_ID;
#elif CONFIG_GFCH100
gBoardId = GFCH100_ID;
#endif
@@ -2325,7 +2492,10 @@
*******************************************************************************/
MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx)
{
- return BOARD_ETH_SWITCH_SMI_SCAN_MODE;
+ if (!mvBoardIsSwitchConnected())
+ return -1;
+
+ return board->pSwitchInfo[switchIdx].smiScanMode;
}
/*******************************************************************************
@@ -2346,7 +2516,119 @@
*******************************************************************************/
MV_U32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx)
{
- return -1;
+ if (!mvBoardIsSwitchConnected())
+ return -1;
+
+ return board->pSwitchInfo[switchIdx].cpuPort;
+}
+
+/*******************************************************************************
+* mvBoardSwitchIsRgmii - Check if the Switch connected to RGMII port
+*
+* DESCRIPTION:
+* This routine returns if the switch connected to RGMII port
+*
+* INPUT:
+* switchIdx - index of the switch. Only 0 is supported.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Status of switch type
+*
+*******************************************************************************/
+MV_BOOL mvBoardSwitchCpuPortIsRgmii(MV_U32 switchIdx)
+{
+ if (!mvBoardIsSwitchConnected())
+ return MV_FALSE;
+
+ return board->pSwitchInfo[switchIdx].isCpuPortRgmii;
+}
+
+/*******************************************************************************
+* mvBoardSwitchPhyAddrGet - Get the the Ethernet Switch PHY address
+*
+* DESCRIPTION:
+* This routine returns the Switch PHY address, -1 else.
+*
+* INPUT:
+* switchIdx - index of the switch. Only 0 is supported.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* the Switch PHY address, -1 if the switch is not connected.
+*
+*******************************************************************************/
+MV_32 mvBoardSwitchPhyAddrGet(MV_U32 switchIdx)
+{
+ if (!mvBoardIsSwitchConnected())
+ return -1;
+
+ return board->pSwitchInfo[switchIdx].quadPhyAddr;
+}
+
+/*******************************************************************************
+* mvBoardSwitchConnectedPortGet -
+*
+* DESCRIPTION:
+* This routine returns the switch port connected to the ethPort
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_32 mvBoardSwitchConnectedPortGet(MV_U32 ethPort)
+{
+ if (!mvBoardIsSwitchConnected())
+ return -1;
+
+ return board->pSwitchInfo[0].connectedPort[ethPort];
+}
+
+/*******************************************************************************
+* mvBoardModuleSwitchInfoUpdate - Update Board information switch module structures
+*
+* DESCRIPTION:
+* Update board information switch module structures according to switch detection
+*
+* INPUT:
+* switchDetected - switch module is detected or not
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvBoardModuleSwitchInfoUpdate(MV_BOOL switchDetected)
+{
+ int i = 0;
+
+ if ((board == ((MV_BOARD_INFO *)-1))) {
+ mvOsPrintf("%s %d:Board unknown.\n", __func__, __LINE__);
+ return;
+ }
+
+ if (switchDetected) {
+ for (i = 0; i < board->switchInfoNum; i++)
+ if (board->pSwitchInfo != NULL)
+ board->pSwitchInfo[i].isEnabled = MV_TRUE;
+ } else {
+ for (i = 0; i < board->switchInfoNum; i++)
+ if (board->pSwitchInfo != NULL)
+ board->pSwitchInfo[i].isEnabled = MV_FALSE;
+
+ board->switchInfoNum = 0;
+ }
}
/*******************************************************************************
@@ -3384,8 +3666,49 @@
return board->nandIfMode;
}
}
+/*******************************************************************************
+* mvBoardIsTdmConnected
+*
+* DESCRIPTION:
+* This routine returns MV_TRUE if TDM module is connected
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - TDM is connected
+* MV_FALSE - otherwise.
+*
+*******************************************************************************/
+MV_BOOL mvBoardIsTdmConnected()
+{
+ return board->isTdmConnected;
+}
/*******************************************************************************
+* mvBoardTdmConnectionSet
+*
+* DESCRIPTION:
+* This routine sets if TDM module is connected or not.
+*
+* INPUT:
+* isConnected - indicated if TDM module is connected.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvBoardTdmConnectionSet(MV_BOOL isConnected)
+{
+ board->isTdmConnected = isConnected;
+}
+/*******************************************************************************
* mvBoardisSdioConnected
* DESCRIPTION: return true if SDIO connected on board
*
@@ -3452,3 +3775,45 @@
return MV_FALSE;
}
+/*******************************************************************************
+* mvBoardAudioConnectionGet
+*
+* DESCRIPTION:
+* This routine returns MV_TRUE if SPDIF/I2S is connected
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - SPDIF/I2S is connected
+* MV_FALSE - otherwise.
+*
+*******************************************************************************/
+MV_BOOL mvBoardIsAudioConnected()
+{
+ return board->isAudioConnected;
+}
+
+/*******************************************************************************
+* mvBoardAudioConnectionSet
+*
+* DESCRIPTION:
+* This routine sets if SPDIF/I2S module is connected or not.
+*
+* INPUT:
+* isConnected - indicated if SPDIF/I2S is connected.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvBoardAudioConnectionSet(MV_BOOL isConnected)
+{
+ board->isAudioConnected = isConnected;
+}
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.h
index 68ed322..9225f33 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.h
@@ -175,10 +175,11 @@
MV_MODULE_SDIO = BIT6, /* SDIO board SLM 1361 */
MV_MODULE_SGMII = BIT7, /* SGMII board SLM 1364 */
MV_MODULE_DB381_SGMII = BIT8, /* DB-381 SGMII SLM 1426 */
- MV_MODULE_NAND_ON_BOARD = BIT9, /* ON board nand - detected via S@R bootsrc */
- MV_MODULE_DB381_MMC_8BIT_ON_BOARD = BIT10,/* ON board MMC 8bit - detected via S@R bootsrc */
- MV_MODULE_TYPE_MAX_MODULE = 9,
- MV_MODULE_TYPE_MAX_OPTION = 10
+ MV_MODULE_SWITCH = BIT9,/* SWITCH board SLM 1375 */
+ MV_MODULE_NAND_ON_BOARD = BIT10, /* ON board nand - detected via S@R bootsrc */
+ MV_MODULE_DB381_MMC_8BIT_ON_BOARD = BIT11,/* ON board MMC 8bit - detected via S@R bootsrc */
+ MV_MODULE_TYPE_MAX_MODULE = 10,
+ MV_MODULE_TYPE_MAX_OPTION = 11
} MV_MODULE_TYPE_ID;
typedef struct _devCsInfo {
@@ -191,6 +192,18 @@
MV_BOOL active;
} MV_DEV_CS_INFO;
+struct MV_BOARD_SWITCH_INFO {
+ MV_BOOL isEnabled;
+ MV_BOOL isCpuPortRgmii;
+ MV_32 switchIrq;
+ MV_32 switchPort[BOARD_ETH_SWITCH_PORT_NUM];
+ MV_32 cpuPort;
+ MV_32 connectedPort[MV_ETH_MAX_PORTS];
+ MV_32 smiScanMode;
+ MV_32 quadPhyAddr;
+ MV_U32 forceLinkMask; /* Bitmask of switch ports to have force link (1Gbps) */
+};
+
typedef enum _SatRstatus {
SATR_READ_ONLY = 0x01,
SATR_SWAP_BIT = 0x02,
@@ -207,6 +220,18 @@
MV_U8 gppPinNum;
} MV_BOARD_GPP_INFO;
+typedef enum _mvIoExpanderTypeID {
+ MV_IO_EXPANDER_USB_VBUS,
+ MV_IO_EXPANDER_MAX_OPTION
+} MV_IO_EXPANDER_TYPE_ID;
+
+typedef struct _boardIoExapnderTypesInfo {
+ MV_IO_EXPANDER_TYPE_ID ioFieldid;
+ MV_U32 offset;
+ MV_U32 expanderNum;
+ MV_U32 regNum;
+} MV_BOARD_IO_EXPANDER_TYPE_INFO;
+
typedef struct _boardTwsiInfo {
MV_BOARD_TWSI_CLASS devClass;
MV_U8 devClassId;
@@ -324,6 +349,9 @@
MV_BOARD_MAC_INFO *pBoardMacInfo;
MV_U8 numBoardGppInfo;
MV_BOARD_GPP_INFO *pBoardGppInfo;
+ MV_U8 numBoardIoExpPinInfo;
+ MV_BOARD_IO_EXPANDER_TYPE_INFO *pBoardIoExpPinInfo;
+
MV_U8 activeLedsNumber;
MV_U8 *pLedGppPin;
MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
@@ -340,6 +368,7 @@
MV_U32 gppPolarityValLow;
MV_U32 gppPolarityValMid;
MV_U32 gppPolarityValHigh;
+ MV_VOID (*gppPostConfigCallBack) (struct _boardInfo *);
MV_BOARD_USB_INFO *pBoardUsbInfo; /* usb2.0 and usb3.0 physical port mapping on board */
MV_U8 numBoardUsbInfo;
@@ -386,6 +415,12 @@
MV_U32 numIoExp;
struct MV_BOARD_IO_EXPANDER *pIoExp;
MV_U32 boardOptionsModule;
+ MV_BOOL isAmc; /* AMC active: used for DT update & switching services */
+ MV_BOOL isAudioConnected; /* indicates if SPDIF/I2S is connected */
+ MV_BOOL isTdmConnected; /* indicates if TDM module is connected */
+ /* External Switch Configuration */
+ struct MV_BOARD_SWITCH_INFO *pSwitchInfo;
+ MV_U32 switchInfoNum;
} MV_BOARD_INFO;
struct _mvBoardMppModule {
@@ -395,9 +430,8 @@
#define MPP_MII_MODULE { {0, 0x10111111}, {1, 0x11111111}, {2, 0x11211111} }
-#define MPP_TDM_MODULE { {6, 0x45333333}, {7, 0x00004444} }
-#define MPP_I2S_MODULE {6, 0x55544554}
-#define MPP_SPDIF_MODULE {6, 0x55444444}
+#define MPP_TDM_MODULE { {6, 0x55333333}, {7, 0x00004444} }
+#define MPP_AUDIO_MODULE {6, 0x55444444}
#define MPP_NOR_MODULE { {0, 0x55111111}, {1, 0x15555555}, {2, 0x55566011}, \
{3, 0x55555055}, {4, 0x55555555}, {5, 0x40045525 } }
#define MPP_NAND_MODULE { {0, 0x55111111}, {1, 0x15555555}, {2, 0x55266011}, \
@@ -436,6 +470,11 @@
#define MSAR_0_SPI0 0
#define MSAR_0_SPI1 1
+/* definition for switch device scan mode */
+#define MV_SWITCH_SMI_AUTO_SCAN_MODE 0 /* Scan 0 or 0x10 base address to find the QD */
+#define MV_SWITCH_SMI_MANUAL_MODE 1 /* Use QD located at manually defined base addr */
+#define MV_SWITCH_SMI_MULTI_ADDR_MODE 2 /* Use QD at base addr and use indirect access */
+
MV_VOID mvBoardEnvInit(MV_VOID);
MV_U16 mvBoardModelGet(MV_VOID);
MV_U32 mvBoardRevGet(MV_VOID);
@@ -466,8 +505,11 @@
MV_VOID mvBoardReset(MV_VOID);
MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void);
MV_32 mvBoardResetGpioPinGet(MV_VOID);
+#ifdef MV_USB_VBUS_CYCLE
MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId);
-MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId);
+MV_STATUS mvBoardIoExpanderTypeGet(MV_IO_EXPANDER_TYPE_ID ioClass, MV_BOARD_IO_EXPANDER_TYPE_INFO *ioInfo);
+MV_VOID mvBoardUsbVbusSet(int dev);
+#endif
MV_BOOL mvBoardIsOurPciSlot(MV_U32 busNum, MV_U32 slotNum);
MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp);
MV_U32 mvBoardSlicUnitTypeGet(MV_VOID);
@@ -509,7 +551,7 @@
MV_STATUS mvBoardTwsiSet(MV_BOARD_TWSI_CLASS twsiClass, MV_U8 devNum, MV_U8 regNum, MV_U8 *regVal, MV_U32 len);
MV_U8 mvBoardCpuFreqGet(MV_VOID);
MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal);
-MV_STATUS mvBoardIsInternalSwitchConnected(void);
+MV_STATUS mvBoardIsSwitchConnected(void);
MV_U32 mvBoardSwitchPortForceLinkGet(MV_U32 switchIdx);
MV_U32 mvBoardFreqModesNumGet(void);
MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx);
@@ -517,6 +559,10 @@
MV_VOID mvBoardMacSpeedSet(MV_U32 ethPortNum, MV_BOARD_MAC_SPEED speed);
MV_VOID mvBoardMacSpeedSet(MV_U32 ethPortNum, MV_BOARD_MAC_SPEED macSpeed);
MV_U32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx);
+MV_32 mvBoardSwitchPhyAddrGet(MV_U32 switchIdx);
+MV_32 mvBoardSwitchConnectedPortGet(MV_U32 ethPort);
+MV_BOOL mvBoardSwitchCpuPortIsRgmii(MV_U32 switchIdx);
+MV_VOID mvBoardModuleSwitchInfoUpdate(MV_BOOL switchDetected);
MV_U32 mvBoardMacCpuPortGet(MV_VOID);
MV_BOOL mvBoardIsEthConnected(MV_U32 ethNum);
MV_BOOL mvBoardIsEthActive(MV_U32 ethNum);
@@ -569,11 +615,20 @@
MV_STATUS mvBoardSysConfigSet(MV_CONFIG_TYPE_ID configField, MV_U8 value);
void mvBoardEepromValidSet(void);
#endif /* CONFIG_CMD_BOARDCFG */
+MV_BOOL mvBoardIsTdmConnected(void);
+void mvBoardTdmConnectionSet(MV_BOOL isConnected);
MV_NAND_IF_MODE mvBoardNandIfGet(void);
MV_BOOL mvBoardisSdioConnected(void);
MV_VOID mvBoardSdioConnectionSet(MV_BOOL status);
MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber);
MV_BOARD_INFO *mvBoardInfoStructureGet(MV_VOID);
+MV_BOOL mvBoardIsAudioConnected(void);
+void mvBoardAudioConnectionSet(MV_BOOL isConnected);
+MV_BOOL mvBoardIsUsb3PortDevice(MV_U32 port);
+
+#ifdef CONFIG_SWITCHING_SERVICES
+MV_BOOL mvBoardisAmc(void);
+#endif
#ifdef __cplusplus
}
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.c
index fb27751..4c2ed94 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.c
@@ -99,6 +99,56 @@
return MV_PORT_TYPE_UNKNOWN;
}
+#ifdef CONFIG_SWITCHING_SERVICES
+/*******************************************************************************
+* mvBoardisAmc
+* DESCRIPTION: return true if board is AMC
+*
+* INPUT: None
+* OUTPUT: None.
+* RETURN: MV_TRUE: if board is AMC
+* MV_FALSE: else
+*******************************************************************************/
+MV_BOOL mvBoardisAmc(void)
+{
+ MV_BOARD_INFO *board = mvBoardInfoStructureGet();
+ if (board)
+ return board->isAmc;
+
+ DB(mvOsPrintf("%s: Error: board structure not initialized\n", __func__));
+ return MV_FALSE;
+}
+#endif
+
+/*******************************************************************************
+* mvBoardIsUsb3PortDevice
+* DESCRIPTION: return true USB3 port is in device mode
+*
+* INPUT: port - port number
+* OUTPUT: None.
+* RETURN: MV_TRUE: if port is set to device mode
+* MV_FALSE: otherwise
+*******************************************************************************/
+MV_BOOL mvBoardIsUsb3PortDevice(MV_U32 port)
+{
+ MV_U32 boardId, satrReadResult;
+
+ if (port < 0 || port >= MV_USB3_MAX_HOST_PORTS)
+ return MV_FALSE;
+
+ boardId = mvBoardIdGet();
+ /* since 'usb3port0' and 'usb3port1' are only supported on
+ * DB-BP and DB-6821-BP, return MV_FALSE if we are not on these boards */
+ if (!(boardId == DB_68XX_ID || boardId == DB_BP_6821_ID))
+ return MV_FALSE;
+
+ satrReadResult = mvBoardSatRRead((MV_U32)MV_SATR_DB_USB3_PORT0 + port);
+ if (satrReadResult != MV_ERROR && satrReadResult)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+
/*******************************************************************************
* mvBoardIsPortInSgmii -
*
@@ -328,8 +378,6 @@
if ((mvBoardIsModuleConnected(MV_MODULE_DB381_MMC_8BIT_ON_BOARD)))
mvBoardSdioConnectionSet(MV_TRUE);
- else
- mvBoardSdioConnectionSet(MV_FALSE);
mvBoardIoExpanderUpdate();
mvBoardPcieModulesInfoUpdate(); /* if PCIe modules are configured (via 'SatR') */
@@ -353,6 +401,25 @@
if ((mvBoardIsModuleConnected(MV_MODULE_MII))) /* MII Module uses different PHY address */
mvBoardPhyAddrSet(0, 8); /*set SMI address 8 for port 0*/
+ if (mvBoardIsModuleConnected(MV_MODULE_SPDIF_DEVICE) ||
+ mvBoardIsModuleConnected(MV_MODULE_I2S_DEVICE)) {
+ /* TDM, Audio and Sdio have mpp's conflict
+ * --> disable Sdio and TDM when SPDIF is connected */
+ mvBoardAudioConnectionSet(MV_TRUE);
+ mvBoardSdioConnectionSet(MV_FALSE);
+ mvBoardTdmConnectionSet(MV_FALSE);
+ } else if (mvBoardSatRRead(MV_SATR_TDM_CONNECTED) == 0) {
+ /* if Audio modules detected, skip reading TDM from SatR */
+
+ /* TDM, Audio and Sdio have mpp's conflict
+ * --> disable Audio and Sdio when TDM is connected */
+ mvBoardTdmConnectionSet(MV_TRUE);
+ mvBoardAudioConnectionSet(MV_FALSE);
+ mvBoardSdioConnectionSet(MV_FALSE);
+ /* update DT: used for Linux only */
+ mvBoardSetDevState(1, BOARD_DEV_SPI_FLASH, MV_TRUE);
+ }
+
/* Update MPP group types and values according to board configuration */
mvBoardMppIdUpdate();
/* board on test mode */
@@ -366,6 +433,8 @@
mvBoardPcieModulesInfoUpdate(); /* if PCIe modules are configured (via 'SatR') */
mvBoardFlashDeviceUpdate();
+ mvBoardModuleSwitchInfoUpdate(mvBoardIsModuleConnected(MV_MODULE_SWITCH));
+ mvBoardIoExpanderUpdate();
break;
case DB_AMC_6820_ID:
/* nothing to be updated at run-time for AMC board */
@@ -425,12 +494,13 @@
"SDIO 4bit", \
"SGMII", \
"DB-381 SLM-1426 (SGMII-2)", \
+ "SWITCH", \
};
mvOsOutput("Board configuration detected:\n");
for (i = 0; i < MV_MODULE_TYPE_MAX_MODULE; i++) {
if (mvBoardIsModuleConnected(1 << i))
mvOsOutput(" %s module.\n", moduleStr[i]);
-
}
}
+
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.h
index f22067b..ab8b420 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib38x.h
@@ -79,6 +79,7 @@
MV_BOARD_MAC_SPEED boardMacSpeed;
MV_32 boardEthSmiAddr;
MV_32 boardEthSmiAddr0;
+ MV_BOOL boardMacEnabled;
} MV_BOARD_MAC_INFO;
enum {
@@ -99,6 +100,7 @@
{ MV_MODULE_SDIO, 0x4, 0, 0x2, { 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_SGMII, 0x2, 0, 0xF, { 0, 1, 0, 0, 0, 0, 0} }, \
{ MV_MODULE_DB381_SGMII, 0x0, 0, 0x2, { 0, 0, 0, 0, 0, 1, 0} }, \
+{ MV_MODULE_SWITCH, 0x5, 0, 0xE, { 0, 1, 0, 0, 0, 0, 0} }, \
};
typedef enum _mvSatRTypeID {
@@ -128,6 +130,11 @@
MV_SATR_DEVICE_ID2,
MV_SATR_GP_SERDES1_CFG,
MV_SATR_GP_SERDES2_CFG,
+ MV_SATR_FULL_FLAVOR,
+ MV_SATR_TDM_CONNECTED,
+ MV_SATR_TDM_PLACE_HOLDER,
+ MV_SATR_BOARD_SPEED,
+ MV_SATR_AVS_SKIP,
MV_SATR_MAX_OPTION,
} MV_SATR_TYPE_ID;
@@ -142,7 +149,7 @@
{"ddrbuswidth", MV_SATR_DDR_BUS_WIDTH, 0x08, 3, 0, 0, {1, 1, 1, 1, 1, 0, 1}, 0},\
{"ddreccenable", MV_SATR_DDR_ECC_ENABLE, 0x10, 4, 0, 0, {1, 1, 1, 1, 1, 1, 1}, 0},\
{"ddreccpupselect", MV_SATR_DDR_ECC_PUP_SEL, 0x20, 5, 0, 0, {0, 1, 0, 0, 0, 0, 1}, 0},\
-{"sgmiispeed", MV_SATR_SGMII_SPEED, 0x40, 6, 0, 0, {1, 1, 1, 1, 1, 1, 1}, 0},\
+{"sgmiispeed", MV_SATR_SGMII_SPEED, 0x40, 6, 0, 0, {1, 1, 1, 1, 1, 1, 0}, 0},\
{"bootsrc", MV_SATR_BOOT_DEVICE, 0x3, 0, 3, 0, {0, 1, 0, 0, 0, 1, 0}, SATR_SWAP_BIT},\
{"boarsrc2", MV_SATR_BOOT2_DEVICE, 0x1E, 1, 2, 0, {0, 1, 0, 0, 0, 1, 0}, SATR_SWAP_BIT},\
{"boardid", MV_SATR_BOARD_ID, 0x7, 0, 0, 0, {1, 1, 1, 1, 1, 1, 1}, 0},\
@@ -158,8 +165,16 @@
{"sgmiimode", MV_SATR_SGMII_MODE, 0x40, 6, 0, 1, {0, 1, 0, 0, 1, 1, 1}, 0},\
{"devid", MV_SATR_DEVICE_ID, 0x1, 0, 2, 0, {0, 1, 0, 0, 0, 0, 0}, 0},\
{"devid2", MV_SATR_DEVICE_ID2, 0x10, 4, 3, 0, {0, 1, 0, 0, 0, 0, 0}, 0},\
+{"flavor", MV_SATR_FULL_FLAVOR, 0x10, 4, 0, 2, {0, 1, 0, 1, 1, 1, 0}, 0},\
+{"tdm", MV_SATR_TDM_CONNECTED, 0x20, 5, 0, 2, {0, 1, 0, 0, 0, 0, 0}, 0},\
+{"tdmplaceholder", MV_SATR_TDM_PLACE_HOLDER, 0x40, 6, 0, 2, {0, 0, 0, 0, 0, 0, 0}, 0},\
+{"avsskip", MV_SATR_AVS_SKIP, 0x80, 7, 0, 2, {0, 1, 0, 1, 1, 1, 1}, 0},\
+{"boardspeed", MV_SATR_BOARD_SPEED, 0x3, 0, 0, 3, {0, 1, 0, 1, 1, 0, 1}, SATR_READ_ONLY},\
{"max_option", MV_SATR_MAX_OPTION, 0x0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0}, 0},\
};
+/* tdm place holder is used for future support for multiple tdm devices */
+/* avsskip is used to skip selecting AVS from EFUSE:
+ * - used in binary header by Marvell boards only*/
/* extra SAR table, for different board implementations:
* in case a field is used on 2 boards with different i2c mapping */
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.c
index 1928edf..7de1ac1 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.c
@@ -625,3 +625,18 @@
mvOsOutput("| In-Band |\n");
}
}
+
+/*******************************************************************************
+* mvBoardIsUsb3PortDevice
+* DESCRIPTION: return true USB3 port is in device mode
+*
+* INPUT: port - port number
+* OUTPUT: None.
+* RETURN: MV_TRUE: if port is set to device mode
+* MV_FALSE: otherwise
+*******************************************************************************/
+MV_BOOL mvBoardIsUsb3PortDevice(MV_U32 port)
+{
+ /* Since usb3 device is not supported on current board return false */
+ return MV_FALSE;
+}
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.h
index 12d43ef..a5a2b90 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib39x.h
@@ -88,6 +88,7 @@
MV_32 boardEthSmiAddr;
MV_32 boardEthSmiAddr0;
MV_PHY_NEGOTIATION_PORT_TYPE negType;
+ MV_BOOL boardMacEnabled;
} MV_BOARD_MAC_INFO;
typedef enum {
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
index 45de9b4..a6920a5 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
@@ -83,8 +83,9 @@
#define A38X_CUTOMER_BOARD_ID_BASE 0x0
#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUTOMER_BOARD_ID_BASE + 0)
#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUTOMER_BOARD_ID_BASE + 1)
-#define A38X_GFCH100_ID (A38X_CUTOMER_BOARD_ID_BASE + 2)
-#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUTOMER_BOARD_ID_BASE + 3)
+#define A38X_CLEARFOG_BOARD_ID (A38X_CUTOMER_BOARD_ID_BASE + 2)
+#define A38X_GFCH100_ID (A38X_CUTOMER_BOARD_ID_BASE + 3)
+#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUTOMER_BOARD_ID_BASE + 4)
#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - A38X_CUTOMER_BOARD_ID_BASE)
/* Armada-38x Marvell boards */
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
index fc534f7..a5e1e4d 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
@@ -66,6 +66,7 @@
#include "boardEnv/mvBoardEnvSpec.h"
#include "twsi/mvTwsi.h"
#include "pex/mvPexRegs.h"
+#include "gpp/mvGppRegs.h"
/***************************************** Customer Boards *****************************************/
/*******************************************************************************
@@ -81,15 +82,17 @@
MV_BOARD_TWSI_INFO armada_38x_customer_0_BoardTwsiDev[] = {
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 devClassId, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
- { BOARD_DEV_TWSI_SATR, 0, 0x57, ADDR7_BIT, MV_TRUE}, /* read only for HW configuration */
- { BOARD_DEV_TWSI_SATR, 1, 0x4C, ADDR7_BIT, MV_FALSE},
- { BOARD_TWSI_IO_EXPANDER, 0, 0x20, ADDR7_BIT, MV_FALSE},
- { BOARD_TWSI_IO_EXPANDER, 1, 0x21, ADDR7_BIT, MV_FALSE},
+ { BOARD_DEV_TWSI_SATR, 0, 0x57, ADDR7_BIT, MV_TRUE}, /* read only for HW configuration */
+ { BOARD_DEV_TWSI_SATR, 1, 0x4C, ADDR7_BIT, MV_FALSE},
+ { BOARD_TWSI_IO_EXPANDER, 0, 0x21, ADDR7_BIT, MV_FALSE},
};
+
MV_BOARD_MAC_INFO armada_38x_customer_0_BoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_FALSE},
};
MV_DEV_CS_INFO armada_38x_customer_0_BoardDeCsInfo[] = {
@@ -123,16 +126,32 @@
};
struct MV_BOARD_IO_EXPANDER armada_38x_customer_0_IoExpanderInfo[] = {
- {0, 6, 0xF4}, /* Configuration registers: Bit on --> Input bits */
- {0, 7, 0xC3}, /* Configuration registers: Bit on --> Input bits */
- {0, 2, 0x0B}, /* Output Data, register#0 */
- {0, 3, 0x18}, /* Output Data, register#1 */
- {1, 6, 0xE7}, /* Configuration registers: Bit on --> Input bits */
- {1, 7, 0xF9}, /* Configuration registers: Bit on --> Input bits */
- {1, 2, 0x08}, /* Output Data, register#0 */
- {1, 3, 0x00} /* Output Data, register#1 */
+ {0, 6, 0xFF}, /* Config reg#0: all bits as input (BIT on = Input) */
+ {0, 7, 0xFC}, /* Config reg#1: BIT0(USB3.0 current limit), BIT1(USB3.1 current limit)*/
+ {0, 2, 0xFF}, /* Output Data, reg#0 - no output bits*/
+ {0, 3, 0xFF}, /* Output Data, reg#1: BIT0,USB3.0_CURRENT=1, BIT1,USB3.1_CURRENT=1 */
};
+MV_BOARD_GPP_INFO armada_38x_customer_0_GppInfo[] = {
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+/* USB_Host0 */ /* {BOARD_GPP_USB_VBUS, 44}, */ /* from MPP map */
+};
+
+MV_BOARD_USB_INFO armada_38x_customer_0_InfoBoardUsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOLEAN isActive} */
+ { USB3_UNIT_ID, 0, MV_TRUE},
+ { USB3_UNIT_ID, 1, MV_TRUE},
+ { USB_UNIT_ID, 0, MV_TRUE},
+};
+
+/* gpp_callback is a generic place holder routine for special GPIO pull-up/sown sequence
+ * this routine is called as the final step of mvBoardEnvInit flow
+ * for example see implementation for SolidRun's clearFog board: A38x_CLEARFOG_BOARD_gpp_callback*/
+void A38x_CUSTOMER_BOARD_0_gpp_callback(MV_BOARD_INFO *board) {
+
+ /* implement special GPIO/MPP post configuration here */
+}
+
MV_BOARD_INFO armada_38x_customer_board_0_info = {
.boardName = "A38x-Customer-Board-0",
.numBoardNetComplexValue = 0,
@@ -147,8 +166,10 @@
.pBoardTwsiDev = armada_38x_customer_0_BoardTwsiDev,
.numBoardMacInfo = ARRSZ(armada_38x_customer_0_BoardMacInfo),
.pBoardMacInfo = armada_38x_customer_0_BoardMacInfo,
- .numBoardGppInfo = 0,
- .pBoardGppInfo = 0,
+ .numBoardGppInfo = ARRSZ(armada_38x_customer_0_GppInfo),
+ .pBoardGppInfo = armada_38x_customer_0_GppInfo,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -164,12 +185,16 @@
.gppOutValMid = A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID,
.gppPolarityValLow = A38x_CUSTOMER_BOARD_0_GPP_POL_LOW,
.gppPolarityValMid = A38x_CUSTOMER_BOARD_0_GPP_POL_MID,
+ .gppPostConfigCallBack = A38x_CUSTOMER_BOARD_0_gpp_callback,
/* TDM */
.numBoardTdmInfo = {},
.pBoardTdmInt2CsInfo = {},
.boardTdmInfoIndex = -1,
+ .pBoardUsbInfo = armada_38x_customer_0_InfoBoardUsbInfo,
+ .numBoardUsbInfo = ARRSZ(armada_38x_customer_0_InfoBoardUsbInfo),
+
.pBoardSpecInit = NULL,
/* NAND init params */
@@ -187,7 +212,10 @@
.configAutoDetect = MV_FALSE,
.numIoExp = ARRSZ(armada_38x_customer_0_IoExpanderInfo),
.pIoExp = armada_38x_customer_0_IoExpanderInfo,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
@@ -202,10 +230,11 @@
{ BOARD_TWSI_IO_EXPANDER, 1, 0x21, ADDR7_BIT, MV_FALSE},
};
MV_BOARD_MAC_INFO armada_38x_customer_1_BoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, -1, -1}
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE}
};
MV_DEV_CS_INFO armada_38x_customer_1_BoardDeCsInfo[] = {
@@ -249,6 +278,24 @@
{1, 3, 0xC0} /* Output Data, register#1 */
};
+
+MV_BOARD_GPP_INFO armada_38x_customer_1_GppInfo[] = {
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+/* USB_Host0 *//* //{BOARD_GPP_USB_VBUS, 44},*/ /* from MPP map */
+};
+
+MV_BOARD_USB_INFO armada_38x_customer_1_InfoBoardUsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+ { USB3_UNIT_ID, 0, MV_TRUE},
+ { USB3_UNIT_ID, 1, MV_TRUE}, /* xHCI port#1 connected only via USB2.0 UTMI (not via USB3.0 SerDes lane) */
+ { USB_UNIT_ID, 0, MV_TRUE},
+};
+
+MV_BOARD_IO_EXPANDER_TYPE_INFO armada_38x_customer_1_ioExpPinInfo[] = {
+/* { IO Type enum, bit offset, Io.exp num, reg Num */
+ { MV_IO_EXPANDER_USB_VBUS, 7, 1, 3} /* VBUS_EN: IO.exp#1 (0x21), reg #3, bit 7 */
+};
+
MV_BOARD_INFO armada_38x_customer_board_1_info = {
.boardName = "A38x-Customer-Board-1",
.numBoardNetComplexValue = 0,
@@ -263,8 +310,10 @@
.pBoardTwsiDev = armada_38x_customer_1_BoardTwsiDev,
.numBoardMacInfo = ARRSZ(armada_38x_customer_1_BoardMacInfo),
.pBoardMacInfo = armada_38x_customer_1_BoardMacInfo,
- .numBoardGppInfo = 0,
- .pBoardGppInfo = 0,
+ .numBoardGppInfo = ARRSZ(armada_38x_customer_1_GppInfo),
+ .pBoardGppInfo = armada_38x_customer_1_GppInfo,
+ .numBoardIoExpPinInfo = ARRSZ(armada_38x_customer_1_ioExpPinInfo),
+ .pBoardIoExpPinInfo = armada_38x_customer_1_ioExpPinInfo,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -288,6 +337,9 @@
.pBoardSpecInit = NULL,
+ .pBoardUsbInfo = armada_38x_customer_1_InfoBoardUsbInfo,
+ .numBoardUsbInfo = ARRSZ(armada_38x_customer_1_InfoBoardUsbInfo),
+
/* NAND init params */
.nandFlashReadParams = A38x_CUSTOMER_BOARD_0_NAND_READ_PARAMS,
.nandFlashWriteParams = A38x_CUSTOMER_BOARD_0_NAND_WRITE_PARAMS,
@@ -303,7 +355,172 @@
.configAutoDetect = MV_FALSE,
.numIoExp = ARRSZ(armada_38x_customer_1_IoExpanderInfo),
.pIoExp = armada_38x_customer_1_IoExpanderInfo,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
+};
+
+/*******************************************************************************
+ * A38x SolidRun ClearFog
+ *******************************************************************************/
+MV_BOARD_TWSI_INFO armada_38x_clearfog_BoardTwsiDev[] = {
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 devClassId, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ { BOARD_TWSI_IO_EXPANDER, 0, 0x20, ADDR7_BIT, MV_FALSE},
+};
+MV_BOARD_MAC_INFO armada_38x_clearfog_BoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_1000M, -1, -1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE}
+};
+
+MV_DEV_CS_INFO armada_38x_clearfog_BoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+ { DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
+ { DEVICE_CS1, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
+ { DEVICE_CS2, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
+ { DEVICE_CS3, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
+ { DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE }, /* NOR DEV */
+ { SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
+ { SPI0_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
+ { SPI0_CS2, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
+ { SPI0_CS3, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
+ { SPI1_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_TRUE }, /* SPI1 DEV */
+ { SPI1_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_FALSE }, /* SPI1 DEV */
+ { SPI1_CS2, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_FALSE }, /* SPI1 DEV */
+ { SPI1_CS3, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_FALSE } /* SPI1 DEV */
+};
+
+MV_BOARD_MPP_INFO armada_38x_clearfog_BoardMppConfigValue[] = {
+ { {
+ A38x_CLEARFOG_BOARD_MPP0_7,
+ A38x_CLEARFOG_BOARD_MPP8_15,
+ A38x_CLEARFOG_BOARD_MPP16_23,
+ A38x_CLEARFOG_BOARD_MPP24_31,
+ A38x_CLEARFOG_BOARD_MPP32_39,
+ A38x_CLEARFOG_BOARD_MPP40_47,
+ A38x_CLEARFOG_BOARD_MPP48_55,
+ A38x_CLEARFOG_BOARD_MPP56_63,
+ } }
+};
+
+struct MV_BOARD_IO_EXPANDER armada_38x_clearfog_IoExpanderInfo[] = {
+ {0, 2, 0x40}, /* Deassert both mini pcie reset signals */
+ {0, 6, 0xf9},
+ {0, 2, 0x46}, /* Assert reset signals and enable USB3 current limiter */
+ {0, 6, 0xb9},
+ {0, 3, 0x0}, /* Set SFP_TX_DIS to zero */
+ {0, 7, 0xbf}, /* Drive SFP_TX_DIS to zero */
+};
+
+MV_BOARD_USB_INFO armada_38x_clearfog_InfoBoardUsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+ { USB3_UNIT_ID, 0, MV_TRUE},
+ { USB3_UNIT_ID, 1, MV_TRUE}, /* xHCI port#1 connected only via USB2.0 UTMI (not via USB3.0 SerDes lane) */
+ { USB_UNIT_ID, 0, MV_TRUE},
+};
+
+struct MV_BOARD_SWITCH_INFO armada_38x_clearfog_InfoSwitchInfo[] = {
+ {
+ .isEnabled = MV_TRUE,
+ .isCpuPortRgmii = MV_FALSE,
+ .switchIrq = -1, /* set to -1 for using PPU*/
+ .switchPort = {0, 1, 2, 3, 4, 5, 6},
+ .cpuPort = 5,
+ .connectedPort = {-1, 5, -1},
+ .smiScanMode = MV_SWITCH_SMI_MULTI_ADDR_MODE,
+ .quadPhyAddr = 4,
+ .forceLinkMask = 0x60
+ }
+};
+
+MV_BOARD_IO_EXPANDER_TYPE_INFO armada_38x_clearfog_ioExpPinInfo[] = {
+/* { IO Type enum, bit offset, Io.exp num, reg Num */
+ { MV_IO_EXPANDER_USB_VBUS, 6, 0, 2} /* VBUS_EN: IO.exp#1 (0x21), reg #3, bit 7 */
+};
+
+void A38x_CLEARFOG_BOARD_gpp_callback(MV_BOARD_INFO *board) {
+ /* Toggle GPIO41 to reset on-board switch and phy */
+ /* Set GPIO41 as output enabled */
+ MV_REG_BIT_RESET (GPP_DATA_OUT_REG(1), BIT9);
+ /* reset output value */
+ MV_REG_BIT_RESET (GPP_DATA_OUT_EN_REG(1), BIT9);
+ /* set output value */
+ mvOsDelay(1);
+ MV_REG_BIT_SET (GPP_DATA_OUT_EN_REG(1), BIT9);
+ mvOsDelay(10);
+
+ /* update on-Board IO expander with pre-defined values:
+ * USB3 current limiter, and SFP_TX_DIS, Deassert and assert 2*mini PCIe reset signals, */
+ mvBoardIoExpanderUpdate();
+}
+
+MV_BOARD_INFO armada_38x_clearfog_board_info = {
+ .boardName = "SolidRun ClearFog-A1 REV2.0",
+ .numBoardNetComplexValue = 0,
+ .pBoardNetComplexInfo = NULL,
+ .pBoardMppConfigValue = armada_38x_clearfog_BoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(armada_38x_clearfog_BoardDeCsInfo),
+ .pDevCsInfo = armada_38x_clearfog_BoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(armada_38x_clearfog_BoardTwsiDev),
+ .pBoardTwsiDev = armada_38x_clearfog_BoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(armada_38x_clearfog_BoardMacInfo),
+ .pBoardMacInfo = armada_38x_clearfog_BoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = ARRSZ(armada_38x_clearfog_ioExpPinInfo),
+ .pBoardIoExpPinInfo = armada_38x_clearfog_ioExpPinInfo,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* PMU Power */
+ .pmuPwrUpPolarity = 0,
+ .pmuPwrUpDelay = 80000,
+
+ /* GPP values */
+ .gppOutEnValLow = A38x_CLEARFOG_BOARD_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = A38x_CLEARFOG_BOARD_GPP_OUT_ENA_MID,
+ .gppOutValLow = A38x_CLEARFOG_BOARD_GPP_OUT_VAL_LOW,
+ .gppOutValMid = A38x_CLEARFOG_BOARD_GPP_OUT_VAL_MID,
+ .gppPolarityValLow = A38x_CLEARFOG_BOARD_GPP_POL_LOW,
+ .gppPolarityValMid = A38x_CLEARFOG_BOARD_GPP_POL_MID,
+ .gppPostConfigCallBack = A38x_CLEARFOG_BOARD_gpp_callback,
+
+ /* TDM */
+ .numBoardTdmInfo = {},
+ .pBoardTdmInt2CsInfo = {},
+ .boardTdmInfoIndex = -1,
+
+ .pBoardSpecInit = NULL,
+
+ .pBoardUsbInfo = armada_38x_clearfog_InfoBoardUsbInfo,
+ .numBoardUsbInfo = ARRSZ(armada_38x_clearfog_InfoBoardUsbInfo),
+
+ /* NAND init params */
+ .nandFlashReadParams = 0,
+ .nandFlashWriteParams = 0,
+ .nandFlashControl = 0,
+ .nandIfMode = NAND_IF_NFC,
+
+ .isSdMmcConnected = MV_TRUE,
+
+ /* NOR init params */
+ .norFlashReadParams = 0,
+ .norFlashWriteParams = 0,
+ /* Enable modules auto-detection. */
+ .configAutoDetect = MV_FALSE,
+ .numIoExp = ARRSZ(armada_38x_clearfog_IoExpanderInfo),
+ .pIoExp = armada_38x_clearfog_IoExpanderInfo,
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .pSwitchInfo = armada_38x_clearfog_InfoSwitchInfo,
+ .switchInfoNum = ARRSZ(armada_38x_clearfog_InfoSwitchInfo)
};
/*******************************************************************************
@@ -318,9 +535,10 @@
#define A38x_GFCH100_NOR_WRITE_PARAMS 0x000F0F0F
MV_BOARD_MAC_INFO armada_38x_gfch100_BoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_1000M, 0xff, 0x0}, /* switch, no phy, no addr */
- { BOARD_MAC_SPEED_AUTO, 0x3, 0x0}, /* craft, phy port 3, no addr */
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_1000M, -1, -1, MV_TRUE}, /* switch, no phy, no addr */
+ { BOARD_MAC_SPEED_AUTO, 0x3, 0x0, MV_TRUE}, /* craft, phy port 3, no addr */
};
MV_DEV_CS_INFO armada_38x_gfch100_BoardDeCsInfo[] = {
@@ -397,6 +615,10 @@
.pBoardSpecInit = NULL,
+ /* USB */
+ .numBoardUsbInfo = ARRSZ(armada_38x_gfch100_UsbInfo),
+ .pBoardUsbInfo = armada_38x_gfch100_UsbInfo,
+
/* NAND init params */
.nandFlashReadParams = A38x_GFCH100_NAND_READ_PARAMS,
.nandFlashWriteParams = A38x_GFCH100_NAND_WRITE_PARAMS,
@@ -413,10 +635,6 @@
.numIoExp = ARRSZ(armada_38x_gfch100_IoExpanderInfo),
.pIoExp = armada_38x_gfch100_IoExpanderInfo,
.boardOptionsModule = MV_MODULE_NO_MODULE,
-
- /* USB */
- .numBoardUsbInfo = ARRSZ(armada_38x_gfch100_UsbInfo),
- .pBoardUsbInfo = armada_38x_gfch100_UsbInfo,
};
/*
@@ -425,6 +643,7 @@
MV_BOARD_INFO *customerBoardInfoTbl[] = {
&armada_38x_customer_board_0_info,
&armada_38x_customer_board_1_info,
+ &armada_38x_clearfog_board_info,
&armada_38x_gfch100_info,
};
@@ -460,7 +679,7 @@
{ BOARD_DEV_TWSI_SATR, 1, 0x4c, ADDR7_BIT, MV_FALSE},
{ BOARD_DEV_TWSI_SATR, 2, 0x4d, ADDR7_BIT, MV_FALSE},
{ BOARD_DEV_TWSI_SATR, 3, 0x4e, ADDR7_BIT, MV_FALSE},
- { BOARD_DEV_TWSI_SATR, 4, 0x21, ADDR7_BIT, MV_FALSE},
+ { BOARD_TWSI_IO_EXPANDER, 0, 0x21, ADDR7_BIT, MV_FALSE},
{ BOARD_TWSI_MODULE_DETECT, 0, 0x20, ADDR7_BIT, MV_FALSE}, /* modules */
{ BOARD_TWSI_MODULE_DETECT, 1, 0x23, ADDR7_BIT, MV_FALSE},
{ BOARD_TWSI_MODULE_DETECT, 2, 0x24, ADDR7_BIT, MV_FALSE},
@@ -469,10 +688,11 @@
{ BOARD_TWSI_MODULE_DETECT, 5, 0x27, ADDR7_BIT, MV_FALSE},
};
MV_BOARD_MAC_INFO db88f68xxInfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0, MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
MV_BOARD_USB_INFO db88f68xxInfoBoardUsbInfo[] = {
@@ -487,13 +707,34 @@
{ DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
{ DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE }, /* NOR DEV */
{ SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE }, /* SPI0 DEV */
- { SPI0_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE } /* SPI0 DEV */
+ { SPI1_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_FALSE } /* SPI1 DEV */
};
MV_BOARD_TDM_INFO db88f68xxTdm880[] = { {0} };
MV_BOARD_TDM_SPI_INFO db88f68xxTdmSpiInfo[] = { {1} };
+struct MV_BOARD_SWITCH_INFO db88f68xxSwitchInfo[] = {
+ {
+ .isEnabled = MV_FALSE,
+ .isCpuPortRgmii = MV_TRUE,
+ .switchIrq = -1, /* set to -1 for using PPU*/
+ .switchPort = {0, 1, 2, 3, 4, 5, 6},
+ .cpuPort = 6,
+ .connectedPort = {5, 6, -1},
+ .smiScanMode = MV_SWITCH_SMI_MULTI_ADDR_MODE,
+ .quadPhyAddr = 2,
+ .forceLinkMask = 0x60
+ }
+};
+
+struct MV_BOARD_IO_EXPANDER db88f68xxInfoBoardioExpValue[] = {
+ {0, 6, 0xFF}, /* Config reg#0: all bits as input (BIT on = Input) */
+ {0, 7, 0xFC}, /* Config reg#1: BIT0(USB3.0 current limit), BIT1(USB3.1 current limit)*/
+ {0, 2, 0xFF}, /* Output Data, reg#0 - no output bits*/
+ {0, 3, 0xFF}, /* Output Data, reg#1: BIT0,USB3.0_CURRENT=1, BIT1,USB3.1_CURRENT=1 */
+};
+
MV_BOARD_INFO db88f68xx_board_info = {
.boardName = "DB-88F6820-BP",
.compatibleDTName = "a385-db",
@@ -511,6 +752,8 @@
.pBoardMacInfo = db88f68xxInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -557,9 +800,14 @@
/* Enable modules auto-detection. */
.configAutoDetect = MV_TRUE,
- .numIoExp = 0,
- .pIoExp = NULL,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .numIoExp = ARRSZ(db88f68xxInfoBoardioExpValue),
+ .pIoExp = db88f68xxInfoBoardioExpValue,
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = db88f68xxSwitchInfo,
+ .switchInfoNum = ARRSZ(db88f68xxSwitchInfo)
};
/*******************************************************************************
@@ -573,9 +821,10 @@
{ BOARD_TWSI_IO_EXPANDER, 1, 0x21, ADDR7_BIT, MV_FALSE},
};
MV_BOARD_MAC_INFO rd88F68XXInfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0}
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0, MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE}
};
MV_DEV_CS_INFO rd88F68XXInfoBoardDeCsInfo[] = {
@@ -623,6 +872,8 @@
.pBoardMacInfo = rd88F68XXInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -662,7 +913,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = ARRSZ(ioExpNas),
.pIoExp = ioExpNas,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
* A380 RD-WAP-88F68XX board */
@@ -706,6 +962,8 @@
.pBoardMacInfo = rd88F68XXInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -745,7 +1003,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = ARRSZ(ioExpWap),
.pIoExp = ioExpWap,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
@@ -785,10 +1048,11 @@
};
MV_BOARD_MAC_INFO dbAP88f68xxInfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x6, 0x4},
- { BOARD_MAC_SPEED_AUTO, 0x4, 0x4},
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x6, 0x4, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x4, 0x4, MV_TRUE},
};
MV_BOARD_USB_INFO dbAP88f68xxInfoBoardUsbInfo[] = {
@@ -800,9 +1064,12 @@
MV_DEV_CS_INFO dbAP88f68xxInfoBoardDeCsInfo[] = {
/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
{ DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE }, /* NAND DEV */
- { DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE }, /* NOR DEV */
- { SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
- { SPI0_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE } /* SPI0 DEV */
+ { DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE } /* NOR DEV */
+};
+
+MV_BOARD_GPP_INFO dbAP88f68xxInfoBoardGppInfo[] = {
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+/* USB_Host0 */ {BOARD_GPP_USB_VBUS, 44}, /* from MPP map */
};
MV_BOARD_TDM_INFO dbAP88f68xxTdm880[] = { {0} };
@@ -826,8 +1093,10 @@
.pBoardTwsiDev = dbAP88f68xxInfoBoardTwsiDev,
.numBoardMacInfo = ARRSZ(dbAP88f68xxInfoBoardMacInfo),
.pBoardMacInfo = dbAP88f68xxInfoBoardMacInfo,
- .numBoardGppInfo = 0,
- .pBoardGppInfo = 0,
+ .numBoardGppInfo = ARRSZ(dbAP88f68xxInfoBoardGppInfo),
+ .pBoardGppInfo = dbAP88f68xxInfoBoardGppInfo,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0, /* PMU Power */
@@ -863,7 +1132,12 @@
.configAutoDetect = MV_FALSE,
.numIoExp = 0,
.pIoExp = NULL,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
@@ -878,10 +1152,11 @@
{ BOARD_TWSI_IO_EXPANDER, 1, 0x21, ADDR7_BIT, MV_FALSE},
};
MV_BOARD_MAC_INFO dbGP88F68XXInfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, -1, -1}
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE}
};
MV_BOARD_USB_INFO dbGP88f68xxInfoBoardUsbInfo[] = {
@@ -917,7 +1192,12 @@
{1, 6, 0xC3}, /* Configuration registers: Bit on --> Input bits */
{1, 7, 0x31}, /* Configuration registers: Bit on --> Input bits */
{1, 2, 0x08}, /* Output Data, register#0 */
- {1, 3, 0xC0} /* Output Data, register#1 */
+ {1, 3, 0x40} /* Output Data, register#1 */
+};
+
+MV_BOARD_IO_EXPANDER_TYPE_INFO dbGP88f68XXInfoBoardioExpPinInfo[] = {
+/* { IO Type enum, bit offset, Io.exp num, reg Num */
+ { MV_IO_EXPANDER_USB_VBUS, 7, 1, 3} /* VBUS_EN: IO.exp#1 (0x21), reg #3, bit 7 */
};
MV_U8 dbGP88f68XXInfoBoardPicGpio[] = {33, 34, 35};
@@ -939,6 +1219,8 @@
.pBoardMacInfo = dbGP88F68XXInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = ARRSZ(dbGP88f68XXInfoBoardioExpPinInfo),
+ .pBoardIoExpPinInfo = dbGP88f68XXInfoBoardioExpPinInfo,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -984,7 +1266,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = ARRSZ(dbGP88f68XXInfoBoardioExpValue),
.pIoExp = dbGP88f68XXInfoBoardioExpValue,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
@@ -1011,10 +1298,11 @@
{ BOARD_TWSI_MODULE_DETECT, 0, 0x56, ADDR7_BIT, MV_TRUE}, /* SLM 1426/1427 module */
};
MV_BOARD_MAC_INFO db88f6821InfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
MV_BOARD_USB_INFO db88f6821InfoBoardUsbInfo[] = {
@@ -1026,8 +1314,7 @@
/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
{ DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_FALSE }, /* NAND DEV */
{ DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE }, /* NOR DEV */
- { SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE }, /* SPI0 DEV */
- { SPI0_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE } /* SPI0 DEV */
+ { SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE } /* SPI0 DEV */
};
struct MV_BOARD_IO_EXPANDER db88f6821InfoBoardioExpValue[] = {
@@ -1054,6 +1341,8 @@
.pBoardMacInfo = db88f6821InfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -1081,7 +1370,7 @@
.nandFlashControl = DB_88F68XX_BOARD_NAND_CONTROL,
.nandIfMode = NAND_IF_NFC,
- .isSdMmcConnected = MV_FALSE,
+ .isSdMmcConnected = MV_TRUE,
.isSdMmc_1_8v_Connected = MV_FALSE,
/* NOR init params */
@@ -1092,7 +1381,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = ARRSZ(db88f6821InfoBoardioExpValue),
.pIoExp = db88f6821InfoBoardioExpValue,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_FALSE,
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*******************************************************************************
@@ -1117,28 +1411,28 @@
{ BOARD_DEV_TWSI_SATR, 1, 0x4c, ADDR7_BIT, MV_FALSE},
};
MV_BOARD_MAC_INFO dbAmc88f68xxInfoBoardMacInfo[] = {
- /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- { BOARD_MAC_SPEED_AUTO, 0x1, 0x1},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0},
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+ MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_FALSE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
MV_BOARD_USB_INFO dbAmc88f68xxInfoBoardUsbInfo[] = {
/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
- { USB_UNIT_ID, 1, MV_TRUE},
+ { USB_UNIT_ID, 0, MV_TRUE},
};
MV_DEV_CS_INFO dbAmc88f68xxInfoBoardDeCsInfo[] = {
/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
{ DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE }, /* NAND DEV */
{ DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_FALSE }, /* NOR DEV */
- { SPI0_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_FALSE }, /* SPI0 DEV */
- { SPI0_CS1, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE } /* SPI0 DEV */
+ { SPI1_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_TRUE } /* SPI0 DEV */
};
MV_BOARD_INFO dbAmc88f68xx_board_info = {
.boardName = "DB-88F6820-AMC",
- .compatibleDTName = "a385-amc",
+ .compatibleDTName = "a385-db-amc",
.numBoardNetComplexValue = 0,
.pBoardNetComplexInfo = NULL,
.pBoardMppConfigValue = dbAmc88f68xxInfoBoardMppConfigValue,
@@ -1153,6 +1447,8 @@
.pBoardMacInfo = dbAmc88f68xxInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = 0,
+ .numBoardIoExpPinInfo = 0,
+ .pBoardIoExpPinInfo = 0,
.activeLedsNumber = 0,
.pLedGppPin = NULL,
.ledsPolarity = 0,
@@ -1191,7 +1487,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = 0,
.pIoExp = NULL,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .isAmc = MV_TRUE, /* for DT update and switching services */
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
MV_BOARD_INFO *marvellBoardInfoTbl[] = {
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
index 1a4fb93..eeb5868 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
@@ -120,6 +120,28 @@
#define A38x_CUSTOMER_BOARD_1_GPP_POL_LOW 0x0
#define A38x_CUSTOMER_BOARD_1_GPP_POL_MID 0x0
+
+/******************************* SolidRun Board *******************************/
+/*******************************************************************************
+ * SolidRun ClearFog-A1 REV2.0 */
+/******************************************************************************/
+#define A38x_CLEARFOG_BOARD_MPP0_7 0x11111111
+#define A38x_CLEARFOG_BOARD_MPP8_15 0x11111111
+#define A38x_CLEARFOG_BOARD_MPP16_23 0x10460011
+#define A38x_CLEARFOG_BOARD_MPP24_31 0x22043333
+#define A38x_CLEARFOG_BOARD_MPP32_39 0x44400002
+#define A38x_CLEARFOG_BOARD_MPP40_47 0x41144004
+#define A38x_CLEARFOG_BOARD_MPP48_55 0x45333333
+#define A38x_CLEARFOG_BOARD_MPP56_63 0x00004444
+
+#define A38x_CLEARFOG_BOARD_GPP_OUT_ENA_LOW 0xFFFFFFFF
+#define A38x_CLEARFOG_BOARD_GPP_OUT_ENA_MID 0xFFFFFFFF
+
+#define A38x_CLEARFOG_BOARD_GPP_OUT_VAL_LOW 0x0
+#define A38x_CLEARFOG_BOARD_GPP_OUT_VAL_MID 0x0
+#define A38x_CLEARFOG_BOARD_GPP_POL_LOW 0x0
+#define A38x_CLEARFOG_BOARD_GPP_POL_MID 0x0
+
/*******************************************************************************
* A38x GFCH100
*******************************************************************************/
@@ -252,17 +274,18 @@
#define DB_AP_88F68XX_MPP0_7 0x11111111
#define DB_AP_88F68XX_MPP8_15 0x11111111
#define DB_AP_88F68XX_MPP16_23 0x55066011
-#define DB_AP_88F68XX_MPP24_31 0x05050050
+#define DB_AP_88F68XX_MPP24_31 0x05050050 /* 37: USB3_CfgCurrentLim(out1) */
#define DB_AP_88F68XX_MPP32_39 0x05055555
-#define DB_AP_88F68XX_MPP40_47 0x01100565
+#define DB_AP_88F68XX_MPP40_47 0x01100565 /* 43: USB3_OCSn(in), 44: USB3_VBUS_EN(out1) */
#define DB_AP_88F68XX_MPP48_55 0x00000000
#define DB_AP_88F68XX_MPP56_63 0x00004444
#define DB_AP_88F68XX_GPP_OUT_ENA_LOW (~(BIT21)) /* PIC (STR) GPIO = 21, 47 */
-#define DB_AP_88F68XX_GPP_OUT_ENA_MID (~(BIT1 | BIT2 | BIT3 | BIT15))
+#define DB_AP_88F68XX_GPP_OUT_ENA_MID (~(BIT1 | BIT2 | BIT3 | BIT5 | BIT15))
+ /*GPP_OUT_ENA_MID: BIT5(37):USB3_Cfg = High, BIT12(44):USB3_VBUS_EN = Low */
#define DB_AP_88F68XX_GPP_OUT_ENA_HIGH (~(BIT1))
#define DB_AP_88F68XX_GPP_OUT_VAL_LOW 0x0
-#define DB_AP_88F68XX_GPP_OUT_VAL_MID 0x0
+#define DB_AP_88F68XX_GPP_OUT_VAL_MID (BIT5)
#define DB_AP_88F68XX_GPP_OUT_VAL_HIGH 0x0
#define DB_AP_88F68XX_GPP_POL_LOW 0x0
#define DB_AP_88F68XX_GPP_POL_MID 0x0
@@ -324,7 +347,7 @@
#define DB_AMC_88F68XX_GPP_OUT_ENA_MID (~(BIT12 | BIT17 | BIT18 | BIT20 | BIT21)) /* 44:I2C_EXT_EN, 49,50,52,53:Leds*/
#define DB_AMC_88F68XX_GPP_OUT_ENA_HIGH 0xFFFFFFFF
#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT29) /* GPIO29: QS_SMI_ENA = OUT VAL High */
-#define DB_AMC_88F68XX_GPP_OUT_VAL_MID (BIT12) /* GPIO44: I2C_EXT_EN = OUT VAL High */
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID (BIT12) /* (was BIT12): GPIO44 I2C_EXT_EN = FALSE (False = OUT VAL High) */
#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
#define DB_AMC_88F68XX_GPP_POL_LOW 0x0
#define DB_AMC_88F68XX_GPP_POL_MID 0x0
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec39x.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec39x.c
index b90ba63..b186bfe 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec39x.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec39x.c
@@ -88,11 +88,11 @@
MV_BOARD_MAC_INFO armada_39x_customer_0_BoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_8 boardEthSmiAddr, MV_8
- * boardEthSmiAddr0, MV_PHY_PORT_TYPE portType}} */
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI},
- { BOARD_MAC_SPEED_AUTO, 0x5, 0x5, SMI},
- { BOARD_MAC_SPEED_AUTO, 0x4, 0x4, SMI},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI}
+ * boardEthSmiAddr0, MV_PHY_PORT_TYPE portType, MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x5, 0x5, SMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x4, 0x4, SMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI, MV_TRUE}
};
MV_BOARD_NET_COMPLEX_INFO armada_39x_customer_0_InfoBoardNetComplexInfo[] = {
@@ -120,6 +120,14 @@
{ SPI1_CS3, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 1, MV_FALSE } /* SPI1 DEV */
};
+MV_BOARD_USB_INFO armada_39x_customer_0_BoardUsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+ { USB3_UNIT_ID, 0, MV_FALSE},
+ { USB3_UNIT_ID, 1, MV_TRUE},
+ { USB_UNIT_ID, 0, MV_FALSE},
+};
+
+
MV_BOARD_MPP_INFO armada_39x_customer_0_BoardMppConfigValue[] = {
{ {
A39X_CUSTOMER_BOARD_0_MPP0_7,
@@ -133,6 +141,14 @@
} }
};
+/* gpp_callback is a generic place holder routine for special GPIO pull-up/sown sequence
+ * this routine is called as the final step of mvBoardEnvInit flow
+ * for example see implementation for SolidRun's clearFog board: A38x_CLEARFOG_BOARD_gpp_callback*/
+void A39x_CUSTOMER_BOARD_0_gpp_callback(MV_BOARD_INFO *board) {
+
+ /* implement special GPIO/MPP post configuration here */
+}
+
MV_BOARD_INFO armada_39x_customer_board_0_info = {
.boardName = "A39x-Customer-Board-0",
.numBoardNetComplexValue = ARRSZ(armada_39x_customer_0_InfoBoardNetComplexInfo),
@@ -164,7 +180,10 @@
.gppOutValMid = A39X_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID,
.gppPolarityValLow = A39X_CUSTOMER_BOARD_0_GPP_POL_LOW,
.gppPolarityValMid = A39X_CUSTOMER_BOARD_0_GPP_POL_MID,
+ .gppPostConfigCallBack = A39x_CUSTOMER_BOARD_0_gpp_callback,
+ .pBoardUsbInfo = armada_39x_customer_0_BoardUsbInfo,
+ .numBoardUsbInfo = ARRSZ(armada_39x_customer_0_BoardUsbInfo),
/* TDM */
.numBoardTdmInfo = {},
.pBoardTdmInt2CsInfo = {},
@@ -184,7 +203,9 @@
.configAutoDetect = MV_FALSE,
.numIoExp = 0,
.pIoExp = NULL,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
/*
@@ -239,11 +260,11 @@
MV_BOARD_MAC_INFO db88f69xxInfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_8 boardEthSmiAddr, MV_8
- * boardEthSmiAddr0, MV_PHY_PORT_TYPE portType}} */
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI},
- { BOARD_MAC_SPEED_AUTO, 0x5, 0x5, SMI},
- { BOARD_MAC_SPEED_AUTO, 0x4, 0x4, SMI},
- { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI}
+ * boardEthSmiAddr0, MV_PHY_PORT_TYPE portType, MV_BOOL boardMacEnabled;}} */
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x5, 0x5, SMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x4, 0x4, SMI, MV_TRUE},
+ { BOARD_MAC_SPEED_AUTO, 0x0, 0x0, XSMI, MV_TRUE}
};
MV_BOARD_NET_COMPLEX_INFO db88f69xxInfoBoarNetComplexInfo[] = {
@@ -331,7 +352,12 @@
.configAutoDetect = MV_TRUE,
.numIoExp = 0,
.pIoExp = NULL,
- .boardOptionsModule = MV_MODULE_NO_MODULE
+ .boardOptionsModule = MV_MODULE_NO_MODULE,
+ /* Audio */
+ .isAudioConnected = MV_FALSE,
+ .isTdmConnected = MV_FALSE,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0
};
MV_BOARD_INFO *marvellBoardInfoTbl[] = {
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
index c94b287..6e77d41 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
@@ -117,38 +117,45 @@
#define MV_6810_INDEX 1
#define MV_6811_INDEX 2
#define MV_6828_INDEX 3
+#define MV_6W22_INDEX 4 /* 6W22=A383 */
+#define MV_6W23_INDEX 5 /* 6W23=A384 */
#define MV_6920_INDEX 0
#define MV_6928_INDEX 1
-#define MAX_DEV_ID_NUM 4
+#define MAX_DEV_ID_NUM 6
#ifdef CONFIG_ARMADA_38X
MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
-/* 6820 6810 6811 6828 */
-/* DRAM_UNIT_ID */ { 1, 1, 1, 1},
-/* PEX_UNIT_ID */ { 4, 3, 3, 4},
-/* ETH_GIG_UNIT_ID */ { 3, 2, 2, 3}, /* total SoC MAC unit count (Not updated) */
-/* ETH_GIG_ACTIVE_UNIT_ID */ { 3, 2, 2, 3}, /* active MAC unit count (updated by ethComPhy) */
-/* USB_UNIT_ID */ { 1, 1, 0, 1},
-/* USB3_UNIT_ID */ { 2, 2, 2, 2},
-/* IDMA_UNIT_ID */ { 0, 0, 0, 0},
-/* XOR_UNIT_ID */ { 2, 2, 2, 2},
-/* SATA_UNIT_ID */ { 2, 2, 2, 4},
-/* TDM_32CH_UNIT_ID */ { 1, 1, 0, 1},
-/* UART_UNIT_ID */ { 4, 4, 4, 4},
-/* CESA_UNIT_ID */ { 2, 2, 2, 2},
-/* SPI_UNIT_ID */ { 2, 2, 2, 2},
-/* AUDIO_UNIT_ID */ { 1, 1, 0, 1},
-/* SDIO_UNIT_ID */ { 1, 1, 1, 1},
-/* TS_UNIT_ID */ { 0, 0, 0, 0},
-/* XPON_UNIT_ID */ { 0, 0, 0, 0},
-/* BM_UNIT_ID */ { 0, 0, 0, 0},
-/* PNC_UNIT_ID */ { 0, 0, 0, 0},
-/* I2C_UNIT_ID */ { 2, 2, 2, 2},
-/* QSGMII_UNIT_ID */ { 1, 0, 0, 1},
-/* XAUI_UNIT_ID */ { 0, 0, 0, 0},
-/* USB3_HOST_UNIT_ID*/ { 2, 2, 2, 2},
+/* 6820 6810 6811 6828 6W22 6W23 */
+/* A385 A380 A381/2 A388 A383 A384 */
+/* |======= HW Flavors =======| |==Virtual==|*/
+/* DRAM_UNIT_ID */ { 1, 1, 1, 1, 1, 1},
+/* PEX_UNIT_ID */ { 4, 3, 3, 4, 2, 2},
+/* ETH_GIG_UNIT_ID */ { 3, 2, 2, 3, 2, 2},
+/* ETH_GIG_UNIT_ID -> total SoC MAC unit count (Not updated) */
+/* ETH_GIG_ACTIVE_UNIT_ID */ { 3, 2, 2, 3, 2, 2},
+/* ETH_GIG_ACTIVE_UNIT_ID -> active MAC unit count (updated by ethComPhy) */
+/* USB_UNIT_ID */ { 1, 1, 0, 1, 1, 1},
+/* USB3_UNIT_ID */ { 2, 2, 2, 2, 1, 1},
+/* IDMA_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* XOR_UNIT_ID */ { 2, 2, 2, 2, 2, 2},
+/* SATA_UNIT_ID */ { 2, 2, 2, 4, 1, 1},
+/* TDM_32CH_UNIT_ID */ { 1, 1, 0, 1, 0, 1},
+/* UART_UNIT_ID */ { 4, 4, 4, 4, 1, 1},
+/* CESA_UNIT_ID */ { 2, 2, 2, 2, 2, 2},
+/* SPI_UNIT_ID */ { 2, 2, 2, 2, 2, 2},
+/* AUDIO_UNIT_ID */ { 1, 1, 0, 1, 0, 1},
+/* SDIO_UNIT_ID */ { 1, 1, 1, 1, 1, 1},
+/* TS_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* XPON_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* BM_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* PNC_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* I2C_UNIT_ID */ { 2, 2, 2, 2, 1, 1},
+/* QSGMII_UNIT_ID */ { 1, 0, 0, 1, 0, 0},
+/* XAUI_UNIT_ID */ { 0, 0, 0, 0, 0, 0},
+/* USB3_HOST_UNIT_ID*/ { 2, 2, 2, 2, 1, 1},
+/* SERDES_UNIT_ID */ { 6, 5, 4, 6, 4, 4},
};
#else /* if (CONFIG_ARMADA_39X) */
MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
@@ -176,6 +183,7 @@
/* QSGMII_UNIT_ID */ { 0, 1},
/* XAUI_UNIT_ID */ { 1, 1},
/* USB3_HOST_UNIT_ID */ { 1, 2},
+/* SERDES_UNIT_ID */ { 7, 7},
};
#endif
@@ -189,6 +197,10 @@
#define SERDES_RXAUI(x) (0x100 << x) /* bits 8 : RXAUI port 0 indication */
static MV_U32 ethComPhy;
+/* usbComPhy: bit description for USB port per SerDes Lane,
+ if SerDes lane connected to USB host #X, enable bit #X usbComPhy */
+static MV_U32 usbComPhy;
+
/* Only the first unit, only the second unit or both can be active on the specific board */
static MV_BOOL sataUnitActive[MV_SATA_MAX_UNIT] = {MV_FALSE, MV_FALSE};
@@ -300,6 +312,7 @@
MV_U32 mvCtrlDevIdIndexGet(MV_U32 ctrlModel)
{
switch (ctrlModel) {
+ /* HW flavors */
case MV_6820_DEV_ID:
return MV_6820_INDEX;
case MV_6810_DEV_ID:
@@ -312,6 +325,11 @@
return MV_6920_INDEX;
case MV_6928_DEV_ID:
return MV_6928_INDEX;
+ /* Virtual flavors */
+ case MV_6W22_DEV_ID: /* 6W22=A383 */
+ return MV_6W22_INDEX;
+ case MV_6W23_DEV_ID: /* 6W23=A384 */
+ return MV_6W23_INDEX;
default:
return MV_6820_INDEX;
}
@@ -412,7 +430,26 @@
} else
return serdesNum;
}
-
+/******************************************************************************
+* mvCtrlIsUsbSerDesConnected
+*
+* DESCRIPTION: check if SerDes lane is connected to USB3 host.
+*
+*
+* INPUT: None
+*
+* OUTPUT: None
+*
+* RETURN:return true if SerDes lane is connected to USB3 host, false otherwise.
+*
+*
+*******************************************************************************/
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort)
+{
+ if (((usbComPhy >> usbPort) & 0X1) == 1)
+ return MV_TRUE;
+ return MV_FALSE;
+}
/*******************************************************************************
* mvCtrlSerdesConfigDetect
*
@@ -440,10 +477,8 @@
MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet();
- maxSerdesLane = MV_SERDES_MAX_LANES;
- if (MV_6810_DEV_ID == mvCtrlModelGet())
- maxSerdesLane = MV_SERDES_MAX_LANES_6810;
-
+ maxSerdesLane = mvCtrlSocUnitInfoNumGet(SERDES_UNIT_ID);
+ usbComPhy = 0;
memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO));
commPhyCfgReg = MV_REG_READ(COMM_PHY_SELECTOR_REG);
DB(printf("mvCtrlSerdesConfig: commPhyCfgReg=0x%x\n", commPhyCfgReg));
@@ -456,12 +491,17 @@
ifNo = comPhyCfg & 0x0f;
switch (comPhyCfg & 0xF0) {
case SERDES_UNIT_PEX:
- if ((ifNo == PEX0_IF) && (commPhyCfgReg & PCIE0_X4_EN_MASK))
- boardPexInfo->pexUnitCfg[ifNo] = PEX_BUS_MODE_X4;
- else
+ if ((ifNo == PEX0_IF) && (commPhyCfgReg & PCIE0_X4_EN_MASK)) {
+ if (serdesNum == 0) {
+ boardPexInfo->pexUnitCfg[ifNo] = PEX_BUS_MODE_X4;
+ boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = ifNo;
+ boardPexInfo->boardPexIfNum++;
+ }
+ } else {
boardPexInfo->pexUnitCfg[ifNo] = PEX_BUS_MODE_X1;
- boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = ifNo;
- boardPexInfo->boardPexIfNum++;
+ boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = ifNo;
+ boardPexInfo->boardPexIfNum++;
+ }
DB(printf("PEX, if=%d\n", ifNo));
break;
case SERDES_UNIT_SATA:
@@ -494,6 +534,7 @@
break;
case SERDES_UNIT_USB_H:
DB(printf("USB_H, if=%d\n", ifNo));
+ usbComPhy |= 0X1 << ifNo;
usbHIfCount++;
break;
case SERDES_UNIT_USB:
@@ -594,8 +635,10 @@
if (!(mvBoardIsModuleConnected(MV_MODULE_NOR) ||
mvBoardIsModuleConnected(MV_MODULE_NAND) ||
mvBoardIsModuleConnected(MV_MODULE_NAND_ON_BOARD) ||
- mvCtrlModelGet() == MV_6811_DEV_ID))
- ethComPhy |= ON_BOARD_RGMII(1); /* NOR/NAND modules overides RGMII-1 MPP's */
+ mvCtrlModelGet() == MV_6811_DEV_ID ||
+ (mvCtrlModelGet() == MV_6W22_DEV_ID && mvBoardIdGet() == DB_BP_6821_ID))) {
+ ethComPhy |= ON_BOARD_RGMII(1); /* NOR/NAND modules overides RGMII-1 MPP's */
+ }
mvCtrlSerdesConfigDetect();
@@ -640,9 +683,14 @@
/*SDIO PUP Enable (BIT6) */
MV_REG_BIT_SET(PUP_EN_REG, BIT6);
+ /*SDIO Clk PUP Enable (BIT7) */
+ MV_REG_BIT_SET(PUP_EN_REG, BIT7);
+
/* Sdio_jtag_cell_oe_smp_en */
MV_REG_BIT_SET(PUP_EN_REG, BIT14);
+ /* Sdio Clk jtag cell oe smp en */
+ MV_REG_BIT_SET(PUP_EN_REG, BIT15);
/* XXX: Following setting should be configured by u-boot */
MV_REG_BIT_SET(SOC_DEV_MUX_REG, BIT0); /* Configure NAND flush enabled */
@@ -707,11 +755,23 @@
MV_U32 mvCtrlbootSrcGet(void)
{
MV_U32 satrVal, bootSrc;
+ MV_U32 secBootCtrl = MV_REG_READ(SECURE_BOOT_REG);
- satrVal = MV_REG_READ(MPP_SAMPLE_AT_RESET);
- bootSrc = (satrVal & SATR_BOOT_SRC_MASK) >> SATR_BOOT_SRC_OFFS;
+ if ((secBootCtrl & SECURE_BOOT_ENA_MASK) != 0) {
+ /* Secure mode
+ Once the secure mode activated by efuse, the actual
+ boot device is always taken from the efuse by the HW
+ and any other boot device configured by SatR is ignored.
+ */
+ bootSrc = (secBootCtrl & SECURE_BOOT_DEVICE_MASK) >> SECURE_BOOT_DEVICE_OFFS;
+ } else {
- DB(mvOsPrintf("%s: Read from S@R BOOTSRC = 0x%X\n", __func__, bootSrc));
+ satrVal = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ bootSrc = (satrVal & SATR_BOOT_SRC_MASK) >> SATR_BOOT_SRC_OFFS;
+
+ DB(mvOsPrintf("%s: Read from S@R BOOTSRC = 0x%X\n", __func__, bootSrc));
+ }
+
return bootSrc;
}
@@ -1296,12 +1356,16 @@
MV_U32 defaultCtrlId, ctrlId = (MV_REG_READ(DEV_ID_REG) & (DEVICE_ID_MASK)) >> DEVICE_ID_OFFS;
switch (ctrlId) {
+ /* HW flavors */
case MV_6820_DEV_ID:
case MV_6810_DEV_ID:
case MV_6811_DEV_ID:
case MV_6828_DEV_ID:
case MV_6920_DEV_ID:
case MV_6928_DEV_ID:
+ /* Virtual flavors */
+ case MV_6W22_DEV_ID: /* 6W22=A383 */
+ case MV_6W23_DEV_ID: /* 6W23=A384 */
return ctrlId;
default:
/*Device ID Default for A38x: 6820 , for A39x: 6920 */
@@ -1332,6 +1396,7 @@
MV_U16 mvCtrlDeviceIdGet(MV_VOID)
{
switch (mvCtrlModelGet()) {
+ /* HW flavors */
case MV_6810_DEV_ID:
return 0x380;
case MV_6811_DEV_ID:
@@ -1340,6 +1405,11 @@
return 0x385;
case MV_6828_DEV_ID:
return 0x388;
+ /* Virtual flavors */
+ case MV_6W22_DEV_ID: /* 6W22=A383 */
+ return 0x383;
+ case MV_6W23_DEV_ID: /* 6W23=A384 */
+ return 0x384;
default:
return 0x380; /* use lower device as default in case of error */
}
@@ -1388,7 +1458,16 @@
*******************************************************************************/
MV_STATUS mvCtrlNameGet(char *pNameBuff)
{
- mvOsSPrintf(pNameBuff, "%s%x", SOC_NAME_PREFIX, mvCtrlModelGet());
+ MV_U16 ctrlModel = mvCtrlModelGet();
+ /* Virtual Flavors has different ctrlModel values than
+ * it's Controller names: 6W22: 0x6823 | 6W23: 0x6824 */
+ if (ctrlModel == MV_6W22_DEV_ID)
+ mvOsSPrintf(pNameBuff, "%s%s", SOC_NAME_PREFIX, MV_6W22_DEV_NAME);
+ else if (ctrlModel == MV_6W23_DEV_ID)
+ mvOsSPrintf(pNameBuff, "%s%s", SOC_NAME_PREFIX, MV_6W23_DEV_NAME);
+ else
+ mvOsSPrintf(pNameBuff, "%s%x", SOC_NAME_PREFIX, ctrlModel);
+
return MV_OK;
}
@@ -2146,8 +2225,14 @@
MV_32 reg = 0;
/* Initiates TSEN hardware reset once */
- if ((MV_REG_READ(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
- MV_REG_BIT_SET(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
+ if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) {
+ MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
+ /* set Tsen Tc Trim to correct default value (errata #132698) */
+ reg = MV_REG_READ(TSEN_CONTROL_LSB_REG);
+ reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK;
+ reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET;
+ MV_REG_WRITE(TSEN_CONTROL_LSB_REG, reg);
+ }
mvOsDelay(10);
/* Check if the readout field is valid */
@@ -2158,8 +2243,9 @@
reg = MV_REG_READ(TSEN_STATUS_REG);
reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
- return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
+ return ((4761 * reg) - 2791000) / 10000;
}
+
/*******************************************************************************
* mvCtrlNandClkSet
*
@@ -2218,66 +2304,21 @@
* mvCtrlUsbMapGet
*
* DESCRIPTION:
-* Get the map of USB ports if exists
+* Controller USB mapping is not valid for A38x/a39x Port are mapped per board via mvBoardIsUsbPortConnected.
*
* INPUT:
* the current USB unit(USB3.0 or USB2.0)
* the current usbActive(not used, relevant for other SoC)
*
* OUTPUT:
-* Mapped usbActive.
+* Mapped usbActive.
*
* RETURN:
* None
*******************************************************************************/
MV_U32 mvCtrlUsbMapGet(MV_U32 usbUnitId, MV_U32 usbActive)
{
- MV_U32 lane5Cfg, lane3Cfg, phySelector;
-
- /* On A39x and A38x A0 revision, there are 2 USB3.0 MACs, and the connectivity of the
- USB3.0 depends on the SerDes configuration:
- 2 SerDes lanes for USB3.0:
- | usbActive | USB port |
- -----------------------------------------
- | 0 | USB3.0 Host Port #0 |
- | 1 | USB3.0 Host Port #1 |
-
- single SerDes lane#5 Or single SerDes lane#3 for USB3.0
- | usbActive | USB port |
- ---------------------------------------------------------
- | 0 | USB3.0 Host Port #1 |
- | 1 | USB2.0 via USB3.0 Host Port #0 |
-
- When only single USB3.0 Host port #1 is connected via SerDes Lane 3 or 5,
- map the USB port #1 to be usbActive=0
- */
-
- /* if a38x Z0 rev, return original mapping */
- if (mvCtrlDevFamilyIdGet(0) == MV_88F68XX && mvCtrlRevGet() == MV_88F68XX_Z1_ID)
- return usbActive;
-
- /* if only single USB3.0 SerDes, via Lane5 or via lane3 */
- if (usbUnitId == USB3_UNIT_ID && mvCtrlUsb3MaxGet() == 1) {
- phySelector = MV_REG_READ(COMM_PHY_SELECTOR_REG);
- lane5Cfg = (phySelector & COMPHY_SELECT_MASK(5)) >> COMPHY_SELECT_OFFS(5);
- lane3Cfg = (phySelector & COMPHY_SELECT_MASK(3)) >> COMPHY_SELECT_OFFS(3);
- if (lane5Cfg == COMPHY_SELECT_LANE5_USB3_VAL ||
- lane3Cfg == COMPHY_SELECT_LANE3_USB3_VAL)
- return 1 - usbActive;
- }
-#ifdef CONFIG_ARMADA_39X
- /* temporery fix for A39x:
- In order to keep the same USB mapping for xHCI usage,
- nevermind if port is connected with SerDes lane, or without,
- return the same mapping for all xHCI/USB3.0 usage.
- TODO: remove USB mapping and use USB board structre information */
- if (usbUnitId == USB3_UNIT_ID)
- return 1 - usbActive;
-#endif
- /* If A39x or A38x A0 rev, but the no mapping needed:
- * - single USB#0 in use
- * - both USB units are in use */
-
+ /*No controller port mapping for a38x/a39x*/
return usbActive;
}
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
index f22a9be..140b24c 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
@@ -126,13 +126,13 @@
/* Lane 0 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 0, SERDES_UNIT_GBE | 0,\
SERDES_UNIT_GBE, SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA,\
SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
-/* Lane 1 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_SATA | 0,\
+/* Lane 1 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 0,\
SERDES_UNIT_GBE | 0, SERDES_UNIT_GBE | 1, SERDES_UNIT_USB_H | 0, SERDES_UNIT_QSGMII | 0,\
SERDES_UNIT_GBE | 0, SERDES_UNIT_GBE | 0, SERDES_UNIT_NA}, \
-/* Lane 2 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_PEX | PEX2_IF, SERDES_UNIT_SATA | 1,\
+/* Lane 2 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 1,\
SERDES_UNIT_GBE | 1, SERDES_UNIT_GBE | 1, SERDES_UNIT_NA, SERDES_UNIT_NA,\
SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
-/* Lane 3 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_SATA | 3,\
+/* Lane 3 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 3,\
SERDES_UNIT_GBE | 2, SERDES_UNIT_USB_H | 1, SERDES_UNIT_USB, SERDES_UNIT_GBE | 2,\
SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
/* Lane 4 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_NA, SERDES_UNIT_GBE | 1,\
@@ -147,13 +147,13 @@
/* Lane 0 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 0, SERDES_UNIT_GBE | 0,\
SERDES_UNIT_GBE, SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA,\
SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
-/* Lane 1 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_SATA | 0,\
+/* Lane 1 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 0,\
SERDES_UNIT_GBE | 0, SERDES_UNIT_GBE | 1, SERDES_UNIT_USB_H | 0, SERDES_UNIT_QSGMII | 0,\
SERDES_UNIT_GBE | 0, SERDES_UNIT_GBE | 0, SERDES_UNIT_NA}, \
-/* Lane 2 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_PEX | PEX2_IF, SERDES_UNIT_SATA | 1,\
+/* Lane 2 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 1,\
SERDES_UNIT_GBE | 1, SERDES_UNIT_GBE | 1, SERDES_UNIT_NA, SERDES_UNIT_NA,\
SERDES_UNIT_NA, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
-/* Lane 3 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_SATA | 3,\
+/* Lane 3 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX3_IF, SERDES_UNIT_PEX | PEX0_IF, SERDES_UNIT_SATA | 3,\
SERDES_UNIT_GBE | 2, SERDES_UNIT_USB_H | 1, SERDES_UNIT_USB, SERDES_UNIT_GBE | 2,\
SERDES_UNIT_XAUI | 3, SERDES_UNIT_NA, SERDES_UNIT_NA}, \
/* Lane 4 */ {SERDES_UNIT_NA, SERDES_UNIT_PEX | PEX1_IF, SERDES_UNIT_NA, SERDES_UNIT_GBE | 1,\
@@ -170,13 +170,13 @@
/* Termal Sensor Registers */
-#define TSEN_STATE_REG 0xE4070
-#define TSEN_STATE_OFFSET 31
-#define TSEN_STATE_MASK (0x1 << TSEN_STATE_OFFSET)
+#define TSEN_CONTROL_LSB_REG 0xE4070
+#define TSEN_CONTROL_LSB_TC_TRIM_OFFSET 0
+#define TSEN_CONTROL_LSB_TC_TRIM_MASK (0x7 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET)
-#define TSEN_CONF_REG 0xE4074
-#define TSEN_CONF_RST_OFFSET 8
-#define TSEN_CONF_RST_MASK (0x1 << TSEN_CONF_RST_OFFSET)
+#define TSEN_CONTROL_MSB_REG 0xE4074
+#define TSEN_CONTROL_MSB_RST_OFFSET 8
+#define TSEN_CONTROL_MSB_RST_MASK (0x1 << TSEN_CONTROL_MSB_RST_OFFSET)
#define TSEN_STATUS_REG 0xE4078
#define TSEN_STATUS_READOUT_VALID_OFFSET 10
@@ -209,6 +209,7 @@
MV_BOOL mvCtrlSSCGInit(void);
MV_BOOL mvCtrlPortIsSerdesSgmii(MV_U32 ethPort);
MV_BOOL mvCtrlPortIsSerdesRxaui(MV_U32 ethPort);
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort);
MV_BOOL mvCtrlPortIsRgmii(MV_U32 ethPort);
MV_U32 mvCtrlGetCpuNum(MV_VOID);
MV_U32 mvCtrlDevIdIndexGet(MV_U32 ctrlModel);
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvRegs.h
index a30eb3c..2b4c94a 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -228,6 +228,15 @@
#define GENERAL_PURPOSE_RESERVED1_REG 0x182E4
#define GENERAL_PURPOSE_RESERVED1_DEFAULT_VALUE (~BIT17)
+/*****************/
+/* Secure boot */
+/*****************/
+#define SECURE_BOOT_REG 0x18280
+#define SECURE_BOOT_ENA_OFFS 0
+#define SECURE_BOOT_ENA_MASK (1 << SECURE_BOOT_ENA_OFFS)
+#define SECURE_BOOT_DEVICE_OFFS 8
+#define SECURE_BOOT_DEVICE_MASK (0xFF << SECURE_BOOT_DEVICE_OFFS)
+
/* USB3 registers */
#define MV_USB3_WIN_BASE(dev) (MV_USB3_REGS_BASE(dev) + 0x4000)
@@ -369,6 +378,7 @@
MV_U32 ddrFreq;
MV_U32 l2Freq;
MV_BOOL isDisplay;
+ MV_BOOL isLimited;
} MV_FREQ_MODE;
/* End of Table indicator - Should be in the last line of the SAR Table */
@@ -379,31 +389,37 @@
#ifdef CONFIG_DDR4
#define MV_SAR_FREQ_MODES { \
- { 0x6, 1200, 600, 600, MV_TRUE }, \
- { 0x8, 1332, 666, 666, MV_TRUE }, \
- { 0xC, 1600, 800, 800, MV_TRUE }, \
- { 0x12, 1800, 900, 900, MV_TRUE }, \
- { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE } \
+ /*ID, CPU, DDR, L@, isDisaply?, isLimited? */\
+ { 0x6, 1200, 600, 600, MV_TRUE , MV_FALSE}, \
+ { 0x8, 1332, 666, 666, MV_TRUE , MV_FALSE}, \
+ { 0xC, 1600, 800, 800, MV_TRUE , MV_FALSE}, \
+ { 0x10, 1866, 933, 933, MV_TRUE , MV_TRUE}, \
+ { 0x13, 2000, 933, 1000, MV_TRUE , MV_TRUE}, \
+ { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE, MV_FALSE } \
};
#else
#ifdef CONFIG_ARMADA_38X
#define MV_SAR_FREQ_MODES { \
- { 0x0, 666, 333, 333, MV_TRUE }, \
- { 0x2, 800, 400, 400, MV_TRUE }, \
- { 0x4, 1066, 533, 533, MV_TRUE }, \
- { 0x6, 1200, 600, 600, MV_TRUE }, \
- { 0x8, 1332, 666, 666, MV_TRUE }, \
- { 0xC, 1600, 800, 800, MV_TRUE }, \
- { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE } \
+ /*ID, CPU, DDR, L2, isDisaply?, isLimited? */\
+ { 0x0, 666, 333, 333, MV_TRUE , MV_FALSE}, \
+ { 0x2, 800, 400, 400, MV_TRUE , MV_FALSE}, \
+ { 0x4, 1066, 533, 533, MV_TRUE , MV_FALSE}, \
+ { 0x6, 1200, 600, 600, MV_TRUE , MV_FALSE}, \
+ { 0x8, 1332, 666, 666, MV_TRUE , MV_FALSE}, \
+ { 0xC, 1600, 800, 800, MV_TRUE , MV_FALSE}, \
+ { 0x10, 1866, 933, 933, MV_TRUE , MV_TRUE}, \
+ { 0x13, 2000, 933, 1000, MV_TRUE , MV_TRUE}, \
+ { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE, MV_FALSE } \
};
#else
#define MV_SAR_FREQ_MODES { \
- { 0x4, 1066, 533, 533, MV_TRUE }, \
- { 0x6, 1200, 600, 600, MV_TRUE }, \
- { 0x8, 1332, 666, 666, MV_TRUE }, \
- { 0xC, 1600, 800, 800, MV_TRUE }, \
- { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE } \
+ /*ID, CPU, DDR, L@, isDisaply?,isLimited? */\
+ { 0x4, 1066, 533, 533, MV_TRUE , MV_FALSE}, \
+ { 0x6, 1200, 600, 600, MV_TRUE , MV_FALSE}, \
+ { 0x8, 1332, 666, 666, MV_TRUE , MV_FALSE}, \
+ { 0xC, 1600, 800, 800, MV_TRUE , MV_FALSE}, \
+ { MV_SAR_FREQ_MODES_EOT, 0, 0, 0, MV_FALSE, MV_FALSE} \
};
#endif
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvSpec.h
index 41e75b7..e1f0d4c 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -118,11 +118,14 @@
(MV_ETH_BASE_ADDR_PORT1_2 + (((p) - 1) * 0x4000)))
#define MV_ETH_SGMII_PHY_REGS_OFFSET(p) (MV_ETH_REGS_OFFSET(p)+0x2000)
+#define MV_TDM_OFFSET (0xB0000)
#define MV_PEX_IF_REGS_OFFSET(pexIf) (((pexIf) == 0) ? 0x80000 : (0x40000 + ((pexIf-1) * 0x4000)))
#define MV_USB_REGS_OFFSET(dev) (0x58000)
#define MV_USB3_REGS_OFFSET(dev) (0xF0000 + (dev * 0x8000))
#define MV_USB2_USB3_REGS_OFFSET(unitType, dev) (unitType == USB_UNIT_ID ? \
MV_USB_REGS_OFFSET(dev) : MV_USB3_REGS_OFFSET(dev))
+#define MV_USB3_DEVICE_REGS_OFFSET (0x50000)
+#define MV_USB3_DEVICE_USB2_REGS_OFFSET (0x54100)
#define MV_XOR_REGS_OFFSET(unit) (0x60800 + (unit)*0x100)
#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000))
#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000))
@@ -133,6 +136,7 @@
#define MV_NFC_REGS_OFFSET (0xD0000)
#define MV_SDMMC_REGS_OFFSET (0xD8000)
#define MV_SDMMC_WINDOWS_REGS_OFFSET (0xDC000)
+#define MV_AUDIO_OFFSET (0xE8000)
#define SATA3_NUM_OF_PORTS 2
#define SATA3_MAX_PORTS_PER_UNIT 2
@@ -239,6 +243,7 @@
#define MV_ETH_MAX_RXQ 8
#define MV_ETH_MAX_TXQ 8
#define MV_ETH_TX_CSUM_MAX_SIZE 9800
+#define MV_ETH_TX_CSUM_MIN_SIZE 2048
#define MV_ETH_TX_CSUM_MAX_SIZE_SMALL 2048
#define MV_PNC_TCAM_LINES 1024 /* TCAM num of entries */
@@ -306,6 +311,7 @@
QSGMII_UNIT_ID,
XAUI_UNIT_ID,
USB3_HOST_UNIT_ID, /* USB3.0 HOST ports */
+ SERDES_UNIT_ID,
MAX_UNITS_ID
} MV_UNIT_ID;
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvAhbToMbusRegs.h
index 4660c50..35b3710 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvAhbToMbusRegs.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvAhbToMbusRegs.h
@@ -131,7 +131,7 @@
#define SRAMWCR_SIZE_MASK (0x7 << SRAMWCR_SIZE_OFFS)
#define SRAMWCR_BASE_OFFS 16
#define SRAMWCR_BASE_MASK (0xFFFF << SRAMWCR_BASE_OFFS)
-
+#define L2_FILTER_BASE_REG 0x8c04
/**********************/
/* MBUS BRIDGE WINDOW */
/**********************/
@@ -141,4 +141,6 @@
#define BRIDGWCR_SIZE_MASK (0xFFFF << BRIDGWCR_SIZE_OFFS)
#define MBUS_BRIDGE_WIN_BASE_REG (MV_MBUS_REGS_OFFSET + 0x254)
+
+
#endif /* __INCmvAhbToMbusRegsh */
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvCpuIf.c
index f5ebb2d..73e8f90 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvCpuIf.c
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/sys/mvCpuIf.c
@@ -957,6 +957,33 @@
}
/*******************************************************************************
+* mvCpuIfL2FilterSet
+*
+* DESCRIPTION:
+* Set L2 Filter base - IO prioritization filter
+*
+* INPUT:
+* L2 base value
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvCpuIfL2FilterSet(MV_U32 base)
+{
+ /* 0.25GB reserved for IO - verify no collision with IO @ 3.75GB (0xf000000) */
+ if (base > 0xf0000000) {
+ mvOsPrintf("Error: Requested L2 base (%x) overlaps with IO at 3.75GB\n", base);
+ return;
+ }
+
+ MV_REG_WRITE(L2_FILTER_BASE_REG, base);
+}
+
+/*******************************************************************************
* mvCpuIfMbusWindowSet
*
* DESCRIPTION:
@@ -976,6 +1003,9 @@
{
MV_U32 reg;
+ /* Align L2 (IO) filter with MBUS base */
+ mvCpuIfL2FilterSet(base);
+
MV_REG_WRITE(MBUS_BRIDGE_WIN_BASE_REG, base);
/* Align window size to 64KB */
size = ((size / _64K) - 1) << BRIDGWCR_SIZE_OFFS;
diff --git a/board/mv_ebu/a38x/cmd_efuse.c b/board/mv_ebu/a38x/cmd_efuse.c
index b70fb7d..fafeec0 100644
--- a/board/mv_ebu/a38x/cmd_efuse.c
+++ b/board/mv_ebu/a38x/cmd_efuse.c
@@ -251,13 +251,19 @@
val[2] = MV_EFUSE_REG_READ(EFUSE_BIT_64_ADDR(line));
DBPR("Read from %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), val[2]);
- MV_EFUSE_REG_WRITE(EFUSE_BIT_31_0_ADDR(line), val[0]);
- DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_31_0_ADDR(line), val[0]);
- MV_EFUSE_REG_WRITE(EFUSE_BIT_63_32_ADDR(line), val[1]);
- DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_63_32_ADDR(line), val[1]);
- MV_EFUSE_REG_BIT_SET(EFUSE_BIT_64_ADDR(line), 0x1);
- DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), 0x1);
- mvOsDelay(5);
+ if (val[2] == 0) { /* If the eFuse not yet burned by tester */
+ /* invalidate eFuse data before validating the row */
+ val[0] = 0xFFFFFFFF;
+ val[1] = 0x00FFFFFF;
+
+ MV_EFUSE_REG_WRITE(EFUSE_BIT_31_0_ADDR(line), val[0]);
+ DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_31_0_ADDR(line), val[0]);
+ MV_EFUSE_REG_WRITE(EFUSE_BIT_63_32_ADDR(line), val[1]);
+ DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_63_32_ADDR(line), val[1]);
+ MV_EFUSE_REG_BIT_SET(EFUSE_BIT_64_ADDR(line), 0x1);
+ DBPR("Write to %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), 0x1);
+ mvOsDelay(5);
+ }
}
}
diff --git a/board/mv_ebu/a38x/cmd_sar38x.c b/board/mv_ebu/a38x/cmd_sar38x.c
index ef514f9..ff36066 100755
--- a/board/mv_ebu/a38x/cmd_sar38x.c
+++ b/board/mv_ebu/a38x/cmd_sar38x.c
@@ -23,12 +23,13 @@
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "boardEnv/mvBoardEnvLib.h"
+#include "switchingServices/switchingServices.h"
enum {
CMD_DUMP = MV_SATR_MAX_OPTION+1,
CMD_DEFAULT,
CMD_UNKNOWN,
- CMD_NOT_ACTIVE // Command that requests valid but not active field on current board
+ CMD_NOT_ACTIVE // Command that requests valid but not active field on current board
};
MV_FREQ_MODE cpuDdrClkTbl[] = MV_SAR_FREQ_MODES;
@@ -46,7 +47,7 @@
MV_SATR_TYPE_ID satrId;
MV_U32 defauleValueForBoard[MV_MARVELL_BOARD_NUM];
} MV_BOARD_SATR_DEFAULT;
-#define MAX_DEFAULT_ENTRY 16
+#define MAX_DEFAULT_ENTRY 23
MV_BOARD_SATR_DEFAULT boardSatrDefault[MAX_DEFAULT_ENTRY] = {
/* defauleValueForBoard[] = RD_NAS_68xx, DB_BP_68xx, RD_WAP_68xx, DB_AP_68xx , DB_GP_68xx, DB_BP_6821, DB-AMC */
{ MV_SATR_CPU_DDR_L2_FREQ, {0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x4, 0x0c}},
@@ -65,6 +66,13 @@
{ MV_SATR_DB_USB3_PORT1, {0, 0, 0, 0, 0, 0, 0}},
{ MV_SATR_DDR_ECC_ENABLE, {0, 0, 0, 0, 0, 0, 1}},
{ MV_SATR_DDR_ECC_PUP_SEL, {0, 0, 0, 0, 0, 0, 1}},
+{ MV_SATR_FULL_FLAVOR, {0, 1, 0, 1, 1, 1, 0} },
+{ MV_SATR_TDM_CONNECTED, {0, 1, 0, 0, 0, 0, 0} },
+{ MV_SATR_TDM_PLACE_HOLDER, {0, 1, 0, 0, 0, 0, 0} },
+{ MV_SATR_BOARD_SPEED, {0, 0x1, 0, 0x1, 0x1, 0, 0x1} },
+{ MV_SATR_AVS_SKIP, {0, 0x1, 0, 0x1, 0x1, 0x1, 0x1} },
+{MV_SATR_BOOT_DEVICE, {0, 0, 0, 0, 0, 0, 0} },/* Dummy entry: default value taken from S@R register */
+{MV_SATR_BOOT2_DEVICE, {0, 0, 0, 0, 0, 0, 0} },/* Dummy entry: default value taken from S@R register */
};
char *lane1Arr[7] = { "Unconnected" ,
@@ -83,17 +91,49 @@
char *devIdArr[4] = {
"6810 (A380)",
"6820 (A385)",
- "6811 (A381/2)",
+ "N/A",
"6828 (A388)" };
-MV_BOOL mvVerifyRequest(void)
+static MV_U32 getBoardSpeed(MV_U32 boardspeed)
{
- readline(" ");
- if(strlen(console_buffer) == 0 || /* if pressed Enter */
- strcmp(console_buffer,"n") == 0 ||
- strcmp(console_buffer,"N") == 0 ) {
- printf("\n");
- return MV_FALSE;
+ switch (boardspeed) {
+ case 1:
+ return 2000;
+ case 2:
+ return 1866;
+ case 3:
+ return 1600;
+ default:
+ return 0;
+ }
+}
+/*
+ * when each CPU is checked, max CPU speed is determined for each board
+ * To enable the speed limitation for each board, the according value is written
+ * in SatR field 'boardspeed':
+ * -0x1 for max value 2000Mhz
+ * -0x2 for max value 1866MHz
+ * -0x3 for max value 1600MHz
+ *
+ * The function returns MV_TRUE if the cpuMode is not limited on this board
+ * by checking the 'boardspeed' field, otherwise returns MV_FALSE
+ */
+static MV_BOOL isCpuModeSupportedForBoard(int index, MV_BOOL printError)
+{
+ MV_U32 tmp;
+
+ if (cpuDdrClkTbl[index].isLimited == MV_TRUE) {
+ tmp = mvBoardSatRRead(MV_SATR_BOARD_SPEED);
+ if (tmp == MV_ERROR) {
+ mvOsPrintf("Failed reading 'boardspeed' SatR field\n");
+ return MV_FALSE;
+ }
+
+ if (cpuDdrClkTbl[index].cpuFreq > getBoardSpeed(tmp)) {
+ if (printError == MV_TRUE)
+ mvOsPrintf("Maximum supported CPU speed is %uMHz\n", getBoardSpeed(tmp));
+ return MV_FALSE;
+ }
}
return MV_TRUE;
}
@@ -103,11 +143,17 @@
MV_U32 i, rc, defaultValue, boardId = mvBoardIdIndexGet(mvBoardIdGet());
MV_SATR_TYPE_ID satrClassId;
MV_BOARD_SATR_INFO satrInfo;
-
+ MV_U32 satrBootDeviceValue = mvCtrlbootSrcGet(), tmp;
for (i = 0; i < MAX_DEFAULT_ENTRY; i++) {
satrClassId = boardSatrDefault[i].satrId;
if (mvBoardSatrInfoConfig(satrClassId, &satrInfo) != MV_OK)
continue;
+ if (satrClassId == MV_SATR_BOOT_DEVICE)
+ boardSatrDefault[i].defauleValueForBoard[boardId] = satrBootDeviceValue & satrInfo.mask;
+ if (satrClassId == MV_SATR_BOOT2_DEVICE) {
+ tmp = satrBootDeviceValue >> MV_SATR_BOOT2_VALUE_OFFSET;
+ boardSatrDefault[i].defauleValueForBoard[boardId] = tmp & MV_SATR_BOOT2_VALUE_MASK;
+ }
defaultValue = boardSatrDefault[i].defauleValueForBoard[boardId];
rc = mvBoardSatRWrite(satrClassId, defaultValue);
if (rc == MV_ERROR) {
@@ -116,11 +162,16 @@
}
/* set default Device ID - if MV_SATR_DEVICE_ID field is relevant on board */
- if (mvBoardSatrInfoConfig(MV_SATR_DEVICE_ID, &satrInfo) == MV_OK) {
- if (mvBoardSatRWrite(MV_SATR_DEVICE_ID, mvCtrlDevIdIndexGet(mvCtrlModelGet())) == MV_ERROR)
- mvOsPrintf("Error writing default Device ID ('devid') =%d\n", i);
- }
+ /* A383/A384 are virtual device ID's - not represented as HW device ID values in S@R@0x18600.
+ A383/A384 are configured in SW EEPROM with FULL_FLAVOR field: if false override device ID */
+ if (!(mvCtrlModelGet() == MV_6W22_DEV_ID
+ || mvCtrlModelGet() == MV_6W23_DEV_ID)) { /* 6W22=A383, 6W23=A384 */
+ if (mvBoardSatrInfoConfig(MV_SATR_DEVICE_ID, &satrInfo) == MV_OK) {
+ if (mvBoardSatRWrite(MV_SATR_DEVICE_ID, mvCtrlDevIdIndexGet(mvCtrlModelGet())) == MV_ERROR)
+ mvOsPrintf("Error writing default Device ID ('devid') =%d\n", i);
+ }
+ }
printf("\nSample at Reset values were restored to default.\n");
return 0;
}
@@ -156,23 +207,26 @@
switch (satrInfo->satrId) {
case MV_SATR_CPU_DDR_L2_FREQ:
mvOsPrintf("cpufreq options - Determines the frequency of CPU/DDR/L2:\n\n");
- mvOsPrintf("| ID | CPU Freq (MHz) | L2 Freq (MHz) | SDRAM Freq (MHz) |\n");
- mvOsPrintf("|----|----------------|-----------------|-------------------|\n");
+ mvOsPrintf("| ID | CPU Freq (MHz) | DDR Freq (MHz) | L2 freq(MHz) |\n");
+ mvOsPrintf("|----|----------------|------------------|----------------|\n");
for (i=0; i <= MV_SAR_FREQ_MODES_EOT; i++) {
if (cpuDdrClkTbl[i].id == MV_SAR_FREQ_MODES_EOT)
break;
- if (cpuDdrClkTbl[i].isDisplay)
- mvOsPrintf("| %2d | %4d | %4d | %4d | \n",
+ if (cpuDdrClkTbl[i].isDisplay && isCpuModeSupportedForBoard(i, MV_FALSE) == MV_TRUE)
+ mvOsPrintf("| %2d | %4d | %4d | %4d | \n",
cpuDdrClkTbl[i].id,
cpuDdrClkTbl[i].cpuFreq,
cpuDdrClkTbl[i].ddrFreq,
cpuDdrClkTbl[i].l2Freq);
}
- mvOsPrintf("-------------------------------------------------------------\n");
+ mvOsPrintf("-----------------------------------------------------------\n");
break;
case MV_SATR_CORE_CLK_SELECT:
mvOsPrintf("Determines the Core clock frequency:\n");
- mvOsPrintf("\t0 = 250MHz\n");
+ if (mvCtrlModelGet() == MV_6811_DEV_ID)
+ mvOsPrintf("\t0 = 166MHz\n"); /* device 381/2 (6811/21) use 166MHz instead of 250MHz */
+ else
+ mvOsPrintf("\t0 = 250MHz\n");
mvOsPrintf("\t1 = 200MHz\n");
break;
case MV_SATR_CPU1_ENABLE:
@@ -280,6 +334,27 @@
for (i = 0; i < ARRAY_SIZE(devIdArr); i++)
mvOsPrintf("\t %d = %s\n", i, devIdArr[i]);
break;
+ case MV_SATR_FULL_FLAVOR:
+ mvOsPrintf("Determines whether to use full flavor capabilites:\n");
+ mvOsPrintf("\t0 = Reduced Flavor\n");
+ mvOsPrintf("\t1 = Full Flavor\n ");
+ break;
+ case MV_SATR_TDM_CONNECTED:
+ mvOsPrintf("Indicates whether TDM module is connected or not:\n");
+ mvOsPrintf("\t0 = Connected\n");
+ mvOsPrintf("\t1 = Not connected\n ");
+ break;
+ case MV_SATR_AVS_SKIP:
+ mvOsPrintf("Indicates whether to skip AVS update from EFUSE or not:\n");
+ mvOsPrintf("\t0 = Do not skip AVS update from EFUSE\n");
+ mvOsPrintf("\t1 = Skip AVS update from EFUSE\n");
+ break;
+ case MV_SATR_BOARD_SPEED:
+ mvOsPrintf("Determines the max supported CPU speed:\n");
+ mvOsPrintf("\t1 = %uMHz\n", getBoardSpeed(1));
+ mvOsPrintf("\t2 = %uMHz\n", getBoardSpeed(2));
+ mvOsPrintf("\t3 = %uMHz\n", getBoardSpeed(3));
+ break;
default:
mvOsPrintf("Usage: sar list [options] (see help)\n");
return 1;
@@ -290,6 +365,7 @@
int do_sar_read(MV_U32 mode, MV_BOARD_SATR_INFO *satrInfo)
{
MV_U32 i, tmp;
+ char core_clk_value0[4];
if (mode != CMD_DUMP) {
tmp = mvBoardSatRRead(satrInfo->satrId);
@@ -305,20 +381,22 @@
break;
if (cpuDdrClkTbl[i].id == tmp) {
mvOsPrintf("\nCurrent freq configuration:\n");
- mvOsPrintf("| ID | CPU Freq (MHz) | L2 Freq (MHz) | SDRAM Freq (MHz) |\n");
- mvOsPrintf("|----|----------------|-----------------|-------------------|\n");
- mvOsPrintf("| %2d | %4d | %4d | %4d |\n",
+ mvOsPrintf("| ID | CPU Freq (MHz) | DDR Freq (MHz) | L2 freq(MHz) |\n");
+ mvOsPrintf("|----|----------------|------------------|----------------|\n");
+ mvOsPrintf("| %2d | %4d | %4d | %4d |\n",
cpuDdrClkTbl[i].id,
cpuDdrClkTbl[i].cpuFreq,
cpuDdrClkTbl[i].ddrFreq,
cpuDdrClkTbl[i].l2Freq);
- mvOsPrintf("-------------------------------------------------------------\n");
+ mvOsPrintf("-----------------------------------------------------------\n");
break;
}
}
break;
case MV_SATR_CORE_CLK_SELECT:
- mvOsPrintf("\ncoreclock\t= %d ==> %sMhz\n", tmp, (tmp == 0x0) ? "250" : "200");
+ /* device 381/2 (6811/21) use 166MHz instead of 250MHz */
+ sprintf(core_clk_value0, mvCtrlModelGet() == MV_6811_DEV_ID ? "166" : "250");
+ mvOsPrintf("\ncoreclock\t= %d ==> %sMhz\n", tmp, (tmp == 0x0) ? core_clk_value0 : "200");
break;
case MV_SATR_CPU1_ENABLE:
mvOsPrintf("cpusnum\t\t= %d ==> %s CPU\n", tmp, (tmp == 0) ? "Single" : "Dual");
@@ -380,6 +458,25 @@
case MV_SATR_DEVICE_ID:
mvOsPrintf("devid\t\t= %d ==> Device ID: %s\n", tmp, devIdArr[tmp]);
break;
+ case MV_SATR_FULL_FLAVOR:
+ mvOsPrintf("flavor\t\t= %d ==> %s Flavor", tmp, (tmp == 0) ? "Reduced" : "Full");
+ if (!tmp) {
+ if (mvBoardIdGet() == DB_GP_68XX_ID)
+ mvOsPrintf(" (A384 on DB-GP)");
+ else if (mvBoardIdGet() == DB_BP_6821_ID)
+ mvOsPrintf(" (A383 on DB-88F6821-BP)");
+ }
+ mvOsPrintf("\n");
+ break;
+ case MV_SATR_TDM_CONNECTED:
+ mvOsPrintf("tdm\t\t= %d ==> TDM module is %s\n", tmp, (tmp == 0) ? "connected" : "not connected");
+ break;
+ case MV_SATR_AVS_SKIP:
+ mvOsPrintf("avsskip\t\t= %d ==> %sskip AVS update from EFUSE\n", tmp, (tmp == 0) ? "Do not " : "");
+ break;
+ case MV_SATR_BOARD_SPEED:
+ mvOsPrintf("boardspeed\t\t= %d ==> Max CPU speed is %uMHz\n", tmp, getBoardSpeed(tmp));
+ break;
case CMD_DUMP:
{
MV_BOARD_SATR_INFO satrInfo;
@@ -427,6 +524,11 @@
}
if (satrInfo->satrId == MV_SATR_CPU_DDR_L2_FREQ) {
+ /* DB-6821-BP maximum CPU/DDR frequency mode is 8 : 1332/666 MHz */
+ if (boardId == DB_BP_6821_ID && value > 0x8) {
+ mvOsPrintf("Maximum supported CPU/DDR mode for DB-6821-BP is 0x8\n");
+ return 1;
+ }
freqValueInvalid = 1;
for (i=0; i <= MV_SAR_FREQ_MODES_EOT; i++) {
if (cpuDdrClkTbl[i].id == MV_SAR_FREQ_MODES_EOT)
@@ -441,12 +543,14 @@
mvOsPrintf("Write S@R failed!\n");
return 1;
}
+ if (isCpuModeSupportedForBoard(i, MV_TRUE) == MV_FALSE)
+ return 1;
}
/* verify requested entry is valid and map it's ID value */
if (satrInfo->satrId == MV_SATR_DEVICE_ID) {
- if (value > ARRAY_SIZE(devIdArr)) {
- printf("%s: Error: requested invalid DEVICE_ID value (%x)\n", __func__, value);
+ if (value > ARRAY_SIZE(devIdArr) || value == 2) { /* devid = 2 (6811/21) : not supported via SatR */
+ printf("%s: Error: requested invalid Device ID value (%x)\n", __func__, value);
return 1;
}
}
@@ -460,7 +564,10 @@
if (MV_SATR_BOARD_ID == satrInfo->satrId) {
mvOsPrintf("\nBoard ID update requires new default environment variables.\n");
mvOsPrintf(" Reset environment for %s ? [y/N]" ,marvellBoardInfoTbl[value]->boardName);
- if (mvVerifyRequest() == MV_TRUE)
+ readline(" ");
+ if(strlen(console_buffer) != 0 && /* if pressed Enter */
+ strcmp(console_buffer,"n") != 0 &&
+ strcmp(console_buffer,"N") != 0 )
run_command("resetenv", 0);
}
return 0;
@@ -481,6 +588,16 @@
return 1;
}
+ /* Check if switch is connected to AMC board */
+ if (boardId == DB_AMC_6820_ID) {
+ static SILICON_TYPE silt = SILT_NOT_DETECT;
+
+ if (silt == SILT_NOT_DETECT)
+ silt = get_attached_silicon_type();
+ if (silt == SILT_BC2)
+ return do_sar_bc2(cmdtp, flag, argc, argv);
+ }
+
/* is requested 'SatR read' --> Dump all */
if (argc > 1 && argc < 3 && strcmp(cmd, "read") == 0)
mode = CMD_DUMP;
@@ -552,6 +669,8 @@
"ddr4select - DB-88F6820-BP: DDR3/4 (read only)\n"
"ecoversion - DB-88F6820-BP: ECO version (read only)\n"
"boardid - board ID (read only)\n"
+"boardspeed - MAX validated CPU mode for current chip (read only)\n"
+"avsskip - Skip AVS from EFUSE update\n"
"\n\t Board Specific SW fields\n"
"\t------------------------\n"
@@ -561,7 +680,10 @@
"dbserdes1 - DB-GP, DB-88F6821-BP: SerDes lane #1\n"
"dbserdes2 - DB-GP, DB-88F6821-BP: SerDes lane #2\n"
"usb3port0 - DB-GP, DB-88F6821-BP: USB3-Port0 mode\n"
-"usb3port1 - DB-GP, DB-88F6821-BP: USB3-Port1 mode\n\n"
+"usb3port1 - DB-GP, DB-88F6821-BP: USB3-Port1 mode\n"
+"flavor - DB-GP, DB-88F6821-BP: Is full flavor (for A383/4 simulation)\n"
+"tdm - DB-BP: is TDM module connected\n\n"
+
);
#endif /*defined(CONFIG_CMD_SAR)*/
diff --git a/board/mv_ebu/a38x/cmd_sar39x.c b/board/mv_ebu/a38x/cmd_sar39x.c
index 2710284..a7185e2 100644
--- a/board/mv_ebu/a38x/cmd_sar39x.c
+++ b/board/mv_ebu/a38x/cmd_sar39x.c
@@ -45,12 +45,14 @@
MV_SATR_TYPE_ID satrId;
MV_U32 defauleValueForBoard[MV_MARVELL_BOARD_NUM];
} MV_BOARD_SATR_DEFAULT;
-#define MAX_DEFAULT_ENTRY 2
+#define MAX_DEFAULT_ENTRY 4
MV_BOARD_SATR_DEFAULT boardSatrDefault[MAX_DEFAULT_ENTRY] = {
/* defauleValueForBoard[] = RD_69xx, DB_68xx */
-{ MV_SATR_CPU_DDR_L2_FREQ, {0x0c, 0x0c, } },
-{ MV_SATR_CORE_CLK_SELECT, {0, 0, } },
+{MV_SATR_CPU_DDR_L2_FREQ, {0x0c, 0x0c, } },
+{MV_SATR_CORE_CLK_SELECT, {0, 0, } },
+{MV_SATR_BOOT_DEVICE, {0, 0, } },/* Dummy entry: default value taken from S@R register */
+{MV_SATR_BOOT2_DEVICE, {0, 0, } },/* Dummy entry: default value taken from S@R register */
};
typedef struct _deviceIdEntry {
@@ -65,28 +67,22 @@
{ "6928 (A398)", 0x6928, 0x6 },
};
-MV_BOOL mvVerifyRequest(void)
-{
- readline(" ");
- if(strlen(console_buffer) == 0 || /* if pressed Enter */
- strcmp(console_buffer,"n") == 0 ||
- strcmp(console_buffer,"N") == 0 ) {
- printf("\n");
- return MV_FALSE;
- }
- return MV_TRUE;
-}
-
int do_sar_default(void)
{
MV_U32 i, rc, defaultValue, boardId = mvBoardIdIndexGet(mvBoardIdGet());
MV_SATR_TYPE_ID satrClassId;
MV_BOARD_SATR_INFO satrInfo;
-
+ MV_U32 satrBootDeviceValue = mvCtrlbootSrcGet(), tmp;
for (i = 0; i < MAX_DEFAULT_ENTRY; i++) {
satrClassId = boardSatrDefault[i].satrId;
if (mvBoardSatrInfoConfig(satrClassId, &satrInfo) != MV_OK)
continue;
+ if (satrClassId == MV_SATR_BOOT_DEVICE)
+ boardSatrDefault[i].defauleValueForBoard[boardId] = satrBootDeviceValue & satrInfo.mask;
+ if (satrClassId == MV_SATR_BOOT2_DEVICE) {
+ tmp = satrBootDeviceValue >> MV_SATR_BOOT2_VALUE_OFFSET;
+ boardSatrDefault[i].defauleValueForBoard[boardId] = tmp & MV_SATR_BOOT2_VALUE_MASK;
+ }
defaultValue = boardSatrDefault[i].defauleValueForBoard[boardId];
rc = mvBoardSatRWrite(satrClassId, defaultValue);
if (rc == MV_ERROR) {
diff --git a/board/mv_ebu/a38x/mvSysHwConfig.h b/board/mv_ebu/a38x/mvSysHwConfig.h
index e6f704c..9cdc713 100644
--- a/board/mv_ebu/a38x/mvSysHwConfig.h
+++ b/board/mv_ebu/a38x/mvSysHwConfig.h
@@ -33,6 +33,7 @@
#define MV_INCLUDE_TWSI
#define MV_INCLUDE_UART
#define MV_INCLUDE_TDM
+#define MV_INCLUDE_AUDIO
#define MV_INCLUDE_XOR
#define CONFIG_SATA_AHCI_MV /* shared for u-boot and linux*/
#define MV_INCLUDE_SATA /* only on u-boot */
@@ -40,6 +41,7 @@
#define MV_INCLUDE_RTC
#define MV_INCLUDE_CLK_PWR_CNTRL
+#define MV_INCLUDE_SWITCH
/*
* Board devices
diff --git a/board/mv_ebu/a38x/mv_main_a38x.c b/board/mv_ebu/a38x/mv_main_a38x.c
index 6c1fc3d..5f5f58c 100755
--- a/board/mv_ebu/a38x/mv_main_a38x.c
+++ b/board/mv_ebu/a38x/mv_main_a38x.c
@@ -103,6 +103,11 @@
#include <sdhci.h>
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
#endif
+
+#ifdef CONFIG_SWITCHING_SERVICES
+#include "switchingServices/switchingServices.h"
+#endif
+
/* #define MV_DEBUG */
#ifdef MV_DEBUG
#define DB(x) x
@@ -306,7 +311,6 @@
*(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
mvBoardDebugLed(4);
- mv_print_map();
#if defined(CONFIG_CMD_BOARDCFG)
mvBoardEepromValidSet();
#endif
@@ -319,6 +323,10 @@
char tmp_buf[10];
unsigned int malloc_len;
+ env = getenv("limit_dram_size");
+ if (!env)
+ setenv("limit_dram_size", "yes");
+
env = getenv("console");
if (!env)
setenv("console", "console=ttyS0,115200");
@@ -326,7 +334,7 @@
env = getenv("mtdids");
if (!env) {
#if defined(MV_NAND) && defined(MV_INCLUDE_SPI)
- setenv("mtdids", "nand0=armada-nand;spi0=spi_flash");
+ setenv("mtdids", "nand0=armada-nand,spi0=spi_flash");
#elif defined(MV_NAND)
setenv("mtdids", "nand0=armada-nand");
#elif defined(MV_INCLUDE_SPI)
@@ -336,15 +344,23 @@
env = getenv("mtdparts");
if (!env) {
#if defined(MV_NAND) && defined(MV_INCLUDE_SPI)
- setenv("mtdparts", "'mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);mtdparts=spi_flash:4m(boot),-(spi-rootfs)'");
+ /* Since only AMC board supports both NAND and SPI, and it uses SPI1
+ * "spi1.0" is used in mtdparts instead of "spi0.0" */
+ setenv("mtdparts", "'mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);spi1.0:4m(boot),-(spi-rootfs);"
+ "pxa3xx_nand-0:8m(boot)ro,8m@8m(kernel),-(rootfs)'");
+ setenv("mtdparts_lgcy", "'mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);spi_flash:4m(boot),-(spi-rootfs);"
+ "pxa3xx_nand-0:8m(boot)ro,8m@8m(kernel),-(rootfs)'");
#elif defined(MV_NAND)
- setenv("mtdparts", "mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs)");
+ setenv("mtdparts", "mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);"
+ "pxa3xx_nand-0:8m(boot)ro,8m@8m(kernel),-(rootfs)");
+ setenv("mtdparts_lgcy", getenv("mtdparts"));
#elif defined(MV_INCLUDE_SPI)
#ifdef CONFIG_GFCH100
setenv("mtdparts", "mtdparts=spi_flash:1m(boot),64k@1m(env),-(reserved)");
#else
- setenv("mtdparts", "mtdparts=spi_flash:4m(boot),-(spi-rootfs)");
+ setenv("mtdparts", "mtdparts=spi0.0:4m(boot),-(spi-rootfs)");
#endif
+ setenv("mtdparts_lgcy", "mtdparts=spi_flash:4m(boot),-(spi-rootfs)");
#endif
}
@@ -492,11 +508,11 @@
env = getenv("bootargs_dflt");
if (!env)
#if defined(CONFIG_ARMADA_39X)
- setenv("bootargs_dflt", "$console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
+ setenv("bootargs_dflt", "$console $nandEcc $mtdparts_lgcy $bootargs_root nfsroot=$serverip:$rootpath "
"ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
"clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel $nss_emac_map");
#else
- setenv("bootargs_dflt", "$console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
+ setenv("bootargs_dflt", "$console $nandEcc $mtdparts_lgcy $bootargs_root nfsroot=$serverip:$rootpath "
"ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
"clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel");
#endif
@@ -505,7 +521,11 @@
setenv("bootcmd_auto", "stage_boot $boot_order");
env = getenv("bootcmd_lgcy");
if (!env)
- setenv("bootcmd_lgcy", "tftpboot 0x2000000 $image_name; setenv bootargs $bootargs_dflt; bootm 0x2000000; ");
+ setenv("bootcmd_lgcy", "tftpboot 0x2000000 $image_name;"
+ "setenv bootargs $console $nandEcc $mtdparts_lgcy"
+ " $bootargs_root nfsroot=$serverip:$rootpath "
+ "ip=$ipaddr:$serverip$bootargs_end video=dovefb:lcd0:$lcd0_params "
+ "clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootm $loadaddr; ");
#endif
env = getenv("pxe_files_load");
if (!env)
@@ -530,6 +550,22 @@
setenv("bootargs_debug", "debug=1 login=1 earlyprintk");
#endif
+#ifdef CONFIG_CMD_SOURCE
+ env = getenv("run_script");
+ if (!env)
+ setenv("run_script", "no");
+#endif
+ env = getenv("sd_detection_dat3");
+ if (!env) {
+ /* by default DB-GP is the only marvell board with DAT3 detection method support.
+ This support was added in ECO 1.5 and above, so added env.
+ variable to control detection method according to ECO ver. */
+ if (mvBoardIdGet() == DB_GP_68XX_ID)
+ setenv("sd_detection_dat3", "yes");
+ else
+ setenv("sd_detection_dat3", "no");
+ }
+
/* netbsd boot arguments */
env = getenv("netbsd_en");
if ( !env || ( ((strcmp(env, "no") == 0) || (strcmp(env, "No") == 0) )))
@@ -624,11 +660,7 @@
} else {
env = getenv("bootargs_end");
if (!env)
-#if defined(MV_INC_BOARD_QD_SWITCH)
- setenv("bootargs_end", MV_BOOTARGS_END_SWITCH);
-#else
setenv("bootargs_end", MV_BOOTARGS_END);
-#endif
}
env = getenv("image_name");
@@ -704,9 +736,7 @@
#if (CONFIG_BOOTDELAY >= 0)
env = getenv("bootcmd");
if (!env)
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_LIBFDT_IS_DEFAULT)
- setenv("bootcmd",bootcmd_fdt);
-#elif defined(CONFIG_GFCH100)
+#if defined(CONFIG_GFCH100)
setenv("gfparams",
"if test $HNV_ACTIVATED_KERNEL_NAME = kernel1; "
"then gfkernel=0x9048 gfroot=root=rootfs1; "
@@ -718,42 +748,18 @@
"setenv bootargs $console $mtdparts $gfroot $bootargs_extra; "
"bootm $loadaddr; "
);
-#elif defined(CONFIG_CMD_STAGE_BOOT)
-// setenv("bootcmd","stage_boot $boot_order");
-// Temporary workaround till stage_boot gets stable.
- setenv("bootcmd", "tftpboot 0x2000000 $image_name;"
- "setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
- "ip=$ipaddr:$serverip$bootargs_end video=dovefb:lcd0:$lcd0_params "
- "clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootm $loadaddr; ");
-
-#elif defined(MV_INCLUDE_TDM) || defined(MV_INC_BOARD_QD_SWITCH)
- setenv("bootcmd", "tftpboot 0x2000000 $image_name;"
- "setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
- "ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
- "clcd.lcd0_enable=$(lcd0_enable) clcd.lcd_panel=$lcd_panel; bootm $loadaddr; ");
#else
- setenv("bootcmd", "tftpboot 0x2000000 $image_name;"
- "setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
- "ip=$ipaddr:$serverip$bootargs_end video=dovefb:lcd0:$lcd0_params "
- "clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootm $loadaddr; ");
+ setenv("bootcmd", "tftpboot 0x2000000 $image_name;tftpboot $fdtaddr $fdtfile;"
+ "setenv bootargs $console $nandEcc $mtdparts $bootargs_root nfsroot=$serverip:$rootpath "
+ "ip=$ipaddr:$serverip$bootargs_end $mvNetConfig video=dovefb:lcd0:$lcd0_params "
+ "clcd.lcd0_enable=$lcd0_enable clcd.lcd_panel=$lcd_panel; bootz 0x2000000 - $fdtaddr;");
#endif
#endif /* (CONFIG_BOOTDELAY >= 0) */
env = getenv("standalone");
if (!env)
-#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH)
- setenv("standalone", "fsload 0x2000000 $image_name;setenv bootargs $console $nandEcc $mtdparts "
- "root=/dev/mtdblock0 rw ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000;");
-#elif defined(MV_INC_BOARD_QD_SWITCH)
- setenv("standalone", "fsload 0x2000000 $image_name;setenv bootargs $console $nandEcc $mtdparts "
- "root=/dev/mtdblock0 rw ip=$ipaddr:$serverip$bootargs_end $mvNetConfig; bootm 0x2000000;");
-#elif defined(MV_INCLUDE_TDM)
- setenv("standalone", "fsload 0x2000000 $image_name;setenv bootargs $console $nandEcc $mtdparts "
+ setenv("standalone", "fsload 0x2000000 $image_name;setenv bootargs $console $nandEcc $mtdparts_lgcy "
"root=/dev/mtdblock0 rw ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000;");
-#else
- setenv("standalone", "fsload 0x2000000 $image_name;setenv bootargs $console $nandEcc $mtdparts "
- "root=/dev/mtdblock0 rw ip=$ipaddr:$serverip$bootargs_end; bootm 0x2000000;");
-#endif
/* Set boodelay to 3 sec, if Monitor extension are disabled */
if (!enaMonExt())
@@ -986,6 +992,11 @@
kick_next();
mvBoardDebugLed(0);
+#ifdef CONFIG_SWITCHING_SERVICES
+ /* Some additional tasks maybe required for slave BC2 device, like QSGMII select */
+ if (mvBoardisAmc() && (get_attached_silicon_type() == SILT_BC2))
+ hwServicesLateInit();
+#endif
return 0;
}
@@ -1060,6 +1071,7 @@
int late_print_cpuinfo(void)
{
char name[50];
+ int ddrType = 4;
mvCtrlUpdatePexId();
@@ -1080,9 +1092,12 @@
printf(" CPU @ %d [MHz]\n", mvCpuPclkGet()/1000000);
printf(" L2 @ %d [MHz]\n", mvCpuL2ClkGet()/1000000);
printf(" TClock @ %d [MHz]\n", mvTclkGet()/1000000);
- printf(" DDR @ %d [MHz]\n", CONFIG_SYS_BUS_CLK/1000000);
- printf(" DDR %d Bit Width, %s Memory Access, DLB %s, ECC %s",
- mvCtrlDDRBudWidth(),
+#ifdef CONFIG_DDR3/*DDR3*/
+ ddrType = 3;
+#endif
+ printf(" DDR%d @ %d [MHz]\n", ddrType, CONFIG_SYS_BUS_CLK/1000000);
+ printf(" DDR%d %d Bit Width,%s Memory Access, DLB %s, ECC %s",
+ ddrType, mvCtrlDDRBudWidth(),
mvCtrlDDRThruXbar() ? "XBAR" : "FastPath",
mvCtrlIsDLBEnabled() ? "Enabled" : "Disabled",
mvCtrlDDRECC() ? "Enabled" : "Disabled");
@@ -1124,6 +1139,7 @@
#endif
/* init the units decode windows */
misc_init_r_dec_win();
+ mv_print_map();
memset((void*)CONFIG_SYS_LOAD_ADDR, 0, CONFIG_SYS_MIN_HDR_DEL_SIZE);
mvBoardDebugLed(6);
@@ -1143,13 +1159,20 @@
setenv("pcieTune", "no");
+
+
#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH)
mvBoardEgigaPhyInit();
#endif
#if defined(CONFIG_CMD_DATE)
rtc_init(); /* Ensure the bus bridge parameters are ready for RTC access */
#endif
-
+#ifdef CONFIG_CMD_SOURCE
+ /* run saved script */
+ env = getenv("run_script");
+ if (env && strcmp(env, "yes") == 0)
+ run_command("mvsource run", 0);
+#endif
return 0;
}
diff --git a/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.c
index 827db7c..a4d0307 100644
--- a/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.c
@@ -103,6 +103,32 @@
MV_U32 boardOptionsConfig[MV_CONFIG_TYPE_MAX_OPTION];
/*******************************************************************************
+* mvBoardisUsbPortConnected
+*
+* DESCRIPTION:
+* return True if requested USB type and port num exists on current board
+*
+* INPUT:
+* usbTypeID - requested USB type : USB3_UNIT_ID / USB_UNIT_ID
+* usbPortNumbder - requested USB port number (according to xHCI MAC port num)
+*
+* OUTPUT: None
+*
+* RETURN: MV_TRUE if requested port/type exist on board
+
+*******************************************************************************/
+MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber)
+{
+ /* USB Port board mapping is not supported by Avanta-LP
+ Controller mapping is done via mvCtrlUsbMapGet.*/
+ if (usbPortNumber >= mvCtrlUsbMaxGet())
+ return MV_FALSE;
+ return MV_TRUE;
+}
+
+
+
+/*******************************************************************************
* mvBoardIdIndexGet
*
* DESCRIPTION:
@@ -1702,6 +1728,41 @@
}
/*******************************************************************************
+* mvBoardIsSwitchConnected
+*
+* DESCRIPTION:
+* This routine returns port's connection status, this route provide a unified inerface
+* for other modules to call without care of the switch conntection mode - external or internal
+* if the switch is connected
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 1 - if ethPortNum is connected to switch, 0 otherwise
+*
+*******************************************************************************/
+MV_STATUS mvBoardIsSwitchConnected(void)
+{
+ return mvBoardIsInternalSwitchConnected();
+
+}
+
+/* this temporary functions to compile switch code.
+ mvEthE6171SwitchBasicInit is not used by alp code */
+MV_BOOL mvBoardSwitchCpuPortIsRgmii(MV_U32 switchIdx)
+{
+ return MV_FALSE;
+}
+MV_32 mvBoardSwitchPhyAddrGet(MV_U32 switchIdx)
+{
+ return -1;
+}
+
+/*******************************************************************************
* mvBoardFreqModesNumGet
*
* DESCRIPTION: Return the number of supported frequency modes for this SoC
diff --git a/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.h
index f215473..f67ca3d 100755
--- a/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/alp/avanta_lp_family/boardEnv/mvBoardEnvLib.h
@@ -613,7 +613,10 @@
MV_U8 mvBoardCpuFreqGet(MV_VOID);
MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal);
MV_STATUS mvBoardIsInternalSwitchConnected(void);
+MV_BOOL mvBoardSwitchCpuPortIsRgmii(MV_U32 switchIdx);
+MV_32 mvBoardSwitchPhyAddrGet(MV_U32 switchIdx);
MV_U32 mvBoardSwitchPortForceLinkGet(MV_U32 switchIdx);
+MV_STATUS mvBoardIsSwitchConnected(void);
MV_U32 mvBoardFreqModesNumGet(void);
MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx);
MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum);
@@ -638,6 +641,7 @@
MV_NFC_ECC_MODE mvBoardNandECCModeGet(void);
MV_STATUS mvBoardEepromWriteDefaultCfg(void);
MV_NAND_IF_MODE mvBoardNandIfGet(void);
+MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber);
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.c
index f0a9f1c..581da38 100644
--- a/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.c
@@ -217,6 +217,28 @@
return MV_ERROR;
}
+/******************************************************************************
+* mvCtrlIsUsbSerDesConnected
+*
+* DESCRIPTION:check if SerDes lane is connected to USB3 host.
+*
+*
+* INPUT: None
+*
+* OUTPUT: None
+*
+* RETURN:return true if SerDes lane is connected to USB3 host, false otherwise.
+*
+*
+*******************************************************************************/
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort)
+{
+ int usb3HostNum = mvCtrlUsb3HostMaxGet();
+ int maxSerDesLanes = mvCtrlUsb3MaxGet();
+ if (usbPort >= maxSerDesLanes && usb3HostNum > maxSerDesLanes)
+ return MV_FALSE;
+ return MV_TRUE;
+}
#ifdef MV_INCLUDE_PEX
MV_STATUS mvCtrlUpdatePexId(MV_VOID)
diff --git a/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.h
index 10784cd..a2d51f1 100644
--- a/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/alp/avanta_lp_family/ctrlEnv/mvCtrlEnvLib.h
@@ -265,6 +265,7 @@
MV_STATUS mvCtrlSatRWrite(MV_SATR_TYPE_ID satrReadField, MV_U8 val, MV_BOOL restoreDefault);
MV_STATUS mvCtrlSatRRead(MV_SATR_TYPE_ID satrField, MV_U32 *value);
MV_STATUS mvCtrlCpuDdrL2FreqGet(MV_FREQ_MODE *freqMode);
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort);
MV_VOID mvCtrlSatrInit(MV_VOID);
MV_U32 mvCtrlGetCpuNum(MV_VOID);
MV_BOOL mvCtrlIsSscgEnabled(MV_VOID);
diff --git a/board/mv_ebu/alp/mv_main_alp.c b/board/mv_ebu/alp/mv_main_alp.c
index 7e86320..320969a 100644
--- a/board/mv_ebu/alp/mv_main_alp.c
+++ b/board/mv_ebu/alp/mv_main_alp.c
@@ -302,7 +302,6 @@
*(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
mvBoardDebugLed(4);
- mv_print_map();
return 0;
}
@@ -319,7 +318,7 @@
env = getenv("mtdids");
if (!env) {
#if defined(MV_NAND) && defined(MV_INCLUDE_SPI)
- setenv("mtdids", "nand0=armada-nand;spi0=spi_flash");
+ setenv("mtdids", "nand0=armada-nand,spi0=spi_flash");
#elif defined(MV_NAND)
setenv("mtdids", "nand0=armada-nand");
#elif defined(MV_INCLUDE_SPI)
@@ -495,6 +494,12 @@
if (!env)
setenv("initrd_name", "uInitrd");
+#ifdef CONFIG_CMD_SOURCE
+ env = getenv("run_script");
+ if (!env)
+ setenv("run_script", "no");
+#endif
+
/* netbsd boot arguments */
env = getenv("netbsd_en");
if ( !env || ( ((strcmp(env, "no") == 0) || (strcmp(env, "No") == 0) )))
@@ -1045,6 +1050,7 @@
#if !defined(CONFIG_MACH_AVANTA_LP_FPGA)
/* init the units decode windows */
misc_init_r_dec_win();
+ mv_print_map();
memset((void*)CONFIG_SYS_LOAD_ADDR, 0, CONFIG_SYS_MIN_HDR_DEL_SIZE);
mvBoardDebugLed(6);
@@ -1069,7 +1075,12 @@
mvBoardEgigaPhyInit();
#endif
#endif
-
+#ifdef CONFIG_CMD_SOURCE
+ /* run saved script */
+ env = getenv("run_script");
+ if (env && strcmp(env, "yes") == 0)
+ run_command("mvsource run", 0);
+#endif
return 0;
}
diff --git a/board/mv_ebu/common/Makefile b/board/mv_ebu/common/Makefile
index 9c46bf0..4f68969 100644
--- a/board/mv_ebu/common/Makefile
+++ b/board/mv_ebu/common/Makefile
@@ -17,6 +17,7 @@
MAKE_PPV2 = yes
MAKE_GENERAL_U_BOOT_TOOLS = yes
MAKE_SPI_NAND = yes
+MAKE_SWITCH = yes
endif
ifeq ($(BOARD),a375)
@@ -33,6 +34,10 @@
MAKE_GENERAL_U_BOOT_TOOLS = yes
MAKE_SPI_NAND = yes
MAKE_RTC2 = yes
+ifdef CONFIG_ARMADA_38X
+MAKE_SWITCH_SERVICES = yes
+endif
+MAKE_SWITCH = yes
endif
ifeq ($(BOARD),msys)
@@ -99,6 +104,7 @@
$(USP_DIR)/mv_cmd.o \
$(USP_DIR)/mv_dram.o \
$(USP_DIR)/cmd_bubt.o \
+ $(USP_DIR)/cmd_mvsource.o \
$(USP_DIR)/cmd_resetenv.o \
$(USP_DIR)/mvDramScrubbing.o \
$(USP_DIR)/cmd_ddr.o \
@@ -119,12 +125,13 @@
$(HAL_PP2_CLS_DIR)/mvPp2Classifier.o \
$(HAL_PP2_COMMON_DIR)/mvPp2Common.o \
$(USP_DIR)/mv_egiga_pp2.o
-
-USP_OBJS += $(USP_ETH_SWITCH_DIR)/mvSwitch.o
endif
ifdef MAKE_SWITCH_SERVICES
-USP_OBJS += $(USP_DIR)/switchingServices/switchingServices.o
+USP_OBJS += $(USP_DIR)/switchingServices/switchingServices.o
+ifeq ($(BOARD),a38x)
+USP_OBJS += $(USP_DIR)/switchingServices/sar_bc2.o
+endif
endif
ifdef MAKE_NETA
@@ -135,6 +142,9 @@
$(USP_DIR)/mv_egiga_neta.o
endif
+ifdef MAKE_SWITCH
+USP_OBJS += $(USP_ETH_SWITCH_DIR)/mvSwitch.o
+endif
ifdef MAKE_USB
HAL_IF_OBJS += $(HAL_IF_DIR)/mvSysUsb.o
diff --git a/board/mv_ebu/common/USP/cmd_bubt.c b/board/mv_ebu/common/USP/cmd_bubt.c
index 63852ad..6f76bf1 100755
--- a/board/mv_ebu/common/USP/cmd_bubt.c
+++ b/board/mv_ebu/common/USP/cmd_bubt.c
@@ -31,6 +31,8 @@
#include <fs.h>
+#define DESTINATION_STRING 10
+
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
extern nand_info_t nand_info[]; /* info for NAND chips */
@@ -131,11 +133,13 @@
/*
* Extract arguments from bubt command line
* argc, argv are the input arguments of bubt command line
- * loadfrom is pointer to the extracted argument: from where to load the u-boot bin file
+ * loadfrom is a pointer to the extracted argument: from where to load the u-boot bin file
+ * destination_burn is a pointer to a string which denotes the bubt interface
*/
-MV_STATUS fetch_bubt_cmd_args(int argc, char * const argv[], MV_U32 *loadfrom)
+MV_STATUS fetch_bubt_cmd_args(int argc, char * const argv[], int *loadfrom, char *destination_burn)
{
*loadfrom = 0;
+ strcpy(destination_burn,"default");
/* bubt */
if (argc < 2) {
copy_filename (BootFile, "u-boot.bin", sizeof(BootFile));
@@ -146,6 +150,7 @@
if ((0 == strcmp(argv[1], "spi")) || (0 == strcmp(argv[1], "nand"))
|| (0 == strcmp(argv[1], "nor")))
{
+ strcpy(destination_burn, argv[1]);
copy_filename (BootFile, "u-boot.bin", sizeof(BootFile));
printf("Using default filename \"u-boot.bin\" \n");
}
@@ -159,6 +164,7 @@
if ((0 == strcmp(argv[1], "spi")) || (0 == strcmp(argv[1], "nand"))
|| (0 == strcmp(argv[1], "nor")))
{
+ strcpy(destination_burn, argv[1]);
copy_filename (BootFile, "u-boot.bin", sizeof(BootFile));
printf("Using default filename \"u-boot.bin\" \n");
@@ -174,12 +180,16 @@
}
else
{
+ strcpy(destination_burn, argv[2]);
+
copy_filename (BootFile, argv[1], sizeof(BootFile));
}
}
/* "bubt filename destination source" */
else
{
+ strcpy(destination_burn, argv[2]);
+
copy_filename (BootFile, argv[1], sizeof(BootFile));
if (0 == strcmp("usb", argv[3])) {
@@ -230,20 +240,19 @@
return filesize;
}
-#if defined(MV_NAND_BOOT)
+#if defined(MV_NAND_BOOT) || defined(MV_NAND)
/* Boot from NAND flash */
/* Write u-boot image into the nand flash */
-int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int loadfrom, int argc, char * const argv[])
{
int filesize = 0;
MV_U32 ret = 0;
extern char console_buffer[];
nand_info_t *nand = &nand_info[0];
size_t blocksize = nand_info[0].erasesize;
- size_t env_offset = CONFIG_ENV_OFFSET;
+ size_t env_offset = CONFIG_ENV_OFFSET_NAND;
size_t size = CONFIG_UBOOT_SIZE;
size_t offset = 0;
- MV_U32 loadfrom = 0; /* 0 - from tftp, 1 - from USB */
/* Align U-Boot size to currently used blocksize */
size = ((size + (blocksize - 1)) & (~(blocksize-1)));
@@ -267,9 +276,6 @@
#endif
/* verify requested source is valid */
- if (fetch_bubt_cmd_args(argc, argv, &loadfrom) != MV_OK)
- return 0;
-
if ((filesize = fetch_uboot_file (loadfrom)) <= 0)
return 0;
@@ -284,8 +290,8 @@
strcmp(console_buffer,"yes") == 0 ||
strcmp(console_buffer,"y") == 0 ) {
- printf("Erasing 0x%x - 0x%x:",env_offset, env_offset + CONFIG_ENV_RANGE);
- nand_erase(nand, env_offset, CONFIG_ENV_RANGE);
+ printf("Erasing 0x%x - 0x%x:",env_offset, env_offset + CONFIG_ENV_RANGE_NAND);
+ nand_erase(nand, env_offset, CONFIG_ENV_RANGE_NAND);
printf("\t[Done]\n");
}
@@ -303,27 +309,18 @@
return 1;
}
-U_BOOT_CMD(
- bubt, 4, 1, nand_burn_uboot_cmd,
- "bubt - Burn an image on the Boot Nand Flash.\n",
- "[file-name] [destination [source]] \n"
- "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n"
- "\tdestination is nand, spi or nor.\n"
- "\tsource can be tftp or usb, default is tftp.\n"
-);
#endif /* defined(CONFIG_NAND_BOOT) */
-#if defined(MV_SPI_BOOT)
+#if defined(MV_SPI_BOOT) || defined(MV_INCLUDE_SPI)
/* Boot from SPI flash */
/* Write u-boot image into the SPI flash */
-int spi_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int spi_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int loadfrom, int argc, char * const argv[])
{
int filesize = 0;
MV_U32 ret = 0;
extern char console_buffer[];
load_addr = CONFIG_SYS_LOAD_ADDR;
- MV_U32 loadfrom = 0; /* 0 - from tftp, 1 - from USB */
if(!flash) {
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
@@ -336,9 +333,6 @@
}
/* verify requested source is valid */
- if (fetch_bubt_cmd_args(argc, argv, &loadfrom) != MV_OK)
- return 0;
-
if ((filesize = fetch_uboot_file (loadfrom)) <= 0)
return 0;
@@ -355,17 +349,17 @@
strcmp(console_buffer,"yes") == 0 ||
strcmp(console_buffer,"y") == 0 ) {
- printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE);
- spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
+ printf("Erasing 0x%x - 0x%x:",CONFIG_ENV_OFFSET_SPI, CONFIG_ENV_OFFSET_SPI + CONFIG_ENV_SIZE_SPI);
+ spi_flash_erase(flash, CONFIG_ENV_OFFSET_SPI, CONFIG_ENV_SIZE_SPI);
printf("\t[Done]\n");
}
- if (filesize > CONFIG_ENV_OFFSET)
+ if (filesize > CONFIG_ENV_OFFSET_SPI)
{
printf("Error: Image size (%x) exceeds environment variables offset (%x). ",filesize,CONFIG_ENV_OFFSET);
return 0;
}
- printf("Erasing 0x%x - 0x%x: ",0, 0 + CONFIG_ENV_OFFSET);
- spi_flash_erase(flash, 0, CONFIG_ENV_OFFSET);
+ printf("Erasing 0x%x - 0x%x: ",0, 0 + CONFIG_ENV_OFFSET_SPI);
+ spi_flash_erase(flash, 0, CONFIG_ENV_OFFSET_SPI);
printf("\t\t[Done]\n");
printf("Writing image to flash:");
@@ -384,22 +378,13 @@
return 1;
}
-U_BOOT_CMD(
- bubt, 4, 1, spi_burn_uboot_cmd,
- "bubt - Burn an image on the Boot SPI Flash.\n",
- " file-name \n"
- "[file-name] [destination [source]] \n"
- "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n"
- "\tdestination is nand, spi or nor.\n"
- "\tsource can be tftp or usb, default is tftp.\n"
-);
#endif
-#if defined(MV_NOR_BOOT)
+#if defined(MV_NOR_BOOT) || (MV_INCLUDE_NOR)
/* Boot from Nor flash */
-int nor_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int nor_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int loadfrom, int argc, char * const argv[])
{
int filesize = 0;
MV_U32 ret = 0;
@@ -414,12 +399,8 @@
// s_end = flash_in_which_sec(&flash_info[0], CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN -1);
// env_sec = flash_in_which_sec(&flash_info[0], CONFIG_ENV_ADDR);
- MV_U32 loadfrom = 0; /* 0 - from tftp, 1 - from USB */
/* verify requested source is valid */
- if (fetch_bubt_cmd_args(argc, argv, &loadfrom) != MV_OK)
- return 0;
-
if ((filesize = fetch_uboot_file (loadfrom)) <= 0)
return 0;
@@ -463,27 +444,17 @@
return 1;
}
-U_BOOT_CMD(
- bubt, 4, 1, nor_burn_uboot_cmd,
- "bubt - Burn an image on the Boot Flash.\n",
- " file-name \n"
- "[file-name] [destination [source]] \n"
- "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n"
- "\tdestination is nand, spi or nor.\n"
- "\tsource can be tftp or usb, default is tftp.\n"
-);
#endif /* MV_NOR_BOOT */
#if defined(MV_MMC_BOOT)
/* Boot from SD/MMC/eMMC */
/* Write u-boot image into SD/MMC/eMMC device */
-int mmc_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int mmc_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int loadfrom, int argc, char * const argv[])
{
int filesize = 0;
extern char console_buffer[];
load_addr = CONFIG_SYS_LOAD_ADDR;
- MV_U32 loadfrom = 0; /* 0 - from tftp, 1 - from USB */
lbaint_t start_lba;
lbaint_t blk_count;
ulong blk_written;
@@ -514,9 +485,6 @@
#endif
/* verify requested source is valid */
- if (fetch_bubt_cmd_args(argc, argv, &loadfrom) != MV_OK)
- return 0;
-
if ((filesize = fetch_uboot_file (loadfrom)) <= 0)
return 0;
@@ -565,12 +533,76 @@
return 1;
}
+#endif
+
+int burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char destination_burn[DESTINATION_STRING];
+ int loadfrom = 0; /* 0 - from tftp, 1 - from USB */
+
+ memset(destination_burn, '\0', sizeof(destination_burn));
+
+ if(fetch_bubt_cmd_args(argc, argv, &loadfrom,destination_burn) != MV_OK)
+ return 0;
+
+#if defined(MV_CROSS_FLASH_BOOT)
+ if (0 == strcmp(destination_burn, "nand")) {
+#if defined(MV_NAND) || defined(MV_NAND_BOOT)
+ return nand_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+ printf("\t[FAIL] - u-boot does not support a write to %s interface.\n",destination_burn);
+ return 0;
+ }
+
+ if (0 == strcmp(destination_burn, "spi")) {
+#if defined(MV_INCLUDE_SPI) || defined (MV_SPI_BOOT)
+ return spi_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+ printf("\t[FAIL] - u-boot does not support a write to %s interface.\n",destination_burn);
+ return 0;
+ }
+
+ if (0 == strcmp(destination_burn, "nor")) {
+#if defined(MV_INCLUDE_NOR) || defined (MV_NOR_BOOT)
+ return nor_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+ printf("\t[FAIL] - u-boot does not support a write to %s interface.\n",destination_burn);
+ return 0;
+ }
+#endif
+
+#if defined(MV_NAND_BOOT)
+ return nand_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+#if defined(MV_SPI_BOOT)
+ return spi_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+#if defined(MV_NOR_BOOT)
+ return nor_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+#if defined(MV_MMC_BOOT)
+ return mmc_burn_uboot_cmd(cmdtp, flag, loadfrom, argc, argv);
+#endif
+
+ return 1;
+}
+
+#if defined(MV_MMC_BOOT)
U_BOOT_CMD(
- bubt, 3, 1, mmc_burn_uboot_cmd,
- "bubt - Burn an image on the Boot SD/MMC/eMMC device.\n",
+ bubt, 3, 0, burn_uboot_cmd,
+ "bubt - Burn an image on the Boot device.\n",
" file-name \n"
"[file-name] [source] \n"
"\tBurn a binary image on the Boot Device, default file-name is u-boot.bin .\n"
"\tsource can be tftp or usb, default is tftp.\n"
);
+#else
+U_BOOT_CMD(
+ bubt, 4, 0, burn_uboot_cmd,
+ "bubt - Burn an image on the Boot flash device.\n",
+ "[file-name] [destination [source]] \n"
+ "\tBurn a binary image on the Boot Device, default file-name is u-boot.bin .\n"
+ "\tsource can be tftp or usb, default is tftp.\n"
+ "\texample: bubt u-boot.bin nand tftp\n"
+ );
#endif
diff --git a/board/mv_ebu/common/USP/cmd_mvsource.c b/board/mv_ebu/common/USP/cmd_mvsource.c
new file mode 100644
index 0000000..70502b0
--- /dev/null
+++ b/board/mv_ebu/common/USP/cmd_mvsource.c
@@ -0,0 +1,538 @@
+#include <config.h>
+#include <common.h>
+#include "mvCommon.h"
+#include <command.h>
+#include <net.h>
+#include <environment.h>
+
+#ifdef CONFIG_CMD_SOURCE
+#if defined(MV_INCLUDE_USB)
+#include <usb.h>
+#endif
+
+#include <fs.h>
+
+#define DESTINATION_STRING 10
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+extern nand_info_t nand_info[]; /* info for NAND chips */
+#endif
+
+#ifdef CONFIG_CMD_SF
+#include <spi_flash.h>
+extern struct spi_flash *flash;
+#endif
+
+#ifdef CONFIG_CMD_FLASH
+#include <flash.h>
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+#endif
+
+#include <image.h>
+#include <malloc.h>
+
+int dest_flash; /* destination flash to burn the script (0 = SPI, 1 = NAND) */
+
+#ifdef MV_INCLUDE_USB
+/*******************************************************************************
+* load_from_usb
+*
+* DESCRIPTION:
+* Load script file from usb device
+*
+* INPUT:
+* file_name - img file name.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* - file size on success
+* - 0, otherwise
+*
+*******************************************************************************/
+static int load_from_usb(const char *file_name)
+{
+ const char *addr_str;
+ unsigned long addr;
+ int filesize = 0;
+
+ usb_stop();
+ printf("(Re)start USB...\n");
+
+ if (usb_init() < 0) {
+ printf("usb_init failed\n");
+ return 0;
+ }
+
+ /* try to recognize storage devices immediately */
+ /* the parameter '1', tells the function to reports to the
+ * user while scanning for device */
+ if (-1 == usb_stor_scan(1)) {
+ printf("USB storage device not found\n");
+ return 0;
+ }
+
+ /* always load from usb 0 */
+ if (fs_set_blk_dev("usb", "0", FS_TYPE_ANY)) {
+ printf("USB 0 not found\n");
+ return 0;
+ }
+
+ addr_str = getenv("loadaddr");
+ if (addr_str != NULL)
+ addr = simple_strtoul(addr_str, NULL, 16);
+ else
+ addr = CONFIG_SYS_LOAD_ADDR;
+
+ filesize = fs_read(file_name, addr, 0, 0);
+ return filesize;
+}
+#endif
+
+/*******************************************************************************
+* fetch_script_file
+*
+* DESCRIPTION:
+* Load script file into ram from external device: tftp, usb
+*
+* INPUT:
+* loadfrom - specifies the source device:
+* 0 - TFTP, 1 - USB
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* - file size on success
+* - 0, otherwise
+*
+*******************************************************************************/
+static int fetch_script_file(int loadfrom)
+{
+ int filesize = 0;
+ switch (loadfrom) {
+#ifdef MV_INCLUDE_USB
+ case 1:
+ filesize = load_from_usb(BootFile);
+ if (filesize <= 0) {
+ printf("Failed to read file %s\n", BootFile);
+ return 0;
+ }
+ break;
+#endif
+ case 0:
+ filesize = NetLoop(TFTPGET);
+ printf("Checking file size:");
+ if (filesize == -1) {
+ printf("\t[Fail]\n");
+ return 0;
+ }
+ break;
+ default:
+ return 0;
+ }
+
+ return filesize;
+}
+
+/*******************************************************************************
+* fetch_mvsource_cmd_args
+*
+* DESCRIPTION:
+* fetch command arguments from argv and return them in variables
+*
+* INPUT:
+* argc - command arguments' number
+* argv - command arguments' values
+*
+* OUTPUT:
+* command - command to run (0 = burn, 1 = run)
+* offset - offset in flash to burn the script
+* loadfrom - source interface (0 = TFTP, 1 = USB)
+* dest - destination flash if multiple flashes supported
+* (0 = SPI, 1 = NAND)
+*
+* RETURN:
+* - MV_OK on success
+* - MV_FAIL, otherwise
+*
+*******************************************************************************/
+static MV_STATUS fetch_mvsource_cmd_args(int argc, char * const argv[],
+ int *command, MV_U32 *offset, int *loadfrom, int *dest) {
+ int i;
+ const char *default_name = "script.img";
+
+ *command = -1; /* 0 = burn; 1 = run; -1 = invalid command */
+ *offset = 0x300000;
+ *loadfrom = 0; /* 0 = TFTP; 1 = USB */
+ *dest = 0; /* 0 = SPI; 1 = NAND */
+
+ /* fetch destination interface (if exists), else use SPI as default */
+ for (i = 0; i < argc; ++i) {
+ if (strcmp(argv[i], "spi") == 0) {
+ *dest = 0;
+ argc--;
+ break;
+ } else if (strcmp(argv[i], "nand") == 0) {
+ *dest = 1;
+ argc--;
+ break;
+ }
+ }
+
+ if (argc < 2) { /* empty command is unacceptable */
+ printf("Error: too few arguments\n");
+ return MV_FAIL;
+ }
+
+ /* skip main command name */
+ argc--;
+ argv++;
+ if (strcmp(argv[0], "burn") == 0) {
+ *command = 0;
+ /* only burn command have filename as 1st parameter */
+ if (argc > 1) {
+ strncpy(BootFile, argv[1], strlen(argv[1]));
+ argc--;
+ argv++;
+ } else {
+ strncpy(BootFile, default_name, strlen(default_name));
+ printf("using default filename \"%s\"\n", default_name);
+ }
+ } else if (strcmp(argv[0], "run") == 0)
+ *command = 1;
+ else {
+ printf("Error: unknown command\n");
+ return MV_FAIL;
+ }
+
+ /* skip internal command name ('burn' or 'run') */
+ argc--;
+ argv++;
+ switch (argc) {
+ case 2:
+ if (strcmp(argv[1], "tftp") == 0)
+ *loadfrom = 0;
+ else if (strcmp(argv[1], "usb") == 0)
+ *loadfrom = 1;
+ else
+ return MV_FAIL;
+ case 1:
+ *offset = simple_strtoul(argv[0], NULL, 16);
+ default:
+ break;
+ }
+ return MV_OK;
+}
+
+#if defined(MV_INCLUDE_SPI)
+/*******************************************************************************
+* init_spi
+*
+* DESCRIPTION:
+* init spi flash if not initiated
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 0 on success
+* -1 otherwise
+*
+*******************************************************************************/
+static int init_spi(void){
+ if (!flash) {
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+ if (!flash) {
+ printf("Failed to probe SPI Flash\n");
+ return -1;
+ }
+ }
+ return 0;
+}
+
+/*******************************************************************************
+* spi_burn_script
+*
+* DESCRIPTION:
+* burn script image to the SPI flash
+*
+* INPUT:
+* offset - offset in flash to burn the script
+* loadfrom - source interface to fetch the file (0 = TFTP, 1 = USB)
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static void spi_burn_script(MV_U32 offset, int loadfrom)
+{
+ int filesize = 0;
+ MV_U32 ret = 0;
+ load_addr = CONFIG_SYS_LOAD_ADDR;
+ u32 sector_size, aligned_size;
+
+ if (init_spi())
+ return;
+
+ sector_size = flash->sector_size;
+
+ /* verify requested source is valid */
+ filesize = fetch_script_file(loadfrom);
+ if (filesize <= 0)
+ return;
+
+ aligned_size = ((filesize + (sector_size - 1)) & (~(sector_size - 1)));
+ printf("Erasing 0x%x - 0x%x: ", offset, offset + aligned_size);
+ spi_flash_erase(flash, offset, aligned_size);
+ printf("\t\t[Done]\n");
+
+ printf("Writing image to flash:");
+ ret = spi_flash_write(flash, offset, filesize, (const void *)load_addr);
+
+ if (ret)
+ printf("\t\t[Err!]\n");
+ else
+ printf("\t\t[Done]\n");
+}
+#endif /* MV_INCLUDE_SPI */
+
+#if defined(MV_NAND)
+/*******************************************************************************
+* spi_burn_script
+*
+* DESCRIPTION:
+* burn script image to the NAND flash
+*
+* INPUT:
+* offset - offset in flash to burn the script
+* loadfrom - source interface to fetch the file (0 = TFTP, 1 = USB)
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static void nand_burn_script(MV_U32 offset, int loadfrom)
+{
+ int filesize = 0;
+ MV_U32 ret = 0, aligned_size;
+ nand_info_t *nand = &nand_info[0];
+ size_t erasesize = nand_info[0].erasesize;
+
+ if (nand_block_isbad(&nand_info[0], offset)) {
+ printf("Failed to burn: Bad block at offset %X\n", offset);
+ return;
+ }
+
+ /* verify requested source is valid */
+ filesize = fetch_script_file(loadfrom);
+ if (filesize <= 0)
+ return;
+
+ aligned_size = ((filesize + (erasesize - 1)) & (~(erasesize - 1)));
+ printf("\t[Done]\n");
+ printf("Erasing 0x%x - 0x%x: ", offset, offset + aligned_size);
+ nand_erase(nand, offset, aligned_size);
+ printf("\t[Done]\n");
+
+ printf("Writing image to NAND:");
+ ret = nand_write(nand, offset, (size_t *)&filesize, (u_char *)load_addr);
+ if (ret)
+ printf("\t[Fail]\n");
+ else
+ printf("\t[Done]\n");
+}
+#endif /* defined(MV_NAND) */
+
+/*******************************************************************************
+* is_magic_valid
+*
+* DESCRIPTION:
+* checks if the magic value in script header is valid
+*
+* INPUT:
+* header - script header
+*
+* RETURN:
+* MV_TRUE if magic value in header is valid
+* MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_BOOL is_magic_valid(image_header_t *header)
+{
+ /* check if image type is IMAGE_FORMAT_LEGACY */
+ if (be32_to_cpu(header->ih_magic) != IH_MAGIC)
+ return MV_FALSE;
+
+ return MV_TRUE;
+}
+
+/*******************************************************************************
+* get_image_size
+*
+* DESCRIPTION:
+* fetch script size (in bytes) from script header
+*
+* INPUT:
+* offset - script offset in flash
+*
+* OUTPUT:
+* size - script size (in bytes)
+*
+* RETURN:
+* MV_OK on success fetching the size
+* MV_FAIL otherwise
+*
+*******************************************************************************/
+MV_STATUS get_image_size(MV_U32 offset, MV_U32 *size)
+{
+ size_t buff_size = sizeof(image_header_t);
+ image_header_t header;
+#if defined(MV_INCLUDE_SPI)
+ if (init_spi())
+ return MV_FAIL;
+#endif
+#if defined(MV_INCLUDE_SPI) && defined(MV_NAND)
+ if (dest_flash == 0)
+ spi_flash_read(flash, offset, buff_size , &header);
+ else if (dest_flash == 1)
+ nand_read(&nand_info[0], offset, &buff_size, (u_char *)&header);
+#elif defined(MV_INCLUDE_SPI)
+ spi_flash_read(flash, offset, buff_size , &header);
+#elif defined(MV_NAND)
+ nand_read(&nand_info[0], offset, &buff_size, (u_char *)&header);
+#else
+ return MV_FAIL;
+#endif
+ if (is_magic_valid(&header) == MV_FALSE)
+ return MV_FAIL;
+
+ *size = be32_to_cpu(header.ih_size) + sizeof(image_header_t);
+ return MV_OK;
+}
+
+/*******************************************************************************
+* get_block_size
+*
+* DESCRIPTION:
+* get block size of flash
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* block size, on success
+* 0, otherwise
+*
+*******************************************************************************/
+MV_U32 get_block_size(void)
+{
+#if defined(MV_INCLUDE_SPI) && defined(MV_NAND)
+ if (dest_flash == 0)
+ return flash->sector_size;
+ else if (dest_flash == 1)
+ return nand_info[0].erasesize;
+ else
+ return 0;
+#elif defined(MV_INCLUDE_SPI)
+ return flash->sector_size;
+
+#elif defined(MV_NAND)
+ return nand_info[0].erasesize;
+#else
+ return 0;
+#endif
+}
+
+int mvsource_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int command, loadfrom;
+ MV_U32 offset;
+ char *buffer;
+ char buffer_address_str[30]; /* to pass to 'source' argument */
+ MV_U32 size;
+ char *source_argv[2];
+
+ if (fetch_mvsource_cmd_args(argc, argv, &command,
+ &offset, &loadfrom, &dest_flash) != MV_OK)
+ return 1;
+
+
+ if (command == 0) { /* 0 = burn */
+#if defined(MV_INCLUDE_SPI) && defined(MV_NAND)
+ if (dest_flash == 0)
+ spi_burn_script(offset, loadfrom);
+ else if (dest_flash == 1)
+ nand_burn_script(offset, loadfrom);
+#elif defined(MV_INCLUDE_SPI)
+ spi_burn_script(offset, loadfrom);
+#elif defined(MV_NAND)
+ nand_burn_script(offset, loadfrom);
+#endif
+ } else if (command == 1) { /* 1 = run */
+ if (get_image_size(offset, &size) != MV_OK) {
+ printf("Error: Failed to fetch script size\n");
+ return 1;
+ } else {
+ buffer = (char *)malloc(size);
+ if (!buffer) {
+ printf("Error: Failed to allocate memory\n");
+ return 1;
+ }
+ }
+#if defined(MV_INCLUDE_SPI) && defined(MV_NAND)
+ if (dest_flash == 0)
+ spi_flash_read(flash, offset, size , buffer);
+ else if (dest_flash == 1)
+ nand_read(&nand_info[0], offset, &size, (u_char *)buffer);
+#elif defined(MV_INCLUDE_SPI)
+ spi_flash_read(flash, offset, size , buffer);
+#elif defined(MV_NAND)
+ nand_read(&nand_info[0], offset, &size, (u_char *)buffer);
+#else
+ return 1;
+#endif
+ sprintf(buffer_address_str, "%lx", (unsigned long)buffer);
+ source_argv[0] = "source";
+ source_argv[1] = buffer_address_str;
+ do_source(cmdtp, 0, 2, source_argv);
+ free(buffer);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(
+ mvsource, 5, 1, mvsource_cmd,
+ "mvsource - Burn a script image on flash device.\n",
+ "burn [file-name [offset [src_interface]]] [dst_flash]"
+ "\n\tBurn script <file-name> to flash at <offset> from <src_interface> \n"
+ "mvsource run [offset]"
+ "\n\tRun script from flash at <offset>\n"
+ "\nArguments (optional):\n"
+ "\t- file-name: script file name\t\t\t(default = script.bin)\n"
+ "\t- offset: script address in flash\t\t(default = 300000)\n"
+ "\t- src_interface: script source: tftp/usb\t(default = tftp)\n"
+ "\t- dst_flash: flash destination: spi/nand\t(default = spi)\n"
+ "Examples:\n"
+ "\tmvsource burn script.img 300000 tftp spi\n"
+ "\tmvsource burn\n"
+ "\tmvsource run 300000\n"
+ "\tmvsource run\n"
+ );
+
+#endif /* CONFIG_CMD_SOURCE */
diff --git a/board/mv_ebu/common/USP/ethSwitch/mvSwitch.c b/board/mv_ebu/common/USP/ethSwitch/mvSwitch.c
old mode 100755
new mode 100644
index 77af2ea..1b8477a
--- a/board/mv_ebu/common/USP/ethSwitch/mvSwitch.c
+++ b/board/mv_ebu/common/USP/ethSwitch/mvSwitch.c
@@ -69,12 +69,13 @@
#include "mvCtrlEnvLib.h"
#include "mvBoardEnvLib.h"
-
static void switchVlanInit(MV_U32 ethPortNum,
MV_U32 switchCpuPort,
MV_U32 switchMaxPortsNum,
MV_U32 switchPortsOffset,
MV_U32 switchEnabledPortsMask);
+static MV_U16 mvEthSwitchGetDeviceIDInMultiorManualMode(void);
+static MV_U16 mvEthSwitchGetDeviceIDInAutoScanMode(MV_BOOL *highSmiDevAddr);
void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 phyAddr,
MV_U32 regOffs, MV_U16 data);
@@ -84,6 +85,254 @@
int switchMultiChipMode = 0xdeadbeef;
+static MV_32 switchDeviceID = -1; /*-1 : initialized, 0 : no switch, other values are switch device ID*/
+static MV_U32 switchAccessMode = SMI_MANUAL_MODE;
+#ifdef MV_SWITCH_SMI_ACCESS
+static MV_32 switchPhyAddr = -1;
+#endif
+
+/*******************************************************************************
+* mvEthSwitchGetDeviceIDInMultiAddMode -
+*
+* DESCRIPTION:
+* get switch device ID if switch is in SMI muti address access mode
+*
+* INPUT:
+* None
+*
+* OUTPUT:
+* None
+*
+* RETURN: switch device ID
+*
+*******************************************************************************/
+static MV_U16 mvEthSwitchGetDeviceIDInMultiorManualMode(void)
+{
+ MV_U16 data;
+
+ /*read switch device ID, first try the case that port register offset is 8*/
+ data = 0;
+ mvEthSwitchRegRead(0, PORT_REGS_START_ADDR, QD_REG_SWITCH_ID, &data);
+
+ switch (data & 0xFF00) {
+ case 0x0200:
+ case 0x0300:
+ case 0x0500:
+ case 0x0600:
+ case 0x1500:
+ case 0xF500:
+ case 0xF900:
+ case 0x0700: /* Spinnaker */
+ case 0x2200: /* Spinnaker */
+ case 0x2500: /* Spinnaker */
+ return data;
+ case 0xC000: /* Melody, Now it could be 0xc00 - 0xc07 */
+ return data&0xFF0F;
+ default:
+ break;
+ }
+
+ /*read switch device ID, second try the case that port register offset is 0x10*/
+ data = 0;
+ mvEthSwitchRegRead(0, PORT_REGS_START_ADDR_8PORT, QD_REG_SWITCH_ID, &data);
+
+ switch (data & 0xFF00) {
+ case 0x0800:
+ case 0x1A00:
+ case 0x1000:
+ case 0x0900:
+ case 0x0400:
+ case 0x1200:
+ case 0x1400:
+ case 0x1600:
+ case 0x3200:
+ case 0x1700:
+ case 0x3700:
+ case 0x2400: /* Agate */
+ case 0x3500: /* Agate */
+ case 0x1100: /* Pearl */
+ case 0x3100: /* Pearl */
+ case 0xc100: /* ALP Fix */
+ return data;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/*******************************************************************************
+* mvEthSwitchGetDevIDByPortRegStartInAuto -
+*
+* DESCRIPTION:
+* get switch device ID by the switch port register start address if switch is in SMI auto scan access mode
+*
+* INPUT:
+* portRegsStartAddr - switch port register start address
+*
+* OUTPUT:
+* None
+*
+* RETURN: switch device ID
+*
+*******************************************************************************/
+static MV_U16 mvEthSwitchGetDevIDByPortRegStartInAuto(MV_U32 portRegsStartAddr)
+{
+ MV_U16 data, data1;
+
+ /*read switch device ID from switch port 0 and 1, if the 2 values are equal and meaningful, then it's valid*/
+ data = 0;
+ mvEthSwitchRegRead(0, portRegsStartAddr, QD_REG_SWITCH_ID, &data);
+ data1 = 0;
+ mvEthSwitchRegRead(0, portRegsStartAddr + 1, QD_REG_SWITCH_ID, &data1);
+
+ switch (data & 0xFF00) {
+ case 0x0200:
+ case 0x0300:
+ case 0x0500:
+ case 0x0600:
+ case 0x1500:
+ case 0xC000: /* Melody */
+ case 0x0700: /* Spinnaker */
+ case 0x2200: /* Spinnaker */
+ case 0x2500: /* Spinnaker */
+ case 0xF500:
+ case 0xF900:
+ if (data == data1)
+ return data;
+ default:
+ break;
+ }
+
+ return 0;
+
+}
+
+/*******************************************************************************
+* mvEthSwitchGetDeviceIDInAutoScanMode -
+*
+* DESCRIPTION:
+* get switch device ID if switch is in SMI auto scan access mode
+*
+* INPUT:
+* None
+*
+* OUTPUT:
+* highSmiDevAddr - whether high SMI device address is used
+*
+* RETURN: switch device ID
+*
+*******************************************************************************/
+static MV_U16 mvEthSwitchGetDeviceIDInAutoScanMode(MV_BOOL *highSmiDevAddr)
+{
+ MV_U16 data, data1;
+
+ /*read switch device ID, first try the case that port register offset is 8*/
+ data = mvEthSwitchGetDevIDByPortRegStartInAuto(PORT_REGS_START_ADDR);
+ if (data != 0) {
+ *highSmiDevAddr = MV_FALSE;
+ return data;
+ }
+
+ /*read switch device ID, second try the case that port register offset is 0x18*/
+ data = mvEthSwitchGetDevIDByPortRegStartInAuto(PORT_REGS_START_ADDR + 0x10);
+ if (data != 0) {
+ *highSmiDevAddr = MV_TRUE;
+ return data;
+ }
+
+ /*read switch device ID, finally try the case that port register offset is 0x10*/
+ data = 0;
+ mvEthSwitchRegRead(0, PORT_REGS_START_ADDR_8PORT, QD_REG_SWITCH_ID, &data);
+ data1 = 0;
+ mvEthSwitchRegRead(0, PORT_REGS_START_ADDR_8PORT + 1, QD_REG_SWITCH_ID, &data1);
+
+ switch (data & 0xFF00) {
+ case 0x0800:
+ case 0x1A00:
+ case 0x1000:
+ case 0x0900:
+ case 0x0400:
+ case 0x1200:
+ case 0x1400:
+ case 0x1600:
+ case 0x1700:
+ case 0x3200:
+ case 0x3700:
+ case 0x2400: /* Agate */
+ case 0x3500: /* Agate */
+ case 0x1100: /* Pearl */
+ case 0x3100: /* Pearl */
+ if (data == data1) {
+ *highSmiDevAddr = MV_FALSE;
+ return data;
+ }
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+
+/*******************************************************************************
+* mvEthSwitchGetDeviceID -
+*
+* DESCRIPTION:
+* If switch device ID is not initialized, then detect switch device, find out switch device ID,
+* access mode and PHY address, otherwise return switch device ID directly
+*
+* INPUT:
+* None
+*
+* OUTPUT:
+* highSmiDevAddr - Indicates whether to use the high device register
+* addresses when accessing switch's registers (of all kinds)
+* i.e, the devices registers range is 0x10 to 0x1F, or to
+* use the low device register addresses (range 0x0 to 0xF).
+* GT_TRUE - use high addresses (0x10 to 0x1F).
+* GT_FALSE - use low addresses (0x0 to 0xF).
+*
+* RETURN: switch device ID, 0 means no switch detected
+*
+*******************************************************************************/
+MV_U16 mvEthSwitchGetDeviceID(void)
+{
+ MV_BOOL highSmiDevAddr;
+
+ /*if switchDeviceID has been initialized, then return it directly*/
+ if (switchDeviceID >= 0)
+ return (MV_U16)switchDeviceID;
+
+ /*if switch module is not detected, then reurn 0 - no switch detected*/
+ if (mvBoardIsSwitchConnected() == MV_FALSE) {
+ switchDeviceID = 0;
+ return (MV_U16)switchDeviceID;
+ }
+
+ switchAccessMode = mvBoardSmiScanModeGet(0);
+#ifdef MV_SWITCH_SMI_ACCESS
+ switchPhyAddr = mvBoardSwitchPhyAddrGet(0);
+ if ((switchPhyAddr == -1) && (switchAccessMode == SMI_MANUAL_MODE)) {
+ mvOsPrintf("switchPhyAddr value %d is error!\n", switchPhyAddr);
+ switchDeviceID = 0;
+ return switchDeviceID;
+ }
+#endif
+
+ if (switchAccessMode == SMI_MULTI_ADDR_MODE || switchAccessMode == SMI_MANUAL_MODE) {
+ switchDeviceID = mvEthSwitchGetDeviceIDInMultiorManualMode();
+ return (MV_U16)switchDeviceID;
+ } else if (switchAccessMode == SMI_AUTO_SCAN_MODE) {
+ switchDeviceID = mvEthSwitchGetDeviceIDInAutoScanMode(&highSmiDevAddr);
+ return (MV_U16)switchDeviceID;
+ } else {
+ switchDeviceID = 0;
+ return (MV_U16)switchDeviceID;
+ }
+}
+
+
/*******************************************************************************
* mvEthE6065_61PhyBasicInit -
*
@@ -298,31 +547,43 @@
}
#endif /* MV88F66XX */
+/* This initial function is valid for E6176 switch */
MV_VOID mvEthE6171SwitchBasicInit(MV_U32 ethPortNum)
{
MV_U32 prt;
MV_U16 reg;
volatile MV_U32 timeout;
- MV_32 cpuPort = mvBoardSwitchCpuPortGet(0);
+ MV_U32 cpuPort = mvBoardSwitchCpuPortGet(0);
+ MV_U32 swicthPhyAddr = mvBoardSwitchPhyAddrGet(0);
/* The 6171 needs a delay */
mvOsDelay(1000);
/* Init vlan of switch 1 and enable all ports */
- switchVlanInit(ethPortNum, MV_E6171_CPU_PORT, MV_E6171_MAX_PORTS_NUM, MV_E6171_PORTS_OFFSET,
- MV_E6171_ENABLED_PORTS);
+ switchVlanInit(ethPortNum, cpuPort, MV_E6171_MAX_PORTS_NUM, swicthPhyAddr, MV_E6171_ENABLED_PORTS);
- /* Enable RGMII delay on Tx and Rx for port 5 switch 1 */
- mvEthSwitchRegRead(ethPortNum, MV_E6171_PORTS_OFFSET + cpuPort, MV_E6171_SWITCH_PHIYSICAL_CTRL_REG, ®);
- mvEthSwitchRegWrite(ethPortNum, MV_E6171_PORTS_OFFSET + cpuPort, MV_E6171_SWITCH_PHIYSICAL_CTRL_REG,
- (reg|0xC000));
+ if (mvBoardSwitchCpuPortIsRgmii(0)) {
+ /* Enable RGMII delay on Tx and Rx for port 5 switch 1 */
+ mvEthSwitchRegRead(ethPortNum, swicthPhyAddr + cpuPort, MV_E6171_SWITCH_PHIYSICAL_CTRL_REG, ®);
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr + cpuPort, MV_E6171_SWITCH_PHIYSICAL_CTRL_REG,
+ (reg|0xC000));
+ } else {
+ /* If the CPU port is not connected to RGMII, so it connected
+ to SGMII via SerDes lane, this code power-up the SerDes in switch */
+ /* Change to page #1 to access SerDes control register */
+ mvEthSwitchPhyRegWrite(ethPortNum, MV_E6171_SERDES_REG, MV_E6171_PAGE_REG, BIT0);
+ /* Read SerDes power down status of the switch */
+ mvEthSwitchPhyRegRead(ethPortNum, MV_E6171_SERDES_REG, MV_E6171_SERDES_CONTROL_REG, ®);
+ /* Clear Bit 11 to power up the switch SerDes */
+ reg &= ~BIT11;
+ mvEthSwitchPhyRegWrite(ethPortNum, MV_E6171_SERDES_REG, MV_E6171_SERDES_CONTROL_REG, reg);
+ }
/* Power up PHYs */
- for(prt=0; prt < MV_E6171_MAX_PORTS_NUM - 2; prt++) {
- if (prt != MV_E6171_CPU_PORT) {
+ for (prt = 0; prt < MV_E6171_MAX_PORTS_NUM - 2; prt++) {
+ if (prt != cpuPort) {
/*Enable Phy power up for switch 1*/
- mvEthSwitchRegWrite(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR,
- MV_E6171_SMI_PHY_DATA, 0x3360);
+ mvEthSwitchRegWrite(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR, MV_E6171_SMI_PHY_DATA, 0x3360);
mvEthSwitchRegWrite(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR, MV_E6171_SMI_PHY_COMMAND,
(0x9410 | (prt << 5)));
/*Make sure SMIBusy bit cleared before another SMI operation can take place*/
@@ -330,24 +591,23 @@
do {
mvEthSwitchRegRead(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR, MV_E6171_SMI_PHY_COMMAND,®);
- if(timeout-- == 0) {
+ if (timeout-- == 0) {
mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
return;
}
- } while (reg & E6171_PHY_SMI_BUSY_MASK);
+ } while (reg & E6171_PHY_SMI_BUSY_MASK);
mvEthSwitchRegWrite(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR, MV_E6171_SMI_PHY_DATA,0x9140);
mvEthSwitchRegWrite(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR,
MV_E6171_SMI_PHY_COMMAND,(0x9400 | (prt << 5)));
-
/*Make sure SMIBusy bit cleared before another SMI operation can take place*/
timeout = E6171_PHY_TIMEOUT;
do {
mvEthSwitchRegRead(ethPortNum, MV_E6171_GLOBAL_2_REG_DEV_ADDR,
MV_E6171_SMI_PHY_COMMAND,®);
- if(timeout-- == 0) {
+ if (timeout-- == 0) {
mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
return;
}
@@ -355,31 +615,103 @@
}
}
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET + cpuPort, 0x4, 0x7f);
-
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr + cpuPort, 0x4, 0x7f);
+
/* Init LEDs on RD-6282 */
/* Move all LEDs to special */
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET, 0x16, (BIT15|0x67));
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET, 0x16, (BIT15|BIT12|0x32));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr, MV_E6171_LED_CONTROL, (BIT15|0x67));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr, MV_E6171_LED_CONTROL, (BIT15|BIT12|0x32));
/* Port 0 LED special activity link */
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET, 0x16, (BIT15|BIT14|BIT13|BIT12|BIT0));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr, MV_E6171_LED_CONTROL, (BIT15|BIT14|BIT13|BIT12|BIT0));
/* Port 1 LED special activity link */
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET+1, 0x16, (BIT15|BIT14|BIT13|BIT12|BIT1));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr + 1, MV_E6171_LED_CONTROL, (BIT15|BIT14|BIT13|BIT12|BIT1));
/* Port 2 LED special activity link */
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET+2, 0x16, (BIT15|BIT14|BIT13|BIT12|BIT2));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr + 2, MV_E6171_LED_CONTROL, (BIT15|BIT14|BIT13|BIT12|BIT2));
/* Port 3 LED special activity link */
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET+3, 0x16, (BIT15|BIT14|BIT13|BIT12|BIT3));
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr + 3, MV_E6171_LED_CONTROL, (BIT15|BIT14|BIT13|BIT12|BIT3));
#ifdef RD_88F6710
- mvEthSwitchRegWrite(ethPortNum, MV_E6161_PORTS_OFFSET, 0x16, 0xf00f);
+ mvEthSwitchRegWrite(ethPortNum, swicthPhyAddr, MV_E6171_LED_CONTROL, 0xf00f);
#endif
}
+MV_VOID mvEthE6172SwitchBasicInit(MV_U32 ethPortNum)
+{
+
+ MV_U32 prt;
+ MV_U16 reg;
+ MV_U32 timeout;
+ MV_32 cpuPort = MV_E6172_CPU_PORT;/*mvBoardSwitchCpuPortGet(0);*/
+ MV_U16 smiReg, data;
+
+ /* The 6172 needs a delay */
+ mvOsDelay(1000);
+
+ /* Init vlan of switch 1 and enable all ports */
+ switchVlanInit(ethPortNum, MV_E6172_CPU_PORT, MV_E6172_MAX_PORTS_NUM, MV_E6172_PORTS_OFFSET,
+ MV_E6172_ENABLED_PORTS);
+
+ /* Enable RGMII delay on Tx and Rx for cpu port, force duplex, link up, flow control, and speed to 1Gps*/
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_PORTS_OFFSET + cpuPort, MV_E6172_SWITCH_PHIYSICAL_CTRL_REG,
+ QD_PCS_RGMII_RX_TIMING_MASK | QD_PCS_RGMII_TX_TIMING_MASK | QD_PCS_FLOW_CONTROL_VALUE_MASK
+ | QD_PCS_FORCED_FLOW_CONTROL_MASK | QD_PCS_LINK_VALUE_MASK | QD_PCS_FORCED_LINK_MASK
+ | QD_PCS_DUPLEX_VALUE_MASK | QD_PCS_FORCED_DUPLEX_MASK | QD_PCS_FORCE_SPEED_1G);
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_PORTS_OFFSET + cpuPort, MV_E6172_SWITCH_PORT_CTRL_REG,
+ QD_PC_VLAN_TUNNEL_BY_PASS | QD_PC_INITIAL_PRI_IP | QD_PC_EGRESS_FLOODS_ALL | QD_PC_PORT_STATE_FORWARDING);
+
+ /* Power up PHYs */
+ for (prt = 0; prt < MV_E6172_MAX_PORTS_NUM - 2; prt++) {
+ if (prt != MV_E6172_CPU_PORT) {
+ /*Enable Phy power up for switch 1*/
+ data = QD_PHY_MDI_CROSS_AUTO | QD_PHY_ENERGY_DETECT_SENSE_PERIODIC_TX_NLP |
+ QD_PHY_DOWNSHIFT_COUNTER;
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR,
+ MV_E6172_SMI_PHY_DATA, data);
+ smiReg = (QD_SMI_BUSY | (prt << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_WRITE << QD_SMI_OP_BIT) |
+ (QD_PHY_SPEC_CONTROL_REG << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT));
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR,
+ MV_E6172_SMI_PHY_COMMAND, smiReg);
+ /*Make sure SMIBusy bit cleared before another SMI operation can take place*/
+ timeout = E6172_PHY_TIMEOUT;
+
+ do {
+ mvEthSwitchRegRead(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR,
+ MV_E6172_SMI_PHY_COMMAND, ®);
+ if (timeout-- == 0) {
+ mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
+ return;
+ }
+ } while (reg & E6172_PHY_SMI_BUSY_MASK);
+
+ data = QD_PHY_RESET | QD_PHY_AUTONEGO | QD_PHY_DUPLEX | QD_PHY_SPEED_MSB;
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR, MV_E6172_SMI_PHY_DATA,
+ data);
+ smiReg = (QD_SMI_BUSY | (prt << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_WRITE << QD_SMI_OP_BIT) |
+ (QD_PHY_CONTROL_REG << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT));
+ mvEthSwitchRegWrite(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR,
+ MV_E6172_SMI_PHY_COMMAND, smiReg);
+
+ /*Make sure SMIBusy bit cleared before another SMI operation can take place*/
+ timeout = E6172_PHY_TIMEOUT;
+
+ do {
+ mvEthSwitchRegRead(ethPortNum, MV_E6172_GLOBAL_2_REG_DEV_ADDR,
+ MV_E6172_SMI_PHY_COMMAND, ®);
+ if (timeout-- == 0) {
+ mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
+ return;
+ }
+ } while (reg & E6172_PHY_SMI_BUSY_MASK);
+ }
+ }
+
+}
+
static void switchVlanInit(MV_U32 ethPortNum, MV_U32 switchCpuPort, MV_U32 switchMaxPortsNum,
MV_U32 switchPortsOffset, MV_U32 switchEnabledPortsMask)
{
@@ -405,12 +737,13 @@
}
}
+#ifdef MV_SWITCH_DIRECT_ACCESS
void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 switchPort,
- MV_U32 switchReg, MV_U16 data)
+ MV_U32 switchReg, MV_U16 data)
{
MV_U32 offset = 0;
- if (mvBoardIsInternalSwitchConnected() == MV_FALSE) {
+ if (mvBoardIsSwitchConnected() == MV_FALSE) {
mvOsPrintf("No Switch.\n");
return;
}
@@ -423,11 +756,11 @@
}
void mvEthSwitchRegRead(MV_U32 ethPortNum, MV_U32 switchPort,
- MV_U32 switchReg, MV_U16 *data)
+ MV_U32 switchReg, MV_U16 *data)
{
MV_U32 result, reg = 0;
- if (mvBoardIsInternalSwitchConnected() == MV_FALSE) {
+ if (mvBoardIsSwitchConnected() == MV_FALSE) {
mvOsPrintf("No Switch.\n");
return;
}
@@ -440,6 +773,118 @@
*data = result;
}
+#else /*defined(MV_SWITCH_SMI_ACCESS)*/
+/*******************************************************************************
+* mvEthSwitchWaitSMICommandRegFree -
+*
+* DESCRIPTION:
+* wait SMI command register to be free
+*
+* INPUT:
+* timeOut - the wait time, in 100MS units
+*
+* OUTPUT:
+* None
+*
+* RETURN: true - SMI command register is free, false - SMI command register is not free
+*
+*******************************************************************************/
+static MV_BOOL mvEthSwitchWaitSMICommandRegFree(MV_U32 timeOut)
+{
+ MV_U16 smiReg;
+ int i;
+
+ /* first check that it is not busy */
+ if (mvEthPhyRegRead(switchPhyAddr, (MV_U32)QD_REG_SMI_COMMAND, &smiReg) != MV_OK)
+ return MV_FALSE;
+
+ timeOut = QD_SMI_ACCESS_LOOP; /* initialize the loop count */
+
+ if (smiReg & QD_SMI_BUSY) {
+ for (i = 0; i < QD_SMI_TIMEOUT; i++)
+ ;
+ do {
+ if (timeOut-- < 1)
+ return MV_FALSE;
+ if (mvEthPhyRegRead(switchPhyAddr, (MV_U32)QD_REG_SMI_COMMAND, &smiReg) != MV_OK)
+ return MV_FALSE;
+ } while (smiReg & QD_SMI_BUSY);
+ }
+
+ return MV_TRUE;
+}
+
+void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 switchPort,
+ MV_U32 switchReg, MV_U16 data)
+{
+ MV_U16 smiReg;
+
+ if (mvBoardIsSwitchConnected() == MV_FALSE) {
+ mvOsPrintf("No Switch.\n");
+ return;
+ }
+
+ if (switchAccessMode != SMI_MULTI_ADDR_MODE) {
+ mvEthPhyRegWrite(switchPort, switchReg, data);
+ return;
+ }
+
+ /* wait SMI command register to be free */
+ if (mvEthSwitchWaitSMICommandRegFree(QD_SMI_ACCESS_LOOP) == MV_FALSE)
+ return;
+
+ if (mvEthPhyRegWrite(switchPhyAddr, (MV_U32)QD_REG_SMI_DATA, data) != MV_OK)
+ return;
+
+ smiReg = QD_SMI_BUSY | (switchPort << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_WRITE << QD_SMI_OP_BIT) |
+ (switchReg << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT);
+
+ if (mvEthPhyRegWrite(switchPhyAddr, (MV_U32)QD_REG_SMI_COMMAND, smiReg) != MV_OK)
+ return;
+
+ return;
+}
+
+
+void mvEthSwitchRegRead(MV_U32 ethPortNum, MV_U32 switchPort,
+ MV_U32 switchReg, MV_U16 *data)
+{
+ MV_U16 smiReg;
+
+ if (mvBoardIsSwitchConnected() == MV_FALSE) {
+ mvOsPrintf("No Switch.\n");
+ return;
+ }
+
+ if (switchAccessMode != SMI_MULTI_ADDR_MODE) {
+ mvEthPhyRegRead(switchPort, switchReg, &smiReg);
+ *data = smiReg;
+ return;
+ }
+
+ /* wait SMI command register to be free */
+ if (mvEthSwitchWaitSMICommandRegFree(QD_SMI_ACCESS_LOOP) == MV_FALSE)
+ return;
+
+ smiReg = QD_SMI_BUSY | (switchPort << QD_SMI_DEV_ADDR_BIT) | (QD_SMI_READ << QD_SMI_OP_BIT) |
+ (switchReg << QD_SMI_REG_ADDR_BIT) | (QD_SMI_CLAUSE22 << QD_SMI_MODE_BIT);
+
+ if (mvEthPhyRegWrite(switchPhyAddr, (MV_U32)QD_REG_SMI_COMMAND, smiReg) != MV_OK)
+ return;
+
+ /* wait SMI command register to be free */
+ if (mvEthSwitchWaitSMICommandRegFree(QD_SMI_ACCESS_LOOP) == MV_FALSE)
+ return;
+
+ if (mvEthPhyRegRead(switchPhyAddr, (MV_U32)QD_REG_SMI_DATA, &smiReg) != MV_OK)
+ return;
+
+ *data = smiReg;
+
+ return;
+}
+#endif
+
void mvEthSwitchPhyRegWrite(MV_U32 ethPortNum, MV_U16 prt,
MV_U16 regOffs, MV_U16 data)
{
diff --git a/board/mv_ebu/common/USP/ethSwitch/mvSwitch.h b/board/mv_ebu/common/USP/ethSwitch/mvSwitch.h
old mode 100755
new mode 100644
index 47ecfd9..621a843
--- a/board/mv_ebu/common/USP/ethSwitch/mvSwitch.h
+++ b/board/mv_ebu/common/USP/ethSwitch/mvSwitch.h
@@ -67,6 +67,11 @@
#include "mvTypes.h"
+/* definition for device scan mode */
+#define SMI_AUTO_SCAN_MODE 0 /* Scan 0 or 0x10 base address to find the QD */
+#define SMI_MANUAL_MODE 1 /* Use QD located at manually defined base addr */
+#define SMI_MULTI_ADDR_MODE 2 /* Use QD at base addr and use indirect access */
+
MV_VOID mvEthE6063SwitchBasicInit(MV_U32 ethPortNum);
MV_VOID mvEthE6065_61SwitchBasicInit(MV_U32 ethPortNum);
MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum);
@@ -76,9 +81,10 @@
void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data);
void mvEthSwitchPhyRegRead(MV_U32 ethPortNum, MV_U16 prt, MV_U16 regOffs, MV_U16 *data);
void mvEthSwitchPhyRegWrite(MV_U32 ethPortNum, MV_U16 prt, MV_U16 regOffs, MV_U16 data);
-
+MV_U16 mvEthSwitchGetDeviceID(void);
#ifdef MV88F66XX
MV_VOID mvAlpBoardSwitchBasicInit(MV_U32 enabledPorts);
#endif
+MV_VOID mvEthE6172SwitchBasicInit(MV_U32 ethPortNum);
#endif /* __INCETHSWITCHH */
diff --git a/board/mv_ebu/common/USP/ethSwitch/mvSwitchRegs.h b/board/mv_ebu/common/USP/ethSwitch/mvSwitchRegs.h
old mode 100755
new mode 100644
index 7529f2b..c74fb48
--- a/board/mv_ebu/common/USP/ethSwitch/mvSwitchRegs.h
+++ b/board/mv_ebu/common/USP/ethSwitch/mvSwitchRegs.h
@@ -110,18 +110,39 @@
#define E6161_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT)
/* E6171 related */
-#define MV_E6171_CPU_PORT 0x6
-#define MV_E6171_PORTS_OFFSET 0x10
-#define MV_E6171_SWITCH_PHIYSICAL_CTRL_REG 0x1
-#define MV_E6171_SWITCH_PORT_CTRL_REG 0x4
+#define MV_E6171_PRODUCT_NUM 0x171
+#define MV_E6176_PRODUCT_NUM 0x176
+#define MV_E6171_MAX_PORTS_NUM 7
+/* PHY registers */
+#define MV_E6171_SERDES_REG 0xf
+#define MV_E6171_SERDES_CONTROL_REG 0x0
+#define MV_E6171_PAGE_REG 0x16
+#define MV_E6171_SWITCH_PHIYSICAL_CTRL_REG 0x1
+/* Port registers */
+#define MV_E6171_LED_CONTROL 0x16
+#define MV_E6171_GLOBAL_2_REG_DEV_ADDR 0x1C
+/* SMI registers */
#define MV_E6171_SMI_PHY_COMMAND 0x18
#define MV_E6171_SMI_PHY_DATA 0x19
-#define MV_E6171_GLOBAL_2_REG_DEV_ADDR 0x1C
-#define MV_E6171_MAX_PORTS_NUM 7
-#define MV_E6171_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 6))
-#define E6171_PHY_TIMEOUT 10000
-#define E6171_PHY_SMI_BUSY_BIT 15 /* Busy */
-#define E6171_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT)
+#define E6171_PHY_SMI_BUSY_BIT 15 /* Busy */
+#define E6171_PHY_SMI_BUSY_MASK (1 << E6171_PHY_SMI_BUSY_BIT)
+#define E6171_PHY_TIMEOUT 10000
+#define MV_E6171_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 6))
+
+/* E6172 related */
+#define MV_E6172_PRODUCT_NUM 0x172
+#define MV_E6172_CPU_PORT 0x6
+#define MV_E6172_PORTS_OFFSET 0x10
+#define MV_E6172_SWITCH_PHIYSICAL_CTRL_REG 0x1
+#define MV_E6172_SWITCH_PORT_CTRL_REG 0x4
+#define MV_E6172_SMI_PHY_COMMAND 0x18
+#define MV_E6172_SMI_PHY_DATA 0x19
+#define MV_E6172_GLOBAL_2_REG_DEV_ADDR 0x1C
+#define MV_E6172_MAX_PORTS_NUM 7
+#define MV_E6172_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 6))
+#define E6172_PHY_TIMEOUT 10000
+#define E6172_PHY_SMI_BUSY_BIT 15 /* Busy */
+#define E6172_PHY_SMI_BUSY_MASK (1 << E6172_PHY_SMI_BUSY_BIT)
/* Armada 370 internal related */
#define MV_SW_CPU_PORT 0x6
@@ -155,4 +176,91 @@
#define MV_ALP_SW_PORTS_OFFSET 0x10
#define MV_ALP_SW_MAX_PORTS_NUM 7
+/* Start address of ports related register. */
+#define PORT_REGS_START_ADDR 0x8
+#define PORT_REGS_START_ADDR_8PORT 0x10
+
+#define QD_SMI_ACCESS_LOOP 1000
+#define QD_SMI_TIMEOUT 2
+
+/* Definition for Multi Address Mode */
+#define QD_REG_SMI_COMMAND 0x0
+#define QD_REG_SMI_DATA 0x1
+
+#define QD_REG_SWITCH_ID 0x3
+#define QD_REG_SWITCH_ID_PRODUCT_NUM_OFFSET 4
+
+#define QD_PHY_CONTROL_REG 0
+#define QD_PHY_SPEC_CONTROL_REG 16
+
+/* Bit Definition for QD_PHY_CONTROL_REG */
+#define QD_PHY_RESET 0x8000
+#define QD_PHY_LOOPBACK 0x4000
+#define QD_PHY_SPEED 0x2000
+#define QD_PHY_AUTONEGO 0x1000
+#define QD_PHY_POWER 0x800
+#define QD_PHY_ISOLATE 0x400
+#define QD_PHY_RESTART_AUTONEGO 0x200
+#define QD_PHY_DUPLEX 0x100
+#define QD_PHY_SPEED_MSB 0x40
+
+/* Bit Definition for QD_PHY_SPEC_CONTROL_REG */
+#define QD_PHY_MDI_CROSS_AUTO 0x60
+#define QD_PHY_ENERGY_DETECT_SENSE_PERIODIC_TX_NLP 0x300
+#define QD_PHY_DOWNSHIFT_COUNTER 0x3000
+
+/* Bit Definition for MV_SWITCH_PHYS_CONTROL_REG(switch port 1) */
+#define QD_PCS_RGMII_RX_TIMING_OFFSET 15
+#define QD_PCS_RGMII_TX_TIMING_OFFSET 14
+#define QD_PCS_FLOW_CONTROL_VALUE_OFFSET 7
+#define QD_PCS_FORCED_FLOW_CONTROL_OFFSET 6
+#define QD_PCS_LINK_VALUE_OFFSET 5
+#define QD_PCS_FORCED_LINK_OFFSET 4
+#define QD_PCS_DUPLEX_VALUE_OFFSET 3
+#define QD_PCS_FORCED_DUPLEX_OFFSET 2
+#define QD_PCS_FORCE_SPEED_OFFSET 0
+
+#define QD_PCS_RGMII_RX_TIMING_MASK (1 << QD_PCS_RGMII_RX_TIMING_OFFSET)
+#define QD_PCS_RGMII_TX_TIMING_MASK (1 << QD_PCS_RGMII_TX_TIMING_OFFSET)
+#define QD_PCS_FLOW_CONTROL_VALUE_MASK (1 << QD_PCS_FLOW_CONTROL_VALUE_OFFSET)
+#define QD_PCS_FORCED_FLOW_CONTROL_MASK (1 << QD_PCS_FORCED_FLOW_CONTROL_OFFSET)
+#define QD_PCS_LINK_VALUE_MASK (1 << QD_PCS_LINK_VALUE_OFFSET)
+#define QD_PCS_FORCED_LINK_MASK (1 << QD_PCS_FORCED_LINK_OFFSET)
+#define QD_PCS_DUPLEX_VALUE_MASK (1 << QD_PCS_DUPLEX_VALUE_OFFSET)
+#define QD_PCS_FORCED_DUPLEX_MASK (1 << QD_PCS_FORCED_DUPLEX_OFFSET)
+
+#define QD_PCS_FORCE_SPEED_1G (2 << QD_PCS_FORCE_SPEED_OFFSET)
+#define QD_PCS_FORCE_SPEED_NOT_FORCED (3 << QD_PCS_FORCE_SPEED_OFFSET)
+
+/* Bit Definition for MV_SWITCH_PORT_CONTROL_REG(switch port 4) */
+#define QD_PC_PORT_STATE_OFFSET 0
+#define QD_PC_EGRESS_FLOODS_OFFSET 2
+#define QD_PC_INITIAL_PRI_OFFSET 4
+#define QD_PC_VLAN_TUNNEL_OFFSET 7
+
+#define QD_PC_PORT_STATE_FORWARDING (3 << QD_PC_PORT_STATE_OFFSET)
+#define QD_PC_EGRESS_FLOODS_ALL (3 << QD_PC_EGRESS_FLOODS_OFFSET)
+#define QD_PC_INITIAL_PRI_IP (2 << QD_PC_INITIAL_PRI_OFFSET)
+#define QD_PC_VLAN_TUNNEL_BY_PASS (1 << QD_PC_VLAN_TUNNEL_OFFSET)
+
+
+
+
+/* Bit definition for QD_REG_SMI_COMMAND */
+#define QD_SMI_BUSY 0x8000
+#define QD_SMI_MODE 0x1000
+#define QD_SMI_MODE_BIT 12
+#define QD_SMI_OP_BIT 10
+#define QD_SMI_OP_SIZE 2
+#define QD_SMI_DEV_ADDR_BIT 5
+#define QD_SMI_DEV_ADDR_SIZE 5
+#define QD_SMI_REG_ADDR_BIT 0
+#define QD_SMI_REG_ADDR_SIZE 5
+
+#define QD_SMI_CLAUSE45 0
+#define QD_SMI_CLAUSE22 1
+
+#define QD_SMI_WRITE 0x01
+#define QD_SMI_READ 0x02
+
#endif /* __INCethswitchregsh */
diff --git a/board/mv_ebu/common/USP/mv_cmd.c b/board/mv_ebu/common/USP/mv_cmd.c
index fc9003a..96610d1 100644
--- a/board/mv_ebu/common/USP/mv_cmd.c
+++ b/board/mv_ebu/common/USP/mv_cmd.c
@@ -28,6 +28,7 @@
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "boardEnv/mvBoardEnvLib.h"
#include "cpu/mvCpu.h"
+#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
#if defined(MV_INC_BOARD_NOR_FLASH)
#include "norflash/mvFlash.h"
@@ -992,7 +993,6 @@
return 1;
}
-
U_BOOT_CMD(
phyWrite, 4, 4, phy_write_cmd,
"phyWrite - Write Phy register\n",
@@ -1002,7 +1002,6 @@
#if defined(MV_INCLUDE_SWITCH)
#include "ethSwitch/mvSwitch.h"
-
int switch_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
MV_U16 phyReg;
@@ -1039,6 +1038,7 @@
"\tWrite to the switch register.\n"
);
+
int switch_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
MV_U16 phyReg;
@@ -1115,7 +1115,144 @@
" MAC_Port. \n"
"\tRead the switch ports counters. \n"
);
-#endif
+#elif defined(MV_SWITCH_ADDRESS_COMPLETION) /* MV_INCLUDE_SWITCH */
+
+#define SWITCH_REGS_BASE_ADDR_MASK 0xFC000000
+#define SWITCH_ADDR_COMPL_MSB_VAL(addr) ((addr >> 24) & 0xFF)
+#define SWITCH_ADDR_COMPL_SHIFT(addr) (((addr >> 24) & 0x3) << 3)
+#define SWITCH_BUS_ADDR(addr) ((~SWITCH_REGS_BASE_ADDR_MASK & addr) |\
+ (SWITCH_WIN_BASE_ADDR_GET() & SWITCH_REGS_BASE_ADDR_MASK))
+
+/*******************************************************************************
+* SWITCH_WIN_BASE_ADDR_GET
+*
+* DESCRIPTION:
+* This function returns the base address of switch registers window
+*
+*
+* RETURN:
+* base address of switch registers window
+*
+*******************************************************************************/
+static __inline MV_U32 SWITCH_WIN_BASE_ADDR_GET(MV_VOID)
+{
+ static MV_U32 baseAddr;
+ baseAddr = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(SWITCH_WIN_ID));
+ return baseAddr;
+}
+
+/*******************************************************************************
+* SWITCH_ADDR_COMPL_SET
+*
+* DESCRIPTION:
+* This function configures address completion register
+*
+* INPUT:
+* addr - the address to access indirectly
+*
+*******************************************************************************/
+static __inline MV_STATUS SWITCH_ADDR_COMPL_SET(MV_U32 addr)
+{
+ MV_U32 rVal;
+ /* Configure address completion region REG using SERDES memory window */
+ rVal = MV_MEMIO32_READ(SWITCH_WIN_BASE_ADDR_GET());
+ rVal &= ~(0xFF << SWITCH_ADDR_COMPL_SHIFT(addr));
+ rVal |= SWITCH_ADDR_COMPL_MSB_VAL(addr) << SWITCH_ADDR_COMPL_SHIFT(addr);
+ MV_MEMIO32_WRITE(SWITCH_WIN_BASE_ADDR_GET(), rVal);
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSwitchRegisterGet
+*
+* DESCRIPTION:
+* This function reads switch register with address completion
+*
+* INPUT:
+* address - the address to read indirectly
+* mask - mask of the read data
+*
+* OUTPUT:
+* data - the register's data value
+*
+*
+*******************************************************************************/
+void mvSwitchRegisterGet(MV_U32 address, MV_U32 *data, MV_U32 mask)
+{
+ SWITCH_ADDR_COMPL_SET(address); /* Only MSB is important, serdes number offset does not matter */
+ *data = MV_MEMIO32_READ(SWITCH_BUS_ADDR(address)) & mask;
+}
+
+/*******************************************************************************
+* switchRegRead
+*
+* DESCRIPTION:
+* This command reads switch register with address completion
+*
+*******************************************************************************/
+int switch_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ MV_U32 regVal;
+
+ mvSwitchRegisterGet(simple_strtoul(argv[1], NULL, 16), ®Val, 0xFFFF);
+ printf ("0x%x\n", regVal);
+
+ return 1;
+}
+U_BOOT_CMD(
+ switchRegRead, 2, 2, switch_read_cmd,
+"switchRegRead - Read switch register, using Address completion\n",
+" Reg_offset. \n"
+"\tRead the switch register, using Address completion. \n"
+);
+
+/*******************************************************************************
+* mvSwitchRegisterSet
+*
+* DESCRIPTION:
+* This function writes to switch register with address completion
+*
+* address - the address to write to indirectly
+* data - the data to write
+* mask - mask of the write data
+*
+*******************************************************************************/
+void mvSwitchRegisterSet(MV_U32 address, MV_U32 data, MV_U32 mask)
+{
+ MV_U32 regData;
+
+ if ((mask & 0xFFFF) != 0xFFFF) { /* since switch registers are 16 bits - check only the relevant bits */
+ mvSwitchRegisterGet(address, ®Data, ~mask);
+ regData |= (data & mask);
+ } else
+ regData = data;
+
+ SWITCH_ADDR_COMPL_SET(address); /* Only MSB is important, serdes number offset does not matter */
+
+ MV_MEMIO32_WRITE(SWITCH_BUS_ADDR(address), regData);
+}
+
+/*******************************************************************************
+* switchRegWrite
+*
+* DESCRIPTION:
+* This command writes to switch register with address completion
+*
+*******************************************************************************/
+int switch_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ mvSwitchRegisterSet(simple_strtoul(argv[1], NULL, 16), simple_strtoul(argv[2], NULL, 16), 0xFFFF);
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ switchRegWrite, 3, 3, switch_write_cmd,
+"switchRegWrite - Write to switch register, using Address completion\n",
+" Reg_offset Reg_data. \n"
+"\tWrite to the switch register, using Address completion. \n"
+);
+#endif /* MV_SWITCH_ADDRESS_COMPLETION */
#endif /* #if defined(MV_INCLUDE_GIG_ETH) */
#define REG_SDRAM_CONFIG_ADDR 0x1400
@@ -1123,6 +1260,8 @@
#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C
#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0
+#define REG_PHY_DATA 0
+#define REG_PHY_CTRL 1
/******************************************************************************
* Category - DDR3 Training
@@ -1130,13 +1269,13 @@
* Need modifications (Yes/No) - no
*****************************************************************************/
#ifdef MV_DDR_TRAINING_CMD_NEW_TIP
-unsigned int trainingReadPhyReg(int uiRegAddr, int uiPup)
+unsigned int trainingReadPhyReg(int uiRegAddr, int uiPup, int type)
{
unsigned int uiReg;
unsigned int addrLow = 0x3F & uiRegAddr;
unsigned int addrHi = ((0xC0 & uiRegAddr) >> 6);
- uiReg = (1 << 31) + (uiPup << 22) + (addrHi << 28) + (addrLow << 16);
+ uiReg = (1 << 31) + (uiPup << 22) + (type << 26) + (addrHi << 28) + (addrLow << 16);
MV_REG_WRITE(REG_PHY_REGISTRY_FILE_ACCESS_ADDR,uiReg&0x7FFFFFFF);
MV_REG_WRITE(REG_PHY_REGISTRY_FILE_ACCESS_ADDR,uiReg);
@@ -1166,7 +1305,7 @@
printf("CS: %d \n", uiCs);
for(uiPup = 0; uiPup < uiPupNum; uiPup++) {
- uiReg = trainingReadPhyReg(0 + uiCs*4,uiPup);
+ uiReg = trainingReadPhyReg(0 + uiCs*4,uiPup, REG_PHY_DATA);
uiPhase = (uiReg >> 6) & 0x7;
uiDelay = uiReg & 0x1F;
printf("Write Leveling: PUP: %d, Phase: %d, Delay: %d\n",uiPup,uiPhase,uiDelay);
@@ -1174,7 +1313,7 @@
for (uiPup = 0; uiPup < uiPupNum; uiPup++) {
- uiReg = trainingReadPhyReg(2 + uiCs*4,uiPup);
+ uiReg = trainingReadPhyReg(2 + uiCs*4,uiPup, REG_PHY_DATA);
uiPhase = (uiReg >> 6) & 0x7;
uiDelay = uiReg & 0x1F;
printf("Read Leveling: PUP: %d, Phase: %d, Delay: %d\n",uiPup, uiPhase, uiDelay);
@@ -1192,7 +1331,7 @@
if (uiDq == 9)
uiDq++;
- uiReg = trainingReadPhyReg(0x10+uiDq+uiCs*0x12,uiPup);
+ uiReg = trainingReadPhyReg(0x10+uiDq+uiCs*0x12,uiPup, REG_PHY_DATA);
uiDelay = uiReg & 0x1F;
if (uiDq == 0)
@@ -1203,7 +1342,7 @@
}
for(uiPup=0; uiPup < uiPupNum; uiPup++) {
for(uiDq = 0; uiDq < 9; uiDq++) {
- uiReg = trainingReadPhyReg(0x50+uiDq+uiCs*0x12,uiPup);
+ uiReg = trainingReadPhyReg(0x50+uiDq+uiCs*0x12,uiPup, REG_PHY_DATA);
uiDelay = uiReg & 0x1F;
if (uiDq == 0)
@@ -1217,7 +1356,7 @@
/*Read Centralization windows sizes for Scratch PHY registers*/
for(uiPup = 0; uiPup < uiPupNum; uiPup++)
{
- uiReg = trainingReadPhyReg(0xC0+uiCs,uiPup);
+ uiReg = trainingReadPhyReg(0xC0+uiCs,uiPup, REG_PHY_DATA);
uiCentralRxRes = uiReg >> 5;
uiCentralTxRes = uiReg & 0x1F;
printf("Central window size for PUP %d is %d(RX) and %d(TX)\n", uiPup, uiCentralRxRes, uiCentralTxRes);
@@ -1378,11 +1517,31 @@
* Functionality- The commands prints the row data of stability results for DDR3 Training
* Need modifications (Yes/No) - no
*****************************************************************************/
+MV_U32 dminPhyRegTable[20][2] = {
+ {0 ,0xC0},
+ {0 ,0xC1},
+ {0 ,0xC2},
+ {0 ,0xC3},
+ {0 ,0xC4},
+ {1 ,0xC0},
+ {1 ,0xC1},
+ {1 ,0xC2},
+ {1 ,0xC3},
+ {1 ,0xC4},
+ {2 ,0xC0},
+ {2 ,0xC1},
+ {2 ,0xC2},
+ {2 ,0xC3},
+ {2 ,0xC4},
+ {0 ,0xC5},
+ {1 ,0xC5},
+ {2 ,0xC5},
+ {0 ,0xC6},
+ {1 ,0xC6}};
int trainingStability_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
{
- MV_U32 uiCsEna, interfaceId=0,csindex = 0,busId=0,padIndex=0;
- MV_U32 regData;
- MV_U32 readData;
+ MV_U32 uiCsEna, interfaceId=0, csindex = 0,busId=0, padIndex=0;
+ MV_U32 regData, regData1;
uiCsEna = MV_REG_READ(REG_DDR3_RANK_CTRL_ADDR) & 0xF;
@@ -1425,12 +1584,12 @@
for(interfaceId = 0; interfaceId < 1; interfaceId++)
{
printf("Data: %d,%d,",interfaceId,mvCtrlGetJuncTemp());//add Junction Temperature
- readData = MV_REG_READ(0x14C8);
- printf("%d,%d,",((readData&0x3F0)>>4),((readData&0xFC00)>>10));
- readData = MV_REG_READ(0x17C8);
- printf("%d,%d,",((readData&0x3F0)>>4),((readData&0xFC00)>>10));
- readData = MV_REG_READ(0x1DC8);
- printf("%d,%d,",((readData&0x3F0000)>>16),((readData&0xFC00000)>>22));
+ regData = MV_REG_READ(0x14C8);
+ printf("%d,%d,",((regData&0x3F0)>>4),((regData&0xFC00)>>10));
+ regData = MV_REG_READ(0x17C8);
+ printf("%d,%d,",((regData&0x3F0)>>4),((regData&0xFC00)>>10));
+ regData = MV_REG_READ(0x1DC8);
+ printf("%d,%d,",((regData&0x3F0000)>>16),((regData&0xFC00000)>>22));
for(csindex = 0; csindex < 4; csindex++)
{
if (!(uiCsEna & (1 << csindex))) continue;
@@ -1438,48 +1597,52 @@
for(busId = 0; busId <5; busId++)
{
#ifdef CONFIG_DDR3/*DDR3*/
- regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex,busId);
+ regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex,busId, REG_PHY_DATA);
printf("%d,%d,",(regData&0x1F),((regData&0x3E0)>>5));
#else/*DDR4*/
- regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex,busId);
- printf("%d,%d,",(regData&0x1F)*4,2*((regData&0xFFE0)>>5));
- regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex + 4,busId);
- printf("%d,%d,",(regData&0x1F)*4,2*((regData&0xFFE0)>>5));
+ /*DminTx, areaTX*/
+ regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex,busId, REG_PHY_DATA);
+ regData1 = trainingReadPhyReg(dminPhyRegTable[csindex*5+busId][1],dminPhyRegTable[csindex*5+busId][0], REG_PHY_CTRL);
+ printf("%d,%d,",2*(regData1&0xFF),regData);
+ /*DminRx, areaRX*/
+ regData = trainingReadPhyReg(RESULT_DB_PHY_REG_ADDR+csindex+4,busId, REG_PHY_DATA);
+ regData1 = trainingReadPhyReg(dminPhyRegTable[csindex*5+busId][1],dminPhyRegTable[csindex*5+busId][0], REG_PHY_CTRL);
+ printf("%d,%d,",2*(regData1>>8),regData);
#endif
/*WL*/
- regData = trainingReadPhyReg(WL_PHY_REG+csindex*4,busId);
+ regData = trainingReadPhyReg(WL_PHY_REG+csindex*4,busId, REG_PHY_DATA);
printf("%d,%d,%d,",(regData&0x1F)+((regData&0x1C0)>>6)*32,(regData&0x1F),(regData&0x1C0)>>6);
/*RL*/
- readData = MV_REG_READ(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
- readData = (readData&(0xF<<(4*csindex))) >> (4*csindex);
- regData = trainingReadPhyReg(RL_PHY_REG+csindex*4,busId);
- printf("%d,%d,%d,%d,",(regData&0x1F)+((regData&0x1C0)>>6)*32 + readData*64,(regData&0x1F),((regData&0x1C0)>>6),readData);
+ regData1 = MV_REG_READ(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
+ regData1 = (regData1&(0xF<<(4*csindex))) >> (4*csindex);
+ regData = trainingReadPhyReg(RL_PHY_REG+csindex*4,busId, REG_PHY_DATA);
+ printf("%d,%d,%d,%d,",(regData&0x1F)+((regData&0x1C0)>>6)*32 + regData1*64,(regData&0x1F),((regData&0x1C0)>>6),regData1);
/*Centralization*/
- regData = trainingReadPhyReg(WRITE_CENTRALIZATION_PHY_REG+csindex*4,busId);
+ regData = trainingReadPhyReg(WRITE_CENTRALIZATION_PHY_REG+csindex*4,busId, REG_PHY_DATA);
printf("%d,",(regData&0x3F));
- regData = trainingReadPhyReg(READ_CENTRALIZATION_PHY_REG+csindex*4,busId);
+ regData = trainingReadPhyReg(READ_CENTRALIZATION_PHY_REG+csindex*4,busId, REG_PHY_DATA);
printf("%d,",(regData&0x1F));
/*Vref */
- regData = trainingReadPhyReg(PAD_CONFIG_PHY_REG+csindex,busId);
+ regData = trainingReadPhyReg(PAD_CONFIG_PHY_REG+csindex,busId, REG_PHY_DATA);
printf("%d,",(regData&0x7));
/*DQVref*/
/* Need to add the Read Function from device*/
printf("%d,",0);
#ifndef CONFIG_DDR3
- for(padIndex = 0; padIndex < 10; padIndex++)
+ for(padIndex = 0; padIndex < 11; padIndex++)
{
- regData = trainingReadPhyReg(0xD0+12*csindex+padIndex,busId);
+ regData = trainingReadPhyReg(0xD0+12*csindex+padIndex,busId, REG_PHY_DATA);
printf("%d,",(regData&0x3F));
}
#endif
- for(padIndex = 0; padIndex < 10; padIndex++)
+ for(padIndex = 0; padIndex < 11; padIndex++)
{
- regData = trainingReadPhyReg(0x10+16*csindex+padIndex,busId);
+ regData = trainingReadPhyReg(0x10+16*csindex+padIndex,busId, REG_PHY_DATA);
printf("%d,",(regData&0x3F));
}
- for(padIndex = 0; padIndex < 10; padIndex++)
+ for(padIndex = 0; padIndex < 11; padIndex++)
{
- regData = trainingReadPhyReg(0x50+16*csindex+padIndex,busId);
+ regData = trainingReadPhyReg(0x50+16*csindex+padIndex,busId, REG_PHY_DATA);
printf("%d,",(regData&0x3F));
}
}
diff --git a/board/mv_ebu/common/USP/mv_egiga_legacy.c b/board/mv_ebu/common/USP/mv_egiga_legacy.c
index 3827b12..0401a19 100644
--- a/board/mv_ebu/common/USP/mv_egiga_legacy.c
+++ b/board/mv_ebu/common/USP/mv_egiga_legacy.c
@@ -153,6 +153,7 @@
dev->halt = (void*)mvEgigaHalt;
dev->send = (void*)mvEgigaTx;
dev->recv = (void*)mvEgigaRx;
+ dev->index = port;
dev->priv = priv;
dev->iobase = 0;
dev->port = port;
@@ -518,4 +519,4 @@
}
#endif /* legacy */
-#endif /* #if defined (MV_INCLUDE_GIG_ETH) */
\ No newline at end of file
+#endif /* #if defined (MV_INCLUDE_GIG_ETH) */
diff --git a/board/mv_ebu/common/USP/mv_egiga_neta.c b/board/mv_ebu/common/USP/mv_egiga_neta.c
index 55215e5..2ea503d 100755
--- a/board/mv_ebu/common/USP/mv_egiga_neta.c
+++ b/board/mv_ebu/common/USP/mv_egiga_neta.c
@@ -162,6 +162,7 @@
dev->priv = priv;
dev->iobase = 0;
dev->write_hwaddr = 0;
+ dev->index = port;
priv->port = port;
priv->devInit = MV_FALSE;
priv->devEnable = MV_FALSE;
diff --git a/board/mv_ebu/common/USP/mv_egiga_pp2.c b/board/mv_ebu/common/USP/mv_egiga_pp2.c
index a741930..0a9f903 100644
--- a/board/mv_ebu/common/USP/mv_egiga_pp2.c
+++ b/board/mv_ebu/common/USP/mv_egiga_pp2.c
@@ -233,7 +233,7 @@
egigaPriv *priv = NULL;
/* First disable GMAC */
- mvGmacPortDisable(priv->port);
+ mvGmacPortDisable(port);
dev = malloc(sizeof(struct eth_device));
if (!dev) {
@@ -259,6 +259,7 @@
dev->priv = priv;
dev->iobase = 0;
dev->write_hwaddr = 0;
+ dev->index = port;
priv->port = port;
priv->devInit = MV_FALSE;
priv->devEnable = MV_FALSE;
diff --git a/board/mv_ebu/common/USP/mv_fdt.c b/board/mv_ebu/common/USP/mv_fdt.c
index 7bd0351..ad57143 100644
--- a/board/mv_ebu/common/USP/mv_fdt.c
+++ b/board/mv_ebu/common/USP/mv_fdt.c
@@ -27,6 +27,8 @@
#include "libfdt.h"
#include "fdt_support.h"
#include "mvBoardEnvLib.h"
+#include "ethSwitch/mvSwitchRegs.h"
+#include "ethSwitch/mvSwitch.h"
/*******************************************************************************
* fdt_env_setup
@@ -83,6 +85,12 @@
if (!env)
setenv("bootcmd_fdt",bootcmd_fdt);
+#if defined (CONFIG_OF_LIBFDT_IS_DEFAULT)
+ env = getenv("bootcmd");
+ if (!env)
+ setenv("bootcmd", bootcmd_fdt);
+#endif /* (CONFIG_OF_LIBFDT_IS_DEFAULT) */
+
#ifdef CONFIG_GFCH100
env = getenv("fdtcontinueonerror");
if (!env)
@@ -103,11 +111,19 @@
static int mv_fdt_find_node(void *fdt, const char *name);
static int mv_fdt_board_compatible_name_update(void *fdt);
static int mv_fdt_update_serial(void *fdt);
+#ifdef CONFIG_PIC_GPIO
static int mv_fdt_update_pic_gpio(void *fdt);
+#endif
static int mv_fdt_update_cpus(void *fdt);
static int mv_fdt_update_pex(void *fdt);
+#ifdef MV_INCLUDE_SATA
static int mv_fdt_update_sata(void *fdt);
+#endif
+#ifdef MV_INCLUDE_USB
static int mv_fdt_update_usb(void *fdt, MV_UNIT_ID unitType);
+static int mv_fdt_update_usb2(void *fdt);
+static int mv_fdt_update_usb3(void *fdt);
+#endif
static int mv_fdt_update_ethnum(void *fdt);
static int mv_fdt_update_flash(void *fdt);
static int mv_fdt_set_node_prop(void *fdt, const char *node, const char *prop, const char *prop_val);
@@ -115,16 +131,78 @@
static int mv_fdt_scan_and_set_alias(void *fdt, const char *name, const char *alias);
static int mv_fdt_nand_mode_fixup(void *fdt);
static int mv_fdt_update_pinctrl(void *fdt);
+#ifdef MV_INCLUDE_AUDIO
+static int mv_fdt_update_audio(void *fdt);
+#endif
+#ifdef MV_INCLUDE_SWITCH
+static int mv_fdt_update_switch(void *fdt);
+#endif
static int mv_fdt_debug;
#ifdef CONFIG_MV_SDHCI
static int mv_fdt_update_sdhci(void *fdt);
#endif
+#ifdef CONFIG_SWITCHING_SERVICES
+static int mv_fdt_update_prestera(void *fdt);
+#endif
+#ifdef MV_INCLUDE_TDM
+static int mv_fdt_update_tdm(void *fdt);
+#endif
+#ifdef MV_USB_VBUS_CYCLE
+static int mv_fdt_update_usb_vbus(void *fdt);
+#endif
+#ifdef MV_INCLUDE_USB_DEVICE
+static int mv_fdt_update_usb_device(void *fdt);
+#endif
#if 0 /* not compiled, since this routine is currently not in use */
static int mv_fdt_remove_prop(void *fdt, const char *path,
const char *name, int nodeoff);
#endif
+typedef int (update_fnc_t)(void *);
+update_fnc_t *update_sequence[] = {
+ mv_fdt_update_cpus, /* Get number of CPUs and update dt */
+ mv_fdt_update_pex, /* Get number of active PEX port and update DT */
+#ifdef MV_INCLUDE_SATA
+ mv_fdt_update_sata, /* Get number of active SATA units and update DT */
+#endif
+#ifdef MV_INCLUDE_USB
+ mv_fdt_update_usb2, /* Get number of active USB2.0 units and update DT */
+ mv_fdt_update_usb3, /* Get number of active USB3.0 units and update DT */
+#endif
+ mv_fdt_update_ethnum, /* Get number of active ETH port and update DT */
+#ifdef CONFIG_MV_SDHCI
+ mv_fdt_update_sdhci, /* Update SDHCI driver settings in DT */
+#endif
+#ifdef CONFIG_SWITCHING_SERVICES
+ mv_fdt_update_prestera, /* Update prestera driver DT settings - for AMC board */
+#endif
+#ifdef MV_INCLUDE_TDM
+ mv_fdt_update_tdm, /* Update tdm node in DT */
+#endif
+#ifdef MV_USB_VBUS_CYCLE
+ mv_fdt_update_usb_vbus,
+#endif
+ mv_fdt_update_flash, /* Get number of active flash devices and update DT */
+ mv_fdt_nand_mode_fixup, /* Update NAND controller ECC settings in DT */
+ mv_fdt_update_pinctrl, /* Update pinctrl driver settings in DT */
+ mv_fdt_board_compatible_name_update, /* Update compatible (board name) in DT */
+ mv_fdt_update_serial, /* Update serial/UART nodes in DT */
+#ifdef CONFIG_PIC_GPIO
+ mv_fdt_update_pic_gpio,
+#endif
+#ifdef MV_INCLUDE_AUDIO
+ mv_fdt_update_audio, /* Update audio-controller+sound nodes in DT */
+#endif
+#ifdef MV_INCLUDE_SWITCH
+ mv_fdt_update_switch,
+#endif
+#ifdef MV_INCLUDE_USB_DEVICE
+ mv_fdt_update_usb_device,
+#endif
+ NULL,
+};
+
enum nfc_driver_type {
MV_FDT_NFC_PXA3XX, /* mainline pxa3xx-nand */
MV_FDT_NFC_HAL, /* mvebu HAL-based NFC */
@@ -175,6 +253,7 @@
{
int err; /* error number */
char *env; /* env value */
+ update_fnc_t **update_fnc_ptr;
int counter = 0; /* error counter */
int force = 0; /* continue on error if set */
@@ -210,75 +289,14 @@
fixup_memory_node(blob);
mv_fdt_dprintf("Memory node updated\n");
- /* Get number of CPUs and update dt */
- err = mv_fdt_update_cpus(blob);
- if (err < 0)
- report_error(&counter, force, "Updating cpus failed\n");
-
- /* Get number of active PEX port and update DT */
- err = mv_fdt_update_pex(blob);
- if (err < 0)
- report_error(&counter, force, "Updating pex failed\n");
-
- /* Get number of active SATA units and update DT */
- err = mv_fdt_update_sata(blob);
- if (err < 0)
- report_error(&counter, force, "Updating pex failed\n");
-
- /* Get number of active USB2.0 units and update DT */
- err = mv_fdt_update_usb(blob, USB_UNIT_ID);
- if (err < 0)
- report_error(&counter, force, "Updating usb 2.0 failed\n");
-
- /* Get number of active USB3.0 units and update DT */
- err = mv_fdt_update_usb(blob, USB3_UNIT_ID);
- if (err < 0)
- report_error(&counter, force, "Updating usb 3.0 failed\n");
-
- /* Get number of active ETH port and update DT */
- err = mv_fdt_update_ethnum(blob);
- if (err < 0)
- report_error(&counter, force, "Updating ethnum failed\n");
-
-#ifdef CONFIG_MV_SDHCI
- /* Update SDHCI driver settings in DT */
- err = mv_fdt_update_sdhci(blob);
- if (err < 0)
- report_error(&counter, force, "Updating sdhci failed\n");
-#endif
-
- /* Get number of active flash devices and update DT */
- err = mv_fdt_update_flash(blob);
- if (err < 0)
- report_error(&counter, force, "Updating flash failed\n");
-
- /* Update NAND controller ECC settings in DT */
- err = mv_fdt_nand_mode_fixup(blob);
- if (err < 0)
- report_error(&counter, force, "Updating nand mode failed\n");
-
- /* Update pinctrl driver settings in DT */
- err = mv_fdt_update_pinctrl(blob);
- if (err < 0)
- report_error(&counter, force, "Updating pinctrl failed\n");
-
- /* Update compatible (board name) in DT */
- err = mv_fdt_board_compatible_name_update(blob);
- if (err < 0)
- report_error(&counter, force, "Updating board name failed\n");
-
- /* Update serial/UART nodes in DT */
- err = mv_fdt_update_serial(blob);
- if (err < 0)
- report_error(&counter, force, "Updating serial failed\n");
-
- err = mv_fdt_update_pic_gpio(blob);
- if (err < 0)
- report_error(&counter, force, "Updating pic gpio failed\n");
-
- if (counter > 0) {
- mv_fdt_dprintf("Encountered %d errors while updating device tree\n", counter);
- goto bs_fail;
+ /* Make updates of functions in update_sequence */
+ for (update_fnc_ptr = update_sequence; *update_fnc_ptr; ++update_fnc_ptr) {
+ err = (*update_fnc_ptr)(blob);
+ if (err < 0) {
+ report_error(&counter, force,
+ "Updating function 0x%08x failed\n", update_fnc_ptr);
+ /* report_error will "goto bs_fail" on !force */
+ }
}
printf("Updating device tree successful\n");
@@ -363,6 +381,9 @@
* mv_fdt_update_cpus
*
* DESCRIPTION:
+* target : remove excessice cpu nodes.
+* node : cpus
+* dependencies : CPU core num in SOC_COHERENCY_FABRIC_CFG_REG.
*
* INPUT:
* fdt.
@@ -424,10 +445,14 @@
return 0;
}
+#ifdef MV_INCLUDE_SATA
/*******************************************************************************
* mv_fdt_update_sata
*
* DESCRIPTION:
+* target : Update status field of SATA nodes.
+* node, properties : -property status @ node SATA
+* dependencies : sata unit status in sataUnitActive array.
*
* INPUT:
* fdt.
@@ -457,18 +482,160 @@
sprintf(node, "sata@%x", mvCtrlSataRegBaseGet(i));
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
}
return 0;
}
+#endif /* MV_INCLUDE_SATA */
+
+#ifdef MV_INCLUDE_TDM
+/*******************************************************************************
+* mv_fdt_update_tdm
+*
+* DESCRIPTION:
+* target : update status field of tdm@X node.
+* node, properties : -property status @ node tdm@x.
+* dependencies : isTdmConnected entry in board structure.
+*
+* INPUT:
+* fdt.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* -1 on error os 0 otherwise.
+*
+*******************************************************************************/
+static int mv_fdt_update_tdm(void *fdt)
+{
+ int err, nodeoffset; /* nodeoffset: node offset from libfdt */
+ char propval[10]; /* property value */
+ const char *prop = "status"; /* property name */
+ char node[64]; /* node name */
+
+ if (mvBoardIsTdmConnected() == MV_TRUE)
+ sprintf(propval, "okay");
+ else
+ sprintf(propval, "disabled");
+
+ sprintf(node, "tdm@%x", MV_TDM_OFFSET);
+ nodeoffset = mv_fdt_find_node(fdt, node);
+
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return 0;
+ }
+
+ if (strncmp(fdt_get_name(fdt, nodeoffset, NULL), node, strlen(node)) == 0) {
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ propval, strlen(propval)+1));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return 0;
+ }
+ mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef MV_USB_VBUS_CYCLE
+/*******************************************************************************
+* mv_fdt_update_usb_vbus
+*
+* DESCRIPTION:
+* target : update status field of usb3_phy and usb3-vbus-gpio/usb3-vbus-exp1 node.
+* node, properties : -property status @ node usb3_phy and usb3-vbus-gpio/usb3-vbus-exp1 node.
+* dependencies : BOARD_GPP_USB_VBUS entry in BoardGppInfo --> usb3-vbus-gpio node
+* MV_IO_EXPANDER_USB_VBUS entry in BoardIoExpPinInfo --> usb3-vbus-exp1
+*
+* INPUT:
+* fdt.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* -1 on error os 0 otherwise.
+*
+*******************************************************************************/
+static int mv_fdt_update_usb_vbus(void *fdt)
+{
+ int err, nodeoffset; /* nodeoffset: node offset from libfdt */
+ char propval[10]; /* property value */
+ const char *prop = "status"; /* property name */
+ const char *node = NULL, *phy_node = NULL; /* node name */
+ MV_BOARD_IO_EXPANDER_TYPE_INFO ioInfo; /* empty stub - not to be used */
+
+ sprintf(propval, "okay");
+
+ if (mvBoardIoExpanderTypeGet(MV_IO_EXPANDER_USB_VBUS, &ioInfo) != MV_ERROR) {
+ node = "usb3-vbus-exp1";
+ phy_node = "usb3-phy-exp1";
+ } else {
+ /* remove invalid i2c pins information, to avoid unexpected Linux behaviour*/
+ mv_fdt_remove_node(fdt, "i2c-pins-0");
+ }
+ if (mvBoardUSBVbusGpioPinGet(0) != MV_ERROR) {
+ node = "usb3-vbus-gpio";
+ phy_node = "usb3-phy-gpio";
+ } else {
+ /* remove invalid vbus gpio pins information, to avoid unexpected Linux behaviour*/
+ mv_fdt_remove_node(fdt, "xhci0-vbus-pins");
+ }
+
+ if (!node && !phy_node)
+ return 0;
+
+ nodeoffset = mv_fdt_find_node(fdt, node);
+
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return 0;
+ }
+ if (strncmp(fdt_get_name(fdt, nodeoffset, NULL), node, strlen(node)) == 0) {
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ propval, strlen(propval)+1));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return 0;
+ }
+ mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
+ }
+
+ /* enable 'usb3_phy' node - for Linux regulator usage */
+ nodeoffset = mv_fdt_find_node(fdt, phy_node);
+
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", phy_node);
+ return 0;
+ }
+
+ if (strncmp(fdt_get_name(fdt, nodeoffset, NULL), phy_node, strlen(phy_node)) == 0) {
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ propval, strlen(propval)+1));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, phy_node);
+ return 0;
+ }
+ mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, phy_node);
+ } return 0;
+ return 0;
+}
+#endif /* MV_USB_VBUS_CYCLE */
#ifdef CONFIG_MV_SDHCI
/*******************************************************************************
* mv_fdt_update_sdhci
*
* DESCRIPTION:
+* target : update status and dat3-cd fields of MMC node.
+* node, properties : -property status and dat3-cd @ node sdhci@X.
+* dependencies : status of MMC in isSdMmcConnected entry in board structure.
*
* INPUT:
* fdt.
@@ -486,6 +653,7 @@
char propval[10]; /* property value */
const char *prop = "status"; /* property name */
char node[64]; /* node name */
+ char *env;
if (mvBoardisSdioConnected())
sprintf(propval, "okay");
@@ -497,7 +665,7 @@
if (nodeoffset < 0) {
mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
- return -1;
+ return 0;
}
if (strncmp(fdt_get_name(fdt, nodeoffset, NULL), node, strlen(node)) == 0) {
@@ -505,11 +673,122 @@
propval, strlen(propval)+1));
if (err < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
}
+ /* add DAT3 detection */
+ env = getenv("sd_detection_dat3");
+
+ if (!env || strcmp(env, "yes") != 0)
+ return 0;
+
+ prop = "dat3-cd";
+
+ /* add empty property 'dat3-cd' */
+ if (fdt_appendprop(fdt, nodeoffset, prop, NULL, 0) < 0)
+ mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
+
+ return 0;
+}
+#endif
+
+#ifdef MV_INCLUDE_AUDIO
+/*******************************************************************************
+* mv_fdt_update_audio
+*
+* DESCRIPTION: update audio-controller and sound nodes (SPDIF/I2S)
+*
+* INPUT: fdt.
+* OUTPUT: None.
+* RETURN: -1 on error os 0 otherwise.
+*******************************************************************************/
+static int mv_fdt_update_audio(void *fdt)
+{
+ int err, nodeoffset, i; /* nodeoffset: node offset from libfdt */
+ char propval[10]; /* property value */
+ const char *prop = "status"; /* property name */
+ char nodes[2][64]; /* node names */
+
+ if (mvBoardIsAudioConnected() == MV_TRUE)
+ sprintf(propval, "okay");
+ else
+ sprintf(propval, "disabled");
+
+ sprintf(nodes[0], "audio-controller@%x", MV_AUDIO_OFFSET);
+ sprintf(nodes[1], "sound");
+
+ for (i = 0; i < 2; ++i) {
+ nodeoffset = mv_fdt_find_node(fdt, nodes[i]);
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", nodes[i]);
+ return 0;
+ }
+
+ if (strncmp(fdt_get_name(fdt, nodeoffset, NULL), nodes[i], strlen(nodes[i])) == 0) {
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ propval, strlen(propval)+1));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, nodes[i]);
+ return 0;
+ }
+ mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, nodes[i]);
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SWITCHING_SERVICES
+/*******************************************************************************
+* mv_fdt_update_prestera
+*
+* DESCRIPTION:
+* target : update status field of prestera node by checking if the board is AMC.
+* node, properties : -property status @ node prestera.
+* dependencies : AMC status saved in isAmc entry in board structure
+*
+* INPUT:
+* fdt.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* -1 on error os 0 otherwise.
+*
+*******************************************************************************/
+static int mv_fdt_update_prestera(void *fdt)
+{
+ int err, nodeoffset; /* nodeoffset: node offset from libfdt */
+ char propval[10]; /* property value */
+ const char *prop = "status"; /* property name */
+ const char *node = "prestera"; /* node name */
+ MV_BOOL isAmc;
+
+ isAmc = mvBoardisAmc();
+ if (isAmc)
+ sprintf(propval, "okay");
+ else
+ sprintf(propval, "disabled");
+
+ nodeoffset = mv_fdt_find_node(fdt, node);
+
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return 0;
+ }
+
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ propval, strlen(propval)+1));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return -1;
+ }
+ mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
+
return 0;
}
#endif
@@ -518,6 +797,9 @@
* mv_fdt_update_pex
*
* DESCRIPTION:
+* target : update status fields of pcieX nodes.
+* node, properties : -property status @ node pcieX.
+* dependencies : boardPexInfo structure entry in board structure.
*
* INPUT:
* fdt.
@@ -555,7 +837,7 @@
nodeoffset = mv_fdt_find_node(fdt, node);
if (nodeoffset < 0) {
mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
- return -1;
+ return 0;
}
while (strncmp(node, "pcie", 4) == 0) {
for (k = 0; k <= pexnum; k++)
@@ -572,7 +854,7 @@
if (err < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n",
prop, node);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop,
propval, node);
@@ -580,13 +862,13 @@
if (nodeoffset < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n",
prop, node);
- return -1;
+ return 0;
}
node = fdt_get_name(fdt, nodeoffset, NULL);
}
return 0;
}
-
+#ifdef MV_INCLUDE_USB
/*******************************************************************************
* mv_fdt_update_usb
*
@@ -613,7 +895,7 @@
sprintf(node, "usb%s@%x", unitType == USB_UNIT_ID ? "" : "3", MV_USB2_USB3_REGS_OFFSET(unitType, i));
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
}
@@ -621,9 +903,96 @@
}
/*******************************************************************************
+* mv_fdt_update_usb2
+*
+* DESCRIPTION: update USB2.0(eHCI) status, this function is wrapper function
+* to mv_fdt_update_usb, In order to add it to update_sequence array
+*
+* INPUT: fdt.
+* OUTPUT: None.
+* RETURN: -1 on error os 0 otherwise.
+*******************************************************************************/
+static int mv_fdt_update_usb2(void *fdt)
+{
+ return mv_fdt_update_usb(fdt, USB_UNIT_ID);
+}
+
+/*******************************************************************************
+* mv_fdt_update_usb3
+*
+* DESCRIPTION: update USB3.0(xHCI) status, this function is wrapper function
+* to mv_fdt_update_usb, In order to add it to update_sequence array
+*
+* INPUT: fdt.
+* OUTPUT: None.
+* RETURN: -1 on error os 0 otherwise.
+*******************************************************************************/
+static int mv_fdt_update_usb3(void *fdt)
+{
+ return mv_fdt_update_usb(fdt, USB3_UNIT_ID);
+}
+#endif /* MV_INCLUDE_USB */
+
+#ifdef MV_INCLUDE_USB_DEVICE
+/*******************************************************************************
+* mv_fdt_update_usb_device
+*
+* DESCRIPTION: usb3 device status
+* target : update status field of u3d and udc nodes.
+* node, properties : property status @ nodes usb3@X, udc@X and udc@X.
+* dependencies : S@R field 'usb3port0' or 'usb3port1'.
+*
+* INPUT: fdt.
+* OUTPUT: None.
+* RETURN: -1 on error os 0 otherwise.
+*******************************************************************************/
+static int mv_fdt_update_usb_device(void *fdt)
+{
+ char propval[10]; /* property value */
+ const char *prop = "status"; /* property name */
+ char node[64]; /* node name */
+ int i;
+ MV_BOOL isDevice = MV_FALSE;
+
+ /* disable usb3 nodes */
+ for (i = 0; i < MV_USB3_MAX_HOST_PORTS; i++) {
+ if (mvBoardIsUsb3PortDevice(i)) {
+ /* if Port is Device, disable corresponding Host node */
+ sprintf(propval, "disabled");
+ isDevice = MV_TRUE;
+ break;
+ }
+ }
+
+ if (isDevice == MV_FALSE)
+ return 0;
+
+ sprintf(node, "usb3@%x", MV_USB2_USB3_REGS_OFFSET(USB3_UNIT_ID, i));
+ if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0)
+ mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
+
+ /* enable 'u3d' and 'udc' nodes */
+ sprintf(propval, "okay");
+ sprintf(node, "u3d@%x", MV_USB3_DEVICE_REGS_OFFSET);
+ if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
+ mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
+ return 0;
+ }
+ sprintf(node, "udc@%x", MV_USB3_DEVICE_USB2_REGS_OFFSET);
+ if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
+ mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
+ return 0;
+ }
+ return 0;
+}
+#endif /* MV_INCLUDE_USB_DEVICE */
+/*******************************************************************************
* mv_fdt_update_pinctrl
*
* DESCRIPTION:
+* target : update compatible field of pinctrl node.
+* node, properties : -property compatible @ node pinctrl.
+* dependencies :DEV_ID_REG value "device model type".
*
* INPUT:
* fdt.
@@ -645,11 +1014,11 @@
const char *node = "pinctrl"; /* node name */
#endif
- /* update pinctrl driver 'compatible' propert, according to device model type */
+ /* update pinctrl driver 'compatible' property, according to device model type */
sprintf(propval, "marvell,mv88f%x-pinctrl", mvCtrlModelGet());
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
return 0;
@@ -659,6 +1028,14 @@
* mv_fdt_update_ethnum
*
* DESCRIPTION:
+* target : update ethernet nodes for PP3/Neta drivers.
+* node, properties : PP3 Driver : -property status @ node nic@X.
+* -property phy-mode and phy-id @ node macX.
+* Neta Driver : -property status and phy-mode @ node ethernet@X.
+* -property reg @ node ethernet-phy@X.
+* dependencies : pBoardNetComplexInfo entry in board structure.
+* pBoardMacInfo entry in board structure.
+* For PP3/Neta driver we get ethernet nodes via "nic@/ethernet@" aliasses.
*
* INPUT:
* fdt.
@@ -691,7 +1068,7 @@
aliasesoffset = mv_fdt_find_node(fdt, "aliases");
if (aliasesoffset < 0) {
mv_fdt_dprintf("Lack of 'aliases' node in device tree\n");
- return -1;
+ return 0;
}
/* Walk trough all aliases and count Ethernet ports entries */
@@ -713,11 +1090,11 @@
node = fdt_getprop(fdt, aliasesoffset, prop, &len);
if (node == NULL) {
mv_fdt_dprintf("Lack of '%s' property in 'aliases' node\n", prop);
- return -1;
+ return 0;
}
if (len == 0) {
mv_fdt_dprintf("Empty property value\n");
- return -1;
+ return 0;
}
/* Alias points to the ETH port node using full DT path */
nodeoffset = fdt_path_offset(fdt, node);
@@ -738,12 +1115,12 @@
phandle = fdt_getprop(fdt, nodeoffset, "phy", &len);
if (len == 0) {
mv_fdt_dprintf("Empty \"phy\" property value\n");
- return -1;
+ return 0;
}
phyoffset = fdt_node_offset_by_phandle(fdt, ntohl(*phandle));
if (phyoffset < 0) {
mv_fdt_dprintf("Failed to get PHY node by phandle %x\n", ntohl(*phandle));
- return -1;
+ return 0;
}
/* Setup PHY address in DT in "reg" property of an appropriate PHY node.
@@ -754,7 +1131,7 @@
if (err < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n",
prop, fdt_get_name(fdt, phyoffset, NULL));
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set property '%s' of node '%s' to %#010x\n",
prop, fdt_get_name(fdt, phyoffset, NULL), ntohl(phyAddr));
@@ -771,7 +1148,7 @@
break;
default:
mv_fdt_dprintf("Bad port type received for interface %d\n", port);
- return -1;
+ return 0;
}
/* Setup PHY connection type in DT */
@@ -779,7 +1156,7 @@
mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop, propval, strlen(propval)+1));
if (err < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
@@ -791,7 +1168,7 @@
mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop, propval, strlen(propval)+1));
if (err < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property to '%s' in '%s' node\n", prop, propval, node);
@@ -855,7 +1232,7 @@
sprintf(node, "spi@%x", MV_SPI_REGS_OFFSET(unit));
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
} /* SPI units/buses */
@@ -882,7 +1259,7 @@
#endif
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
/* handle NOR flashes - there is only one NOR unit, but different CS are possible */
@@ -916,10 +1293,9 @@
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
}
-
return 0;
}
@@ -1072,8 +1448,8 @@
int err = 0; /* error number */
int level = 0; /* current fdt scanning depth */
char aliasname[128]; /* alias name to be stored in '/aliases' node */
- char path[128] = ""; /* full path to current node */
- char tmp[128]; /* auxiliary char array for extended node name*/
+ char path[256] = ""; /* full path to current node */
+ char tmp[256]; /* auxiliary char array for extended node name*/
char *cut; /* auxiliary char pointer */
const char *node; /* node name */
uint32_t tag; /* device tree tag at given offset */
@@ -1286,7 +1662,7 @@
if (err < 0) {
mv_fdt_dprintf("NFC update: fail to modify '%s'\n",
prop);
- return -1;
+ return 0;
}
mv_fdt_dprintf("NFC update: set '%s' property to '%s'\n",
prop, propval);
@@ -1343,7 +1719,7 @@
mv_fdt_modify(fdt, err, fdt_setprop(fdt,0 , prop, propval, len));
if (len <= 0 || err < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property to Root node\n", prop);
@@ -1354,6 +1730,9 @@
* mv_fdt_update_serial
*
* DESCRIPTION:
+* target : Update status field of serial nodes.
+* node, properties: : -property status @ node serial
+* dependencies : checks if it is a active serial port via mvUartPortGet function.
*
* INPUT:
* fdt.
@@ -1381,13 +1760,13 @@
sprintf(node, "serial@%x", MV_UART_REGS_OFFSET(i));
if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
- return -1;
+ return 0;
}
}
return 0;
}
-
+#ifdef CONFIG_PIC_GPIO
/*******************************************************************************
* mv_fdt_update_pic_gpio
*
@@ -1397,7 +1776,7 @@
* 1. pinctrl/pic-pins-0/marvell,pins = "mpp33", "mpp34";
* 2. pm_pic/ctrl-gpios = <0x0000000c 0x00000001 0x00000001 0x0000000c 0x00000002 0x00000001>;
* Each GPIO is represented in 'ctrl-gpios' property with 3 values of 32 bits:
-* '<pinctrl-0_base + gpio_group_num gpio_pin_num_in_group ACTIVE_LOW>'
+* '<gpios_phandle[gpio_group_num] gpio_pin_num_in_group ACTIVE_LOW>'
* i.e : for mpp 33, and given pinctrl-0 = <0x0000000b> :
* gpio_group_num = 33/32 = 1
* gpio_pin_num_in_group= 33%32 = 1
@@ -1421,11 +1800,13 @@
const char *marvell_pins_prop = "marvell,pins";
const char *pm_picNode = "pm_pic";
const char *ctrl_gpios_prop = "ctrl-gpios";
- const void *pinctrl_0_base;
- MV_U32 pinctrl_0_base_val, picGpioInfo[MAX_GPIO_NUM];
+ MV_U32 picGpioInfo[MAX_GPIO_NUM];
MV_U32 ctrl_gpios_prop_value[3*MAX_GPIO_NUM]; /* 3*32bit is required per GPIO */
char propval[256] = "";
int err, len = 0, nodeoffset, i, gpioMaxNum = mvBoardPICGpioGet(picGpioInfo);
+ MV_U32 gpios_phandle[2]; /* phandle values of gpio nodes */
+ MV_U32 gpio_offset;
+ char gpio_node[30] = "";
/* if board has no dedicated PIC MPP Pins: remove 'pm_pic' & 'pinctrl/pic-pins-0' */
if (gpioMaxNum <= 0) {
@@ -1437,6 +1818,21 @@
return 0;
}
+ /* fetch gpio nodes' phandle.
+ * every GPIO group have GPIO node id DT
+ * and for each GPIO pin, an entry is added to the ctrl-gpios,
+ * in order to link between the entry and the relevant gpio node for the relevant
+ * group, the phandle of the gpio node is added to the entry */
+ for (i = 0; i < 2; ++i) {
+ sprintf(gpio_node, "gpio@%X", MV_GPP_REGS_OFFSET(i));
+ gpio_offset = mv_fdt_find_node(fdt, gpio_node);
+ gpios_phandle[i] = fdt_get_phandle(fdt, gpio_offset);
+ if (!gpios_phandle[i]) {
+ mvOsPrintf("Failed updating suspend-resume GPIO pin settings in DT\n");
+ return 0;
+ }
+ }
+
/* set pinctrl/pic-pins-0/marvell,pins property as concatenated strings.
* (i.e : marvell,pins = "mpp33", "mpp34", "mpp35")
* append next string after the NULL character that the previous
@@ -1448,29 +1844,28 @@
mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, marvell_pins_prop, propval, len));
if (err < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", marvell_pins_prop, picPinsNode);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property in '%s' node\n", marvell_pins_prop, picPinsNode);
/* set pm_pic/ctrl-gpios property: */
nodeoffset = mv_fdt_find_node(fdt, pm_picNode); /* find 'pm_pic' node */
- pinctrl_0_base = fdt_getprop(fdt, nodeoffset, "pinctrl-0", &len);
+
if (len == 0) {
printf("Empty property value\n");
- return -1;
+ return 0;
}
/* Each GPIO is represented in 'ctrl-gpios' property with 3 values of 32 bits:
- * '<pinctrl-0_base + gpio_group_num gpio_pin_num_in_group ACTIVE_LOW>'
+ * '<gpios_phandle[gpio_group_num] gpio_pin_num_in_group ACTIVE_LOW>'
* i.e : for mpp 33, and given pinctrl-0 = <0x0000000b> :
* gpio_group_num = 33/32 = 1
* gpio_pin_num_in_group= 33%32 = 1
* ACTIVE_LOW = 1
* DT entry is : '<0x0000000c 0x00000001 0x00000001>'; */
- pinctrl_0_base_val = ntohl(*((unsigned int*)pinctrl_0_base)); /* DT integer values are in BE format */
for (i = 0 ; i < gpioMaxNum ; i++) {
/* pinctrl_0_base +gpio Group num */
- ctrl_gpios_prop_value[3*i] = htonl(pinctrl_0_base_val + picGpioInfo[i] / 32);
+ ctrl_gpios_prop_value[3*i] = htonl(gpios_phandle[picGpioInfo[i] / 32]);
/* 32 pins in each group */
ctrl_gpios_prop_value[3*i + 1] = htonl(picGpioInfo[i] % 32);
@@ -1482,11 +1877,135 @@
mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, ctrl_gpios_prop, ctrl_gpios_prop_value, 4*gpioMaxNum*3));
if (err < 0) {
mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", ctrl_gpios_prop, pm_picNode);
- return -1;
+ return 0;
}
mv_fdt_dprintf("Set '%s' property in '%s' node\n", ctrl_gpios_prop, pm_picNode);
return 0;
-}
+}
+#endif /* CONFIG_PIC_GPIO */
+#ifdef MV_INCLUDE_SWITCH
+/*******************************************************************************
+* mv_fdt_update_switch
+*
+* DESCRIPTION:
+* This routines updates switch node and ethernet-phy node on status and rgmii_(t)rx_timing_delay properties
+* according to Switch existence and Device ID detection, this route also set ethernet-phy@i node on reg property
+* if ethi is connected to switch
+*
+* INPUT:
+* fdt.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* -1 on error os 0 otherwise.
+*
+*******************************************************************************/
+static int mv_fdt_update_switch(void *fdt)
+{
+ char propval[10]; /* property value */
+ u32 propval_u32 = 0;
+ char prop[50]; /* property name */
+ char node[64]; /* node name */
+ MV_U16 switch_device_id;
+ int nodeoffset; /* node offset from libfdt */
+ int err;
+
+ switch_device_id = mvEthSwitchGetDeviceID();
+
+ /*if switch module is connected and detect correct switch device ID, enable switch in fdt*/
+ if (switch_device_id > 0)
+ sprintf(propval, "okay");
+ else
+ sprintf(propval, "disabled");
+
+ sprintf(node, "switch");
+ sprintf(prop, "status");
+
+ if (mv_fdt_set_node_prop(fdt, node, prop, propval) < 0) {
+ mv_fdt_dprintf("Failed to set property '%s' of node '%s' in device tree\n", prop, node);
+ return 0;
+ }
+
+ if (mvBoardIsSwitchConnected()) {
+ int i = 0;
+ switch_device_id >>= QD_REG_SWITCH_ID_PRODUCT_NUM_OFFSET;
+
+ for (i = 0; i < mvCtrlEthMaxPortGet(); i++) {
+ /*change the switch connected eth ports' phy to 999*/
+ /*999 mean that ethernet is not connected to phy*/
+ if (mvBoardSwitchConnectedPortGet(i) != -1) {
+ sprintf(node, "ethernet-phy@%d", i);
+ sprintf(prop, "reg");
+ propval_u32 = 999;
+
+ nodeoffset = mv_fdt_find_node(fdt, node);
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return -1;
+ }
+
+ /* Setup PHY address in DT in "reg" property of an appropriate PHY node.
+ This value is HEX number, not a string, and uses network byte order */
+ propval_u32 = htonl(propval_u32);
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop,
+ &propval_u32, sizeof(propval_u32)));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return -1;
+ }
+ }
+ }
+
+ /*for E6172 switch, rgmii_rx_timing_delay and rgmii_tx_timing_delay should be enabled*/
+ if (switch_device_id == MV_E6172_PRODUCT_NUM) {
+ /*set rgmii_rx_timing_delay and rgmii_tx_timing_delay to be enabled*/
+ sprintf(node, "switch");
+ sprintf(prop, "rgmii_rx_timing_delay");
+ /*enable delay to RXCLK for IND inputs when port is in RGMII mode*/
+ propval_u32 = 1;
+
+ nodeoffset = mv_fdt_find_node(fdt, node);
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return -1;
+ }
+
+ /* Setup rgmii_rx_timing_delay in DT.
+ This value is HEX number, not a string, and uses network byte order */
+ propval_u32 = htonl(propval_u32);
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop, &propval_u32, sizeof(propval_u32)));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return -1;
+ }
+
+ sprintf(node, "switch");
+ sprintf(prop, "rgmii_tx_timing_delay");
+ /*enable delay to GTXCLK for OUTD outputs when port is in RGMII mode*/
+ propval_u32 = 1;
+ nodeoffset = mv_fdt_find_node(fdt, node);
+ if (nodeoffset < 0) {
+ mv_fdt_dprintf("Lack of '%s' node in device tree\n", node);
+ return -1;
+ }
+
+ /* Setup rgmii_tx_timing_delay in DT.
+ This value is HEX number, not a string, and uses network byte order */
+ propval_u32 = htonl(propval_u32);
+ mv_fdt_modify(fdt, err, fdt_setprop(fdt, nodeoffset, prop, &propval_u32, sizeof(propval_u32)));
+ if (err < 0) {
+ mv_fdt_dprintf("Modifying '%s' in '%s' node failed\n", prop, node);
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
#endif
+#endif
+
diff --git a/board/mv_ebu/common/USP/mv_main.c b/board/mv_ebu/common/USP/mv_main.c
index dbf2159..2aaa439 100755
--- a/board/mv_ebu/common/USP/mv_main.c
+++ b/board/mv_ebu/common/USP/mv_main.c
@@ -98,7 +98,7 @@
#else
#define DB(x)
#endif
-
+extern void fdt_env_setup(char *fdtfile, MV_BOOL runUpdate);
extern int display_dram_config(int print);
int late_print_cpuinfo(void);
/* CPU address decode table. */
@@ -291,7 +291,6 @@
*(unsigned int *)(0x0 + i) = *(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
}
mvBoardDebugLed(4);
- mv_print_map();
return 0;
}
@@ -303,8 +302,8 @@
envSetDefault("console", "console=ttyS0,115200");
#if defined(MV_NAND) && defined(MV_INCLUDE_SPI)
- envSetDefault("mtdparts", "'mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);mtdparts=spi_flash:4m(boot),-(spi-rootfs)'");
- envSetDefault("mtdids", "nand0=armada-nand;spi0=spi_flash");
+ envSetDefault("mtdparts", "'mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs);spi_flash:4m(boot),-(spi-rootfs)'");
+ envSetDefault("mtdids", "nand0=armada-nand,spi0=spi_flash");
#elif defined(MV_NAND)
envSetDefault("mtdparts", "mtdparts=armada-nand:8m(boot)ro,8m@8m(kernel),-(rootfs)");
envSetDefault("mtdids", "nand0=armada-nand");
@@ -393,6 +392,9 @@
envSetDefault("bootcmd_lgcy", "tftpboot 0x2000000 $image_name; setenv bootargs $bootargs_dflt; bootm 0x2000000; ");
#endif /* #if defined (CONFIG_CMD_STAGE_BOOT) */
+#ifdef CONFIG_CMD_SOURCE
+ envSetDefault("run_script", "no");
+#endif
/* netbsd boot arguments */
env = getenv("netbsd_en");
if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) {
@@ -463,6 +465,13 @@
envSetDefault("enaLPAE", "no");;
#endif
+ /* Flatten Device Tree environment setup */
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+ fdt_env_setup("msys.dtb", MV_FALSE); /* static setup: Skip DT update for customer */
+#else
+ fdt_env_setup("msys.dtb", MV_FALSE); /* dynamic setup: run DT update (false since not supported yet) */
+#endif
+
#if (CONFIG_BOOTDELAY >= 0)
env = getenv("bootcmd");
if(!env)
@@ -681,7 +690,7 @@
/* init the units decode windows */
misc_init_r_dec_win();
-
+ mv_print_map();
/* Clear old kernel images which remained stored in memory */
memset ((void *)CONFIG_SYS_LOAD_ADDR, 0, CONFIG_SYS_MIN_HDR_DEL_SIZE);
mvBoardDebugLed(6);
@@ -698,7 +707,12 @@
/* Init the PHY or Switch of the board */
mvBoardEgigaPhyInit();
#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */
-
+#ifdef CONFIG_CMD_SOURCE
+ /* run saved script */
+ env = getenv("run_script");
+ if (env && strcmp(env, "yes") == 0)
+ run_command("mvsource run", 0);
+#endif
return 0;
}
diff --git a/board/mv_ebu/common/USP/mv_phy.c b/board/mv_ebu/common/USP/mv_phy.c
index 411e739..d289e2e 100644
--- a/board/mv_ebu/common/USP/mv_phy.c
+++ b/board/mv_ebu/common/USP/mv_phy.c
@@ -80,6 +80,7 @@
#include "eth/gbe/mvEthRegs.h"
#endif
#include "mvSysEthPhyApi.h"
+#include "ethSwitch/mvSwitchRegs.h"
#include "ethSwitch/mvSwitch.h"
#if defined (MV88F66XX)
@@ -191,7 +192,9 @@
*******************************************************************************/
void mvBoardLedMatrixInit(void)
{
+#ifdef MV_INCLUDE_SWITCH
MV_U8 i;
+#endif
if (mvCtrlDevFamilyIdGet(0) == MV_88F67X0)
/* Led matrix mode in 7Bit */
@@ -205,6 +208,7 @@
/* Use an internal device signal to drive the LED Matrix Control */
MV_REG_WRITE(LED_MATRIX_CONTROL_REG(2), BIT0 | BIT2 | BIT3 | BIT5);
+#ifdef MV_INCLUDE_SWITCH
/* initialize internal PHYs controlled by switch */
if (mvBoardIsInternalSwitchConnected() == MV_TRUE) {
for (i = 0; i < 4; i++) {
@@ -218,6 +222,7 @@
mvEthSwitchPhyRegWrite(0x0, i, 0x16, 0x0);
}
}
+#endif
}
/* initialize External RGMII-0 PHY (SMI controlled by MAC0 @address 0x1) */
@@ -286,6 +291,9 @@
int i;
MV_STATUS status;
MV_U32 phyAddr;
+#ifdef MV_INCLUDE_SWITCH
+ MV_U16 switchDeviceID;
+#endif
for (i = 0; i < mvCtrlEthMaxPortGet(); i++) {
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, i))
@@ -321,6 +329,27 @@
}
}
+#ifdef MV_INCLUDE_SWITCH
+ switchDeviceID = mvEthSwitchGetDeviceID();
+ if (mvBoardIsSwitchConnected()) {
+ switchDeviceID >>= QD_REG_SWITCH_ID_PRODUCT_NUM_OFFSET;
+ for (i = 0; i < mvCtrlEthMaxPortGet(); i++) {
+ /*force the switch connected eth port link up and disable auto-neg, bit 15 must set to 1*/
+ if (mvBoardSwitchConnectedPortGet(i) != -1)
+ MV_REG_WRITE((NETA_GMAC_AN_CTRL_REG(i) + INTER_REGS_BASE),
+ (NETA_FORCE_LINK_PASS_MASK | NETA_SET_GMII_SPEED_1000_MASK |
+ NETA_SET_FLOW_CONTROL_MASK | NETA_FLOW_CONTROL_ADVERTISE_MASK |
+ NETA_SET_FULL_DUPLEX_MASK | BIT15)/*0x9342*/);
+ }
+
+ /*now only E6172 switch works for NETA, so here no other switch initialization is called*/
+ if (switchDeviceID == MV_E6172_PRODUCT_NUM)
+ mvEthE6172SwitchBasicInit(0);
+ if (switchDeviceID == MV_E6176_PRODUCT_NUM)
+ mvEthE6171SwitchBasicInit(0);
+ }
+#endif
+
#elif defined (MV88F66XX) /* Avanta-LP: dynamic PPv2 configuration */
MV_U32 ethComplex = mvBoardEthComplexConfigGet();
char *eeeEnable = NULL;
diff --git a/board/mv_ebu/common/USP/mv_rtc2.c b/board/mv_ebu/common/USP/mv_rtc2.c
index 03b8120..c61b405 100644
--- a/board/mv_ebu/common/USP/mv_rtc2.c
+++ b/board/mv_ebu/common/USP/mv_rtc2.c
@@ -70,38 +70,100 @@
#include "mv_rtc2.h"
#if defined(CONFIG_CMD_DATE)
-
+/* This define for WA in rtc read */
+#define SAMPLE_NR 100
static int rtc_ready = -1;
+
/*******************************************************/
void rtc_init(void)
{
/* Update RTC-MBUS bridge timing parameters */
+ #ifdef ERRATA_FE_3124064
+ /* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
+ * Description:
+ * The device supports CPU write and read access to the RTC Time register.
+ * However, due to this erratum, Write to RTC TIME register may fail.
+ * Read from RTC TIME register may fail.
+ * Workaround:
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
+ * RTC TIME register should be read twice, the second read will return a proper value.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
+ * Functional Impact After Workaround is applied:
+ * No functional impact after WA is applied
+ */
+ MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4FFF);
+#else
MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4CFA);
+#endif
rtc_ready = 1;
}
+#ifdef ERRATA_FE_3124064
+struct _strTime2Freq {
+ unsigned long nTime;
+ unsigned int nFreq;
+
+};
+#endif
+
/*******************************************************/
int rtc_get(struct rtc_time *tm)
{
- unsigned long time, time_check;
+#ifdef ERRATA_FE_3124064
+ /* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
+ * Description:
+ * The device supports CPU write and read access to the RTC Time register.
+ * However, due to this erratum, Write to RTC TIME register may fail.
+ * Read from RTC TIME register may fail.
+ * Workaround:
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to
+ * RTC Status register.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge
+ * Timing Control register.
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to
+ * RTC Status register.
+ * RTC TIME register should be read 100 times, then find the result
+ * that appear most frequently, use this result as the correct value.
+ */
+ unsigned long nTimeArray[SAMPLE_NR], i, j, nTime, nMax = 0, indexMax = SAMPLE_NR - 1;
+ struct _strTime2Freq sTimeToFreq[SAMPLE_NR];
+#endif
if (rtc_ready != 1)
rtc_init();
+#ifdef ERRATA_FE_3124064
+ /* read RTC TIME register 100 times and save the values in array,
+ initialize the counters to zero */
+ for (i = 0; i < SAMPLE_NR; i++) {
+ sTimeToFreq[i].nFreq = 0;
+ nTimeArray[i] = RTC_READ_REG(RTC_TIME_REG_OFFS);
+ }
+ for (i = 0; i < SAMPLE_NR; i++) {
+ nTime = nTimeArray[i];
+ /* if nTime appears in sTimeToFreq array so add the counter of nTime value,
+ if didn't appear yet in counters array then allocate new member of
+ sTimeToFreq array with counter = 1 */
+ for (j = 0; j < SAMPLE_NR; j++) {
+ if (sTimeToFreq[j].nFreq == 0 || sTimeToFreq[j].nTime == nTime)
+ break;
+ }
+ if (sTimeToFreq[j].nFreq == 0)
+ sTimeToFreq[j].nTime = nTime;
+ sTimeToFreq[j].nFreq++;
+ /*find the most common result*/
+ if (nMax < sTimeToFreq[j].nFreq) {
+ indexMax = j;
+ nMax = sTimeToFreq[j].nFreq;
+ }
+ }
- time = RTC_READ_REG(RTC_TIME_REG_OFFS);
- /* WA for failing time read attempts. The HW ERRATA information should be added here */
- /* if detected more than one second between two time reads, read once again */
- time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
- if ((time_check - time) > 1)
- time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
- /* End of WA */
-
- to_tm(time_check, tm);
-
+ to_tm(sTimeToFreq[indexMax].nTime, tm);
+#else
+ to_tm(RTC_READ_REG(RTC_TIME_REG_OFFS), tm);
+#endif
return 0;
}
-
/*******************************************************/
int rtc_set(struct rtc_time *tm)
{
@@ -113,10 +175,22 @@
time = mktime(tm->tm_year, tm->tm_mon,
tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
- /* WA for failing time set attempts. The HW ERRATA information should be added here */
+#ifdef ERRATA_FE_3124064
+ /* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
+ * Description:
+ * The device supports CPU write and read access to the RTC Time register.
+ * However, due to this erratum, Write to RTC TIME register may fail.
+ * Read from RTC TIME register may fail.
+ * Workaround:
+ * Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
+ * RTC TIME register should be read twice, the second read will return a proper value.
+ * Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
+ * Functional Impact After Workaround is applied:
+ * No functional impact after WA is applied
+ */
RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
- mdelay(100);
- /* End of SW WA */
+ RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
+#endif
RTC_WRITE_REG(time, RTC_TIME_REG_OFFS);
return 0;
diff --git a/board/mv_ebu/common/USP/mv_serial.c b/board/mv_ebu/common/USP/mv_serial.c
index 89ea29b..1e49ef9 100755
--- a/board/mv_ebu/common/USP/mv_serial.c
+++ b/board/mv_ebu/common/USP/mv_serial.c
@@ -40,7 +40,11 @@
*/
__weak MV_U32 mvUartPortGet(void)
{
+#ifdef CONFIG_AMP_SUPPORT
+ return whoAmI();
+#else
return CONFIG_SYS_DUART_CHAN;
+#endif
}
int mv_serial_init (void)
@@ -66,18 +70,18 @@
{
if (c == '\n')
- mvUartPutc(whoAmI(), '\r');
- mvUartPutc(whoAmI(), c);
+ mvUartPutc(mvUartPortGet(), '\r');
+ mvUartPutc(mvUartPortGet(), c);
}
int mv_serial_getc(void)
{
- return mvUartGetc(whoAmI());
+ return mvUartGetc(mvUartPortGet());
}
int mv_serial_tstc(void)
{
- return mvUartTstc(whoAmI());
+ return mvUartTstc(mvUartPortGet());
}
void mv_serial_setbrg (void)
diff --git a/board/mv_ebu/common/USP/mv_usb.c b/board/mv_ebu/common/USP/mv_usb.c
index 3794dd0..bd24b65 100644
--- a/board/mv_ebu/common/USP/mv_usb.c
+++ b/board/mv_ebu/common/USP/mv_usb.c
@@ -35,42 +35,6 @@
#endif
#include "mvSysUsbConfig.h"
-/*******************************************************************************
-* getUsbActive - read 'usbActive' env variable and set active port
-*
-* INPUT:
-* MV_U32 usbUnitId - USB interface indication (USB2.0 / USB3.0)
-*
-* OUTPUT:
-* prints selected active port number, and selected interface
-*
-* RETURN:
-* Num of requested interface USB2/3
-*
-*******************************************************************************/
-MV_STATUS getUsbActive(MV_U32 usbUnitId, MV_U32 maxUsbHostPorts, MV_U32 maxSerDesLanes, MV_BOOL printEn)
-{
- char *env = getenv("usbActive");
- int usbActive = simple_strtoul(env, NULL, 10);
-
- /* if requested USB3.0 is not connected via SerDes, but there are enough USB3.0 ports */
- if (printEn) {
- if (usbUnitId == USB3_UNIT_ID && (usbActive >= maxSerDesLanes && maxUsbHostPorts > maxSerDesLanes)) {
- mvOsPrintf("\n'usbActive' warning (%d): Invalid USB3.0 port (no valid SerDes)..", usbActive);
- mvOsPrintf("Trying USB2.0 Host via USB3.0\n");
- } else if (usbActive >= maxUsbHostPorts && usbUnitId == USB_UNIT_ID) {
- mvOsPrintf("\n'usbActive' warning (%d): Invalid USB2.0 port\n", usbActive);
- }
-
- mvOsPrintf("Port (usbActive) : %d\tInterface (usbType = %d) : ", usbActive,
- ((usbUnitId == USB3_UNIT_ID) ? 3 : 2));
- }
- /* Fetch SoC USB mapping:
- For Some SoCs, when using single USB port, unit 1 is active and not 0 */
- usbActive = mvCtrlUsbMapGet(usbUnitId, usbActive);
-
- return usbActive;
-}
#if defined (CONFIG_USB_XHCI)
/*********************************************************************************/
@@ -197,6 +161,44 @@
.interface_supported = MV_FALSE
#endif
};
+/*******************************************************************************
+* printUsbError - This function used to print error message when USB error dedected.
+* called from "usb_lowlevel_init" and "usb_lowlevel_stop" functions.
+*
+* INPUT:
+* MV_BOOL value - MV_TRUE if usb connected on current board ,MV_FALSE otherwise.
+*
+* OUTPUT:
+* prints USB error messages.
+*
+* RETURN:
+* -1
+*
+*******************************************************************************/
+static int printUsbError(MV_BOOL mvBoardIsUsbPortConnected ,int port)
+{
+ int usbType = simple_strtoul(getenv("usbType"), NULL, 10);
+ int usb3HostNum = mvCtrlUsb3HostMaxGet();
+ int usb2HostNum = mvCtrlUsbMaxGet();
+
+ if(mvBoardIsUsbPortConnected == MV_FALSE)
+ mvOsPrintf("\nError: requested 'usbActive' (%d) is not connected on current board\n",port);
+ else {
+ mvOsPrintf("Error: requested 'usbType' (Type %d) is not supported.", usbType);
+ if ((usbType == 2 && usb2HostNum < 1) || (usbType ==3 && usb3HostNum < 1))
+ mvOsPrintf(" (no available USB%d ports on current Soc).\n",usbType);
+ }
+ if ((hc_ehci.interface_supported == MV_TRUE && usb2HostNum > 0) ||
+ (hc_xhci.interface_supported == MV_TRUE && usb3HostNum > 0))
+ mvOsPrintf("\n\n\t Supported Units:\n");
+ if (hc_ehci.interface_supported == MV_TRUE && usb2HostNum > 0)
+ mvOsPrintf("\n\tUSB2.0: %d ports: set usbType = 2 --> EHCI Stack will be used\n", usb2HostNum);
+ if (hc_xhci.interface_supported == MV_TRUE && usb3HostNum > 0)
+ mvOsPrintf("\tUSB3.0: %d ports: set usbType = 3 --> xHCI Stack will be used\n", usb3HostNum);
+ return -1;
+
+}
+
/* usb_lowlevel_init:
* this routine navigate between currently selected stack (eHCI/xHCI)
@@ -205,10 +207,14 @@
* usbType = 3 -- > xHCI
* - Call usb_lowlevel_init from selected stack
*/
+
+/* mark detected usb port, to ensure proper 'stop'
+ * process before next detection request */
+int currentUsbActive = -1;
int usb_lowlevel_init(int index, void **controller)
{
int usb2HostNum, usb3HostNum, usbType, usbActive = 0;
-
+ usbActive = simple_strtoul(getenv("usbActive"), NULL, 10);
usbType = simple_strtoul(getenv("usbType"), NULL, 10);
usb3HostNum = mvCtrlUsb3HostMaxGet();
usb2HostNum = mvCtrlUsbMaxGet();
@@ -216,95 +222,70 @@
switch (usbType) {
case 2:
if (hc_ehci.interface_supported == MV_TRUE && usb2HostNum > 0) {
- usbActive = getUsbActive(USB_UNIT_ID, usb2HostNum, 0, MV_TRUE); /* read requested active port */
+ usbActive = mvCtrlUsbMapGet(USB_UNIT_ID, usbActive);
+ if (mvBoardIsUsbPortConnected(USB_UNIT_ID, usbActive) == MV_FALSE)
+ return printUsbError(MV_FALSE, usbActive);
hc = &hc_ehci; /* set Host Controller struct for function pointers */
} else
- goto input_error;
+ return printUsbError(MV_TRUE, usbActive);
break;
case 3:
if (hc_xhci.interface_supported == MV_TRUE && usb3HostNum > 0) {
- usbActive = getUsbActive(USB3_UNIT_ID, usb3HostNum , mvCtrlUsb3MaxGet(),
- MV_TRUE); /* read requested active port */
+ /* mvCtrlUsbMapGet used only for legacy devices ALP/A375 */
+ usbActive = mvCtrlUsbMapGet(USB3_UNIT_ID, usbActive);
+ if (mvBoardIsUsbPortConnected(USB3_UNIT_ID, usbActive) == MV_FALSE)
+ return printUsbError(MV_FALSE, usbActive);
+ if (mvCtrlIsUsbSerDesConnected(usbActive) == MV_FALSE) {
+ mvOsPrintf("\n'usbActive' warning (%d): Invalid USB3.0 port (no valid SerDes)..", usbActive);
+ mvOsPrintf("Trying USB2.0 Host via USB3.0\n");
+ }
+#ifdef MV_USB_VBUS_CYCLE
+ /* VBUS signal is lowered prior to SerDes initialization sequence,
+ * before initializing and detecting device, set VBUS enabled */
+ mvBoardUsbVbusSet(usbActive);
+#endif
hc = &hc_xhci; /* set Host Controller struct for function pointers */
} else
- goto input_error;
+ return printUsbError(MV_TRUE, usbActive);
break;
default:
- goto input_error;
+ return printUsbError(MV_TRUE, usbActive);
+ }
+ mvOsPrintf("Port (usbActive) : %d\tInterface (usbType = %d) : ", usbActive,
+ ((usbType == 3) ? 3 : 2));
+
+ /* Make sure that usbActive never exeeds the configured max controllers count
+ The CONFIG_USB_MAX_CONTROLLER_COUNT can be changed for different boards */
+ if (usbActive >= CONFIG_USB_MAX_CONTROLLER_HOST_COUNT) {
+ mvOsPrintf("usbActive=%d is out of supported range\n",usbActive);
+ return -1;
}
+ /* Marvell USB code supports only one active controller (USB0), while the actual host
+ device is selected by usbActive environment variable */
+ if (index > 0) {
+ mvOsPrintf("\nOnly one active controller supported! Skipping USB%d initialization.\n", index);
+ return -1;
+ }
+
+ currentUsbActive = usbActive;
return hc->hc_usb_lowlevel_init(usbActive, controller);
-
-input_error:
- mvOsPrintf("Error: requested 'usbType' (Type %d) is not supported", usbType);
- if ((usbType == 2 && usb2HostNum < 1) || (usbType ==3 && usb3HostNum < 1))
- mvOsPrintf(" (no available USB ports).\n");
-
- if ((hc_ehci.interface_supported == MV_TRUE && usb2HostNum > 0) ||
- (hc_xhci.interface_supported == MV_TRUE && usb3HostNum > 0))
- mvOsPrintf("\n\n\t Supported Units:\n");
- if (hc_ehci.interface_supported == MV_TRUE && usb2HostNum > 0)
- mvOsPrintf("\n\tUSB2.0: %d ports: set usbType = 2 --> EHCI Stack will be used\n", usb2HostNum);
- if (hc_xhci.interface_supported == MV_TRUE && usb3HostNum > 0)
- mvOsPrintf("\tUSB3.0: %d ports: set usbType = 3 --> xHCI Stack will be used\n", usb3HostNum);
- return -1;
}
int usb_lowlevel_stop(int index)
{
- int usb2UnitNum, usb3UnitNum, usbType, usbActive = 0;
+ int usbActive = currentUsbActive, ret;
if (!hc) {
mvOsPrintf("%s: Error: run 'usb reset' to set host controller interface.\n", __func__);
return -1;
}
- usbType = simple_strtoul(getenv("usbType"), NULL, 10);
- usb3UnitNum = mvCtrlUsb3MaxGet();
- usb2UnitNum = mvCtrlUsbMaxGet();
-
- switch (usbType) {
- case 2:
- if (hc != &hc_ehci) {
- mvOsPrintf("Error - Please run \"usb stop\" before changing \"usbType\".\n");
- return 0;
- }
- if (hc_ehci.interface_supported == MV_TRUE && usb2UnitNum > 0)
- usbActive = getUsbActive(USB_UNIT_ID, usb2UnitNum, 0,
- MV_FALSE); /* read requested active port */
- else
- goto input_error;
- break;
- case 3:
- if (hc != &hc_xhci) {
- mvOsPrintf("Error - Please run \"usb stop\" before changing \"usbType\".\n");
- return 0;
- }
- if (hc_xhci.interface_supported == MV_TRUE && usb3UnitNum > 0)
- usbActive = getUsbActive(USB3_UNIT_ID, usb3UnitNum, mvCtrlUsb3MaxGet(),
- MV_FALSE); /* read requested active port */
- else
- goto input_error;
- break;
- default:
- goto input_error;
- }
-
- return hc->hc_usb_lowlevel_stop(usbActive);
-input_error:
- mvOsPrintf("Error: requested 'usbType' (Type %d) is not supported", usbType);
- if ((usbType == 2 && usb2UnitNum < 1) || (usbType == 3 && usb3UnitNum < 1))
- mvOsPrintf(" (no available USB ports).\n");
-
- if ((hc_ehci.interface_supported == MV_TRUE && usb2UnitNum > 0) ||
- (hc_xhci.interface_supported == MV_TRUE && usb3UnitNum > 0))
- mvOsPrintf("\n\n\t Supported Units:\n");
- if (hc_ehci.interface_supported == MV_TRUE && usb2UnitNum > 0)
- mvOsPrintf("\n\tUSB2.0: %d ports: set usbType = 2 --> EHCI Stack will be used\n", usb2UnitNum);
- if (hc_xhci.interface_supported == MV_TRUE && usb3UnitNum > 0)
- mvOsPrintf("\tUSB3.0: %d ports: set usbType = 3 --> xHCI Stack will be used\n", usb3UnitNum);
- return -1;
-
+ /* Mark that there is no current usbActive to stop */
+ currentUsbActive = -1;
+ ret = hc->hc_usb_lowlevel_stop(usbActive);
+ hc = NULL;
+ return ret;
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
diff --git a/board/mv_ebu/common/USP/switchingServices/sar_bc2.c b/board/mv_ebu/common/USP/switchingServices/sar_bc2.c
new file mode 100755
index 0000000..714865d
--- /dev/null
+++ b/board/mv_ebu/common/USP/switchingServices/sar_bc2.c
@@ -0,0 +1,478 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+
+*******************************************************************************/
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <net.h>
+#include <spi_flash.h>
+#include <bzlib.h>
+
+#include "mvCommon.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "boardEnv/mvBoardEnvLib.h"
+#include "cpu/mvCpu.h"
+
+#if defined(MV_INC_BOARD_NOR_FLASH)
+#include "norflash/mvFlash.h"
+#endif
+
+#if defined(MV_INCLUDE_GIG_ETH)
+#include "eth-phy/mvEthPhy.h"
+#endif
+
+#if defined(MV_INCLUDE_PEX)
+#include "pex/mvPex.h"
+#endif
+
+#if defined(MV_INCLUDE_PDMA)
+#include "pdma/mvPdma.h"
+#include "mvSysPdmaApi.h"
+#endif
+
+#if defined(MV_INCLUDE_XOR)
+#include "xor/mvXorRegs.h"
+#include "xor/mvXor.h"
+#endif
+
+#if defined(MV_INCLUDE_PMU)
+#include "pmu/mvPmuRegs.h"
+#endif
+
+#include "cntmr/mvCntmrRegs.h"
+#include "switchingServices.h"
+
+/* defines */
+#undef MV_DEBUG
+#ifdef MV_DEBUG
+#define DB(x) x
+#define DB1(x) x
+#else
+#define DB(x)
+#define DB1(x)
+#endif
+
+/* SAR defines when Connected to Bc2*/
+#define MV_BOARD_CTRL_I2C_ADDR_BC2 0x0
+#define TWSI_CHANNEL_BC2 0
+#define TWSI_SPEED_BC2 20000 // wa for bits 1,2 in 0x4c. Mmust lower 100000 -> 20000 . adiy, erez
+typedef volatile unsigned long VUL;
+
+static MV_U8 tread_bc2(MV_U8 addr, int reg)
+{
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+ MV_U8 data;
+
+ DB(printf("tread_bc2, DevAddr = 0x%x\n", addr));
+
+ /* TWSI init */
+ slave.address = MV_BOARD_CTRL_I2C_ADDR_BC2;
+ slave.type = ADDR7_BIT;
+
+ mvTwsiInit (TWSI_CHANNEL_BC2, TWSI_SPEED_BC2, mvBoardTclkGet(), &slave, 0);
+
+ /* read SatR */
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.slaveAddr.address = addr ;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = reg;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if (MV_OK != mvTwsiRead(TWSI_CHANNEL_BC2, &twsiSlave, &data, 1)) {
+ DB(printf("tread_bc2 : twsi read fail\n"));
+ return MV_ERROR;
+ }
+ DB(printf("tread_bc2: twsi read succeeded, data = 0x%x\n", data));
+
+ return data;
+}
+
+static MV_STATUS twrite_bc2(MV_U8 addr, int reg, MV_U8 regVal)
+{
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+ MV_U8 data;
+
+ // printf(">>> in twrite_bc2, addr=0x%x, reg = 0x%x, val=0x%x\n", addr, reg, regVal);
+ /* TWSI init */
+ slave.address = MV_BOARD_CTRL_I2C_ADDR_BC2;
+ slave.type = ADDR7_BIT;
+
+ mvTwsiInit (TWSI_CHANNEL_BC2, TWSI_SPEED_BC2, mvBoardTclkGet(), &slave, 0);
+
+ /* write SatR */
+ twsiSlave.slaveAddr.address = addr;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = reg;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ data = regVal;
+ if (MV_OK != mvTwsiWrite(TWSI_CHANNEL_BC2, &twsiSlave, &data, 1)) {
+ DB(mvOsPrintf("twrite_bc2: twsi write fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("twrite_bc2: twsi write succeeded\n"));
+
+ return MV_OK;
+}
+
+static int do_sar_list_bc2(int argc, char *const argv[])
+{
+ const char *cmd;
+ int all = 0;
+
+ if (argc < 1)
+ goto usage;
+ cmd = argv[0];
+
+ if (strcmp(cmd, "all") == 0)
+ all = 1;
+
+ if ((strcmp(cmd, "corefreq") == 0) || all) {
+ printf("corefreq (0x4d 0:3): Determines the CORE frequency:\n");
+ printf("\t0x0 = 360MHz\n");
+ printf("\t0x1 = 220MHz\n");
+ printf("\t0x2 = 250MHz\n");
+ printf("\t0x3 = 400MHz\n");
+ printf("\t0x4 = 500MHz\n");
+ printf("\t0x5 = 520MHz\n");
+ printf("\t0x6 = 450MHz\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "cpufreq") == 0) || all) {
+ printf("cpufreq (0x4d 3:4 + 0x4e 0:0): Determines the CPU and DDR frequencies:\n");
+ printf("\t0x0 = CPU 400MHz, DDR 400MHz\n");
+ printf("\t0x2 = CPU 667MHz, DDR 667MHz\n");
+ printf("\t0x3 = CPU 800MHz, DDR 800MHz\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "tmfreq") == 0) || all) {
+ printf("tmfreq (0x4e 1:3): Determines the boot selection:\n");
+ printf("\t0x0 = TM clock is disabled\n");
+ printf("\t0x1 = TM runs 400MHZ, DDR3 runs 800MHz\n");
+ printf("\t0x2 = TM runs 466MHZ, DDR3 runs 933MHz\n");
+ printf("\t0x3 = TM runs 333MHZ, DDR3 runs 667MHz\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "bootsel") == 0) || all) {
+ printf("bootsel (0x4f 0:2): Determines the TM frequency:\n");
+ printf("\t0x0 = BootROM enabled, Boot from Device(NOR) flash\n");
+ printf("\t0x1 = BootROM enabled, Boot from NAND flash (new NF controller on DEV_CSn[0])\n");
+ printf("\t0x2 = BootROM enabled, boot from UART\n");
+ printf("\t0x3 = BootROM enabled, boot from SPI0(CS0)\n");
+ printf("\t0x5 = BootROM enabled, Standby slave. Must set PCIs as endpoint (i.e. CPU IDLE)\n");
+ printf("\t0x6 = BootROM enabled, UART debug prompt mode\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "jtagcpu") == 0) || all) {
+ printf("jtagcpu (0x4f 3:3): Determines the JTAG to CPU connection:\n");
+ printf("\t0x0 = JTAG is connected to C3M CPU\n");
+ printf("\t0x1 = JTAG is connected to MSYS CPU\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "ptppll") == 0) || all) {
+ printf("ptppll (0x4f 4:4): Determines the ptppll:\n");
+ printf("\t0x1 = Must write 0x1. PTP PLL runs @ 1093.75MHz, PTP Clock = 546.875MHz\n");
+ printf("\n");
+ }
+
+ if ((strcmp(cmd, "pciegen1") == 0) || all) {
+ printf("pciegen1 (0x4c.1 4:4): Determines the pciegen1:\n");
+ printf("\t0x0 = Do not force BC2 PCIe connection to GEN1\n");
+ printf("\t0x1 = Force BC2 PCIe connection to GEN1\n");
+ printf("\n");
+ }
+
+ return 0;
+
+ usage:
+ printf("Usage: Satr - see options\n");
+ return 1;
+}
+
+static int do_sar_read_bc2(int argc, char *const argv[])
+{
+
+/*
+ bc2 sample and reset register
+
+# 4f # 4e # 4d # 4c #
+# # # # #
+#--|--|--|--|--#--|--|--|--|--#--|--|--|--|--#--|--|--|--|--#
+# | | | | # | | | | # | | | | # | | | | #
+#--|--|--|--|--#--|--|--|--|--#--|--|--|--|--#--|--|--|--|--#
+# | # | | # | # #
+#-P|-R|bootsel-#-R|-TM-f---|-CPU-f--|-CORE-f-#-----devid----#
+
+
+*/
+
+ const char *cmd;
+ volatile uint satr_reg;
+
+ cmd = argv[0];
+
+ if (strcmp(cmd, "dump") == 0) {
+ satr_reg =
+ ((tread_bc2(0x4c, 0)&0x1f) << 0) | // 5 bits
+ ((tread_bc2(0x4d, 0)&0x1f) << 5) |
+ ((tread_bc2(0x4e, 0)&0x1f) << 10) |
+ ((tread_bc2(0x4f, 0)&0x1f) << 15);
+ printf("BC2 S@R raw register = 0x%08x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "devid") == 0) {
+ satr_reg = tread_bc2(0x4c, 0) & 0x1f;
+ printf("BC2 S@R devid = 0x%02x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "corefreq") == 0) {
+ satr_reg = tread_bc2(0x4d, 0) & 0x07;
+ printf("BC2 S@R corefreq = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "cpufreq") == 0) {
+ satr_reg = ((tread_bc2(0x4d, 0) & 0x18) >> 3) | ((tread_bc2(0x4e, 0) & 0x01) << 2);
+ printf("BC2 S@R cpufreq = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "tmfreq") == 0) {
+ satr_reg = (tread_bc2(0x4e, 0) & 0x0e) >> 1;
+ printf("BC2 S@R tmfreq = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "bootsel") == 0) {
+ satr_reg = tread_bc2(0x4f, 0) & 0x07;
+ printf("BC2 S@R bootsel = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "jtagcpu") == 0) {
+ satr_reg = (tread_bc2(0x4f, 0) & 0x08) >> 3;
+ printf("BC2 S@R jtagcpu = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "ptppll") == 0) {
+ satr_reg = (tread_bc2(0x4f, 0) & 0x10) >> 4;
+ printf("BC2 S@R ptppll = 0x%x\n", satr_reg);
+ }
+
+ else if (strcmp(cmd, "pciegen1") == 0) {
+ satr_reg = (tread_bc2(0x4c, 1) & 0x10) >> 4;
+ printf("BC2 S@R pciegen1 = 0x%x\n", satr_reg);
+ }
+
+ return 0;
+}
+
+static int do_sar_write_bc2(int argc, char *const argv[])
+{
+ const char *cmd;
+ volatile uint satr_reg;
+ volatile int bit_mask;
+
+ cmd = argv[0];
+
+ if (strcmp(cmd, "devid") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x1f);
+ twrite_bc2(0x4c, 0, (MV_U8)bit_mask);
+ }
+
+ else if (strcmp(cmd, "corefreq") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x07);
+ satr_reg = tread_bc2(0x4d, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x18) | bit_mask;
+ twrite_bc2(0x4d, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "cpufreq") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x07);
+ satr_reg = tread_bc2(0x4d, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x07) | ((bit_mask & 0x03) << 3);
+ twrite_bc2(0x4d, 0, (MV_U8)satr_reg);
+
+ satr_reg = tread_bc2(0x4e, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x1e) | ((bit_mask & 0x04) >> 2);
+ twrite_bc2(0x4e, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "tmfreq") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x07);
+ satr_reg = tread_bc2(0x4e, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x11) | (bit_mask << 1);
+ twrite_bc2(0x4e, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "bootsel") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x07);
+ satr_reg = tread_bc2(0x4f, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x18) | bit_mask;
+ twrite_bc2(0x4f, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "jtagcpu") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x01);
+ satr_reg = tread_bc2(0x4f, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x17) | (bit_mask << 3);
+ twrite_bc2(0x4f, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "ptppll") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x01);
+ satr_reg = tread_bc2(0x4f, 0) & 0x1f;
+ satr_reg = (satr_reg & 0x0f) | (bit_mask << 4);
+ twrite_bc2(0x4f, 0, (MV_U8)satr_reg);
+ }
+
+ else if (strcmp(cmd, "pciegen1") == 0) {
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x01);
+ satr_reg = tread_bc2(0x4c, 1) & 0x1f;
+ satr_reg = (satr_reg & 0x0f) | (bit_mask << 4);
+ twrite_bc2(0x4c, 1, (MV_U8)satr_reg);
+ }
+
+ return 0;
+}
+
+
+
+MV_STATUS check_twsi_bc2(void)
+{
+ MV_U8 reg = tread_bc2(0x4c, 0);
+ DB(printf("\ncheck_twsi_bc2: read_BC2= 0x%x\n", reg));
+ if (reg == 0xff)
+ return MV_ERROR;
+ else
+ return MV_OK;
+}
+
+int do_sar_bc2(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+
+ const char *cmd;
+
+ /* need at least two arguments */
+ if (argc < 2)
+ goto usage;
+
+ cmd = argv[1];
+
+ if (check_twsi_bc2() == MV_ERROR) {
+ printf("BC2 twsi channel not connected\n");
+ return 1;
+ }
+
+
+ if (strcmp(cmd, "list") == 0)
+ return do_sar_list_bc2(argc - 2, argv + 2);
+
+ else if (strcmp(cmd, "read") == 0)
+ return do_sar_read_bc2(argc - 2, argv + 2);
+
+
+ else if (strcmp(cmd, "write") == 0) {
+ if (do_sar_write_bc2(argc - 2, argv + 2) == 0) {
+ do_sar_read_bc2(argc - 2, argv + 2);
+ }
+ return 0;
+
+ }
+
+ usage:
+ printf("\n");
+ printf("BC2 Sample At Reset sub-system\n");
+ printf("SatR list corefreq - print corefreq list\n");
+ printf("SatR list cpufreq - print cpufreq list\n");
+ printf("SatR list tmfreq - print tmfreq list\n");
+ printf("SatR list bootsel - print boolsel list\n");
+ printf("SatR list jtagcpu - print jtagcpu list\n");
+ printf("SatR list ptppll - print ptppll list\n");
+ printf("SatR list pciegen1 - print pciegen1 list\n");
+
+ printf("\n");
+
+ printf("SatR read devid - read device id\n");
+ printf("SatR read corefreq - read CORE frequency\n");
+ printf("SatR read cpufreq - read CPU frequency\n");
+ printf("SatR read tmfreq - read TM frequency\n");
+ printf("SatR read bootsel - read Boot select\n");
+ printf("SatR read jtagcpu - read JTAG CPU selection\n");
+ printf("SatR read ptppll - read PTP PLL setting\n");
+ printf("SatR read pciegen1 - read Force PCIe GEN1 setting\n");
+ printf("SatR read dump - read all values\n");
+ printf("\n");
+
+ printf("SatR write devid <val> - write device id\n");
+ printf("SatR write corefreq <val> - write CORE frequency\n");
+ printf("SatR write cpufreq <val> - write CPU frequency\n");
+ printf("SatR write tmfreq <val> - write TM frequency\n");
+ printf("SatR write bootsel <val> - write Boot select\n");
+ printf("SatR write jtagcpu <val> - write JTAG CPU selection\n");
+ printf("SatR write ptppll <val> - write PTP PLL setting\n");
+ printf("SatR write pciegen1 <val> - write Force PCIe GEN1 setting\n");
+
+ return 1;
+}
+
+#ifndef MV_MSYS
+/* This function used for AMC + remote MSYS case. The MSYS standalone implementation differs */
+static int do_qsgmii_sel(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+
+ int bit_mask;
+
+ if (argc < 2)
+ goto usage;
+
+ if (check_twsi_bc2() == MV_ERROR) {
+ printf("BC2 twsi channel not connected\n");
+ return 1;
+ }
+
+ bit_mask = (simple_strtoul(argv[1], NULL, 16) & 0x0000ffff);
+
+ twrite_bc2(0x20, 2, (MV_U8)((bit_mask >> 0) & 0xff));
+ twrite_bc2(0x20, 3, (MV_U8)((bit_mask >> 8) & 0xff));
+ twrite_bc2(0x20, 6, 0x0);
+ twrite_bc2(0x20, 7, 0x0);
+ return 1;
+
+ usage:
+ cmd_usage(cmdtp);
+ return 1;
+}
+
+
+U_BOOT_CMD(
+ qsgmii_sel, 2, 1, do_qsgmii_sel,
+ " Select SFP or QSGMII modes on bc2.\n",
+ " apply 16 bit array to select SFP or QSGMII modes"
+ );
+
+#endif
+
+
diff --git a/board/mv_ebu/common/USP/switchingServices/switchingServices.c b/board/mv_ebu/common/USP/switchingServices/switchingServices.c
index 5885aaf..8a5b5cc 100755
--- a/board/mv_ebu/common/USP/switchingServices/switchingServices.c
+++ b/board/mv_ebu/common/USP/switchingServices/switchingServices.c
@@ -246,6 +246,19 @@
"\n - print information for all SPI FLASH memory banks\n"
);
+static int isSwitchingServicesSupported(void)
+{
+ MV_U32 family = mvCtrlDevFamilyIdGet(0);
+
+ /* enable command only for AC3 & BC2 & AMC boards */
+ if (!((family >= MV_ALLEYCAT3_DEV_ID && family <= MV_ALLEYCAT3_MAX_DEV_ID)
+ || family == MV_BOBCAT2_DEV_ID || mvBoardisAmc())) {
+ printf("Command not supported for this SoC/Board\n");
+ return 0;
+ }
+ return 1;
+}
+
/*******************************************************************************
* do_cpss_env - Save CPSS enviroment on flash
*
@@ -263,6 +276,9 @@
{
char buf[1024];
+ if (!isSwitchingServicesSupported())
+ return 0;
+
printf("Saving cpss environment variable\n");
setenv("standalone", "");
setenv("bootcmd", "run standalone_mtd");
@@ -277,7 +293,7 @@
"console=${consoledev},${baudrate} ${othbootargs} ${linux_parts}; tftp ${linux_loadaddr} "
"${image_name};bootm ${linux_loadaddr}");
- sprintf(buf,"'spi_flash:%dm(spi_uboot)ro,%dm(spi_kernel),%dm(spi_rootfs),-(remainder)"
+ sprintf(buf,"'mtdparts=spi_flash:%dm(spi_uboot)ro,%dm(spi_kernel),%dm(spi_rootfs),-(remainder)"
";armada-nand:%dm(nand_kernel),-(nand_rootfs)'", CFG_APPL_FLASH_PART_UBOOT_SIZE / _1M,
CFG_APPL_SPI_FLASH_PART_KERNEL_SIZE / _1M, CFG_APPL_SPI_FLASH_PART_ROOTFS_SIZE / _1M,
CFG_APPL_NAND_FLASH_PART_KERNEL_SIZE / _1M);
@@ -290,7 +306,7 @@
sprintf(buf,
"sf probe; sf read ${loadaddr} 0x%x 0x%x; setenv bootargs ${console} "
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off "
- "root=/dev/mtdblock2 rw init=/linuxrc rootfstype=jffs2 rootwait mtdparts=${mtdparts} "
+ "root=/dev/mtdblock2 rw init=/linuxrc rootfstype=jffs2 rootwait ${mtdparts} "
"${mvNetConfig}; bootm ${loadaddr} ",
CFG_APPL_SPI_FLASH_PART_KERNEL_START, CFG_APPL_SPI_FLASH_PART_KERNEL_SIZE);
#ifndef MV_NAND
@@ -304,7 +320,7 @@
#ifdef MV_NAND
sprintf(buf,
- "nand read ${loadaddr} 0x%x 0x%x; setenv bootargs ${console} mtdparts=${mtdparts} "
+ "nand read ${loadaddr} 0x%x 0x%x; setenv bootargs ${console} ${mtdparts} "
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off "
"ubi.mtd=5 root=ubi0:rootfs_nand ro rootfstype=ubifs ${mvNetConfig}; bootm 0x2000000;" ,
CFG_APPL_NAND_FLASH_PART_KERNEL_START,
@@ -324,7 +340,9 @@
""
);
+#if defined(MV_INCLUDE_SPI)
extern struct spi_flash *flash;
+#endif
struct partitionInformation nandInfo = {
.defaultImage = "ubifs_arm_nand.image",
@@ -355,8 +373,11 @@
sprintf(cmdBuf, "nand write.trimffs %x %x %x\n", source, destination, len);
printf(cmdBuf);
run_command(cmdBuf, 0);
- } else
+ }
+#if defined(MV_INCLUDE_SPI)
+ else
spi_flash_write(flash, destination, len, (const void *)source);
+#endif
}
void flashErase (MV_U32 destination, MV_U32 len, MV_BOOL isNand)
@@ -366,14 +387,16 @@
sprintf(cmdBuf, "nand erase %x %x\n", destination, len);
printf(cmdBuf);
run_command(cmdBuf, 0);
- } else
+ }
+#if defined(MV_INCLUDE_SPI)
+ else
spi_flash_erase(flash, destination, len);
-
+#endif
}
static int do_mtdburn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- MV_U32 i, filesize, addr, src_addr, dest_addr;
+ MV_U32 i, addr, src_addr, dest_addr;
MV_U32 kernel_unc_len, rootfs_unc_len = 0, unc_len, src_len;
MV_U32 kernel_addr = CFG_DEF_KERNEL_DEST_ADDR;
MV_U32 rootfs_addr = CFG_DEF_ROOTFS_DEST_ADDR;
@@ -385,7 +408,10 @@
MV_U32 fsys = FS_TYPE_FAT; /* default FS = FAT */
MV_BOOL isNand = MV_TRUE; /* default destination = NAND */
addr = load_addr = CFG_DEF_SOURCE_LOAD_ADDR;
- int fileSizeFromRam = -1;
+ int filesize, fileSizeFromRam = -1;
+
+ if (!isSwitchingServicesSupported())
+ return 0;
/* scan for flash destination in arguments (allowing usage of only 'mtdburn spi') */
for (i = 1 ; i < argc ; i++) {
@@ -403,30 +429,29 @@
fileSizeFromRam = simple_strtoul(argv[6], NULL, 16);
case 6:/* arg#6 is flash destination, scanned previously --> fall to 5*/
case 5:
- copy_filename (BootFile, argv[4], sizeof(BootFile));
+ if(strcmp(argv[4], "EXT2") == 0)
+ fsys = FS_TYPE_EXT;
/* fall to 4*/
case 4:
- if(strcmp(argv[3], "EXT2") == 0)
- fsys = FS_TYPE_EXT;
+ devPart = argv[3];
/* fall to 3*/
case 3:
- devPart = argv[2];
- /* fall to 2*/
- case 2:
- if(strcmp(argv[1], "usb") == 0)
+ if(strcmp(argv[2], "usb") == 0)
loadfrom = 1;
- else if(strcmp(argv[1], "mmc") == 0)
+ else if(strcmp(argv[2], "mmc") == 0)
loadfrom = 2;
- else if(strcmp(argv[1], "ram") == 0) {
+ else if(strcmp(argv[2], "ram") == 0) {
loadfrom = 3;
if (devPart != NULL)
addr = load_addr = (unsigned int)simple_strtoul(devPart, NULL, 16);
}
if ((loadfrom == 1 || loadfrom == 2) && devPart == NULL) /* if using USB/MMC, and not selected interface num */
devPart = "0"; /* default interface number is 0 */
- /* fall to 1*/
+ /* fall to 2*/
+ case 2:
+ copy_filename (BootFile, argv[1], sizeof(BootFile));
case 1: /* no parameter all default */
- if(argc < 4)
+ if (argc < 2)
copy_filename (BootFile, partitionInfo->defaultImage, sizeof(BootFile));
break;
default:
@@ -451,12 +476,19 @@
if (mvVerifyRequest() == MV_FALSE)
return 0;
- if (isNand == MV_FALSE && !flash) {
- flash = spi_flash_probe(0, 0, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+ if (isNand == MV_FALSE) {
+#if defined(MV_INCLUDE_SPI)
if (!flash) {
- printf("Failed to probe SPI Flash\n");
- return 0;
+ flash = spi_flash_probe(0, 0, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+ if (!flash) {
+ printf("Failed to probe SPI Flash\n");
+ return 0;
+ }
}
+#else
+ printf("SPI Flash is not supported\n");
+ return 0;
+#endif
}
/* Fetch requested file, filesize is needed for single image only */
@@ -551,10 +583,11 @@
}
/* Erase entire NAND flash - avoid invalid file system preparations */
- printf("\nGoing to erase the entire NAND flash. ");
- if (mvVerifyRequest() == MV_TRUE)
- run_command("nand erase.chip", 0);
-
+ if (isNand == MV_TRUE) {
+ printf("\nGoing to erase the entire NAND flash. ");
+ if (mvVerifyRequest() == MV_TRUE)
+ run_command("nand erase.chip", 0);
+ }
printf("\nBurning %s on flash at 0x%08x, length=%dK\n",
(single_file) ? "single image" : "kernel",
partitionInfo->KERNEL_START, kernel_unc_len/_1K);
@@ -593,14 +626,15 @@
U_BOOT_CMD(
mtdburn, 6, 1, do_mtdburn,
"Burn a Linux image and Filesystem` on the NAND/SPI flash.\n",
- "[interface [<dev[:part]> [File system [filename]]]] [flash destination] [single file size on RAM]\n"
+ "[filename [interface [<dev[:part]> [File system]]]] [flash destination] [single file size on RAM]\n"
"\tinterface : ram <load address>, tftp, or mmc/usb <interface_num> (default is tftp)\n"
"\tFile system: FAT or EXT2 (default is FAT).\n"
"\tNAND default file-name is ubifs_arm_nand.image.\n"
"\tSPI default file-name is jffs2_arm.image.\n"
"\tFlash Destination: nand or spi (default is nand). \n"
- "\te.g. MMC: 'mtdburn mmc 0 FAT ubifs_arm_nand.image nand'\n"
- "\te.g. RAM: 'mtdburn ram 5000000 nand'\n"
+ "\te.g. TFTP: 'mtdburn ubifs_arm_nand.image'\n"
+ "\te.g. MMC: 'mtdburn ubifs_arm_nand.image mmc 0 FAT nand'\n"
+ "\te.g. RAM: 'mtdburn ubifs_arm_nand.image ram 5000000 nand'\n"
);
@@ -791,6 +825,7 @@
return silt;
}
+#ifdef MV_MSYS
static int do_qsgmii_sel(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -821,6 +856,7 @@
" Select SFP or QSGMII modes on bc2.\n",
" apply 16 bit array to select SFP or QSGMII modes"
);
+#endif
void hwServicesLateInit(void)
{
diff --git a/board/mv_ebu/common/USP/switchingServices/switchingServices.h b/board/mv_ebu/common/USP/switchingServices/switchingServices.h
index ab40daa..38e21d4 100755
--- a/board/mv_ebu/common/USP/switchingServices/switchingServices.h
+++ b/board/mv_ebu/common/USP/switchingServices/switchingServices.h
@@ -143,10 +143,10 @@
SILT_NP5,
SILT_BC2,
SILT_OTHER,
- SLIC_NOT_DETECT = 0x5a5a
+ SILT_NOT_DETECT = 0x5a5a
} SILICON_TYPE;
SILICON_TYPE get_attached_silicon_type(void);
int do_sar_bc2(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
-
+void hwServicesLateInit(void);
#endif
diff --git a/board/mv_ebu/common/common/mvCommon.h b/board/mv_ebu/common/common/mvCommon.h
index 405fd3c..bc5ef84 100644
--- a/board/mv_ebu/common/common/mvCommon.h
+++ b/board/mv_ebu/common/common/mvCommon.h
@@ -231,6 +231,7 @@
#define _2G 0x80000000
/* Tclock and Sys clock define */
+#define _50MHz 50000000
#define _100MHz 100000000
#define _125MHz 125000000
#define _133MHz 133333334
diff --git a/board/mv_ebu/common/common/mvDeviceId.h b/board/mv_ebu/common/common/mvDeviceId.h
index 4c84e15..ddcb503 100644
--- a/board/mv_ebu/common/common/mvDeviceId.h
+++ b/board/mv_ebu/common/common/mvDeviceId.h
@@ -400,6 +400,10 @@
#define MV_6811_DEV_ID 0x6811
#define MV_6820_DEV_ID 0x6820
#define MV_6828_DEV_ID 0x6828
+#define MV_6W22_DEV_ID 0x6823 /* 6W22=A383 */
+#define MV_6W23_DEV_ID 0x6824 /* 6W23=A384 */
+#define MV_6W22_DEV_NAME "6W22"
+#define MV_6W23_DEV_NAME "6W23"
/* A38x revisions */
#define MV_88F68XX_Z1_ID 0x0
@@ -438,11 +442,46 @@
MV_BOBCAT2_B0_NAME,\
}
+/* BobK Family */
+#define MV_BOBK_DEV_ID 0xBC00
+
+/* BobK deivces matrix */
+#define MV_BOBK_CETUS_98DX4235_DEV_ID 0xBE00
+#define MV_BOBK_CAELUM_98DX4203_DEV_ID 0xBC00
+#define MV_BOBK_LEWIS_98DX8212_DEV_ID 0xBE10
+
+/* BobK Revisions */
+#define MV_BOBK_A0_ID 0x0
+#define MV_BOBK_A0_NAME "A0"
+
+#define MV_BOBK_ID_ARRAY { \
+ MV_BOBK_A0_NAME,\
+}
+
/* Lion2 Family */
#define MV_LION2_DEV_ID 0x8000
/* AlleyCat3 Family */
#define MV_ALLEYCAT3_DEV_ID 0xF400
+#define MV_ALLEYCAT3_MAX_DEV_ID 0xF4FF
+
+/* AlleyCat3/Pomcat3 deivces matrix */
+#define MV_ALLEYCAT3_98DX3336_DEV_ID 0xF400
+#define MV_ALLEYCAT3_98DX3335_DEV_ID 0xF401
+#define MV_ALLEYCAT3_98DX3334_DEV_ID 0xF402
+#define MV_ALLEYCAT3_98DX3333_DEV_ID 0xF403
+#define MV_ALLEYCAT3_98DX1233_DEV_ID 0xF408
+#define MV_ALLEYCAT3_98DX1235_DEV_ID 0xF409
+#define MV_ALLEYCAT3_98DX3236_DEV_ID 0xF410
+#define MV_ALLEYCAT3_98DX3235_DEV_ID 0xF411
+#define MV_ALLEYCAT3_98DX3234_DEV_ID 0xF412
+#define MV_ALLEYCAT3_98DX3233_DEV_ID 0xF413
+#define MV_ALLEYCAT3_98DXH333_DEV_ID 0xF414
+#define MV_ALLEYCAT3_98DX1333_DEV_ID 0xF418
+#define MV_ALLEYCAT3_98DX1335_DEV_ID 0xF419
+#define MV_ALLEYCAT3_98DX1336_DEV_ID 0xF41A
+
+#define MV_MAX_DEV_ID 0xFFFF
/* AlleyCat3 Revisions */
#define MV_ALLEYCAT3_A0_ID 0x3
diff --git a/board/mv_ebu/common/mv_hal/cesa/mvCesa.c b/board/mv_ebu/common/mv_hal/cesa/mvCesa.c
index b39a8c5..9973e0c 100644
--- a/board/mv_ebu/common/mv_hal/cesa/mvCesa.c
+++ b/board/mv_ebu/common/mv_hal/cesa/mvCesa.c
@@ -1026,26 +1026,14 @@
return MV_OUT_OF_CPU_MEM;
}
status = mvCesaFragReqProcess(chan, pReq, frag);
- if (status == MV_OK) {
-#if defined(MV_CESA_CHAIN_MODE) || defined(MV_CESA_INT_COALESCING_SUPPORT) || \
- defined(CONFIG_OF)
-#ifdef CONFIG_OF
- if ((mv_cesa_feature == INT_COALESCING) ||
- (mv_cesa_feature == CHAIN)) {
-#endif /* CONFIG_OF */
- if (frag) {
- pReq->dma[frag - 1].pDmaLast->phyNextDescPtr =
- MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf,
- pReq->dma[frag].pDmaFirst));
- mvOsCacheFlush(cesaOsHandle, pReq->dma[frag - 1].pDmaLast,
- sizeof(MV_DMA_DESC));
- }
-#ifdef CONFIG_OF
- }
-#endif /* CONFIG_OF */
-#endif /* MV_CESA_CHAIN_MODE || MV_CESA_INT_COALESCING_SUPPORT || CONFIG_OF*/
- frag++;
+ if (status == MV_OK && frag) {
+ pReq->dma[frag - 1].pDmaLast->phyNextDescPtr =
+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf,
+ pReq->dma[frag].pDmaFirst));
+ mvOsCacheFlush(cesaOsHandle, pReq->dma[frag - 1].pDmaLast,
+ sizeof(MV_DMA_DESC));
}
+ frag++;
}
pReq->frags.numFrag = frag;
@@ -1282,12 +1270,8 @@
MV_U8 *pNewDigest;
int frag;
-#if defined(MV_CESA_CHAIN_MODE) || defined(MV_CESA_INT_COALESCING_SUPPORT) || \
- defined(CONFIG_OF)
pReq->frags.nextFrag = 1;
while (pReq->frags.nextFrag <= pReq->frags.numFrag) {
-#endif
-
frag = (pReq->frags.nextFrag - 1);
/* Restore DMA descriptor list */
@@ -1329,19 +1313,8 @@
}
readyStatus = MV_OK;
}
-#if defined(MV_CESA_CHAIN_MODE) || defined(MV_CESA_INT_COALESCING_SUPPORT) || \
- defined(CONFIG_OF)
-#ifdef CONFIG_OF
- if ((mv_cesa_feature == INT_COALESCING) ||
- (mv_cesa_feature == CHAIN))
pReq->frags.nextFrag++;
- else
- break;
-#else /* CONFIG_OF */
- pReq->frags.nextFrag++;
-#endif /* CONFIG_OF */
}
-#endif /* MV_CESA_CHAIN_MODE || MV_CESA_INT_COALESCING_SUPPORT || CONFIG_OF */
} else {
mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize);
diff --git a/board/mv_ebu/common/mv_hal/neta/gbe/mvNeta.h b/board/mv_ebu/common/mv_hal/neta/gbe/mvNeta.h
index 12519e5..4492814 100644
--- a/board/mv_ebu/common/mv_hal/neta/gbe/mvNeta.h
+++ b/board/mv_ebu/common/mv_hal/neta/gbe/mvNeta.h
@@ -346,6 +346,9 @@
#define MV_NETA_QUEUE_PREV_DESC(pQueueCtrl, descIdx) \
(((descIdx) > 0) ? ((descIdx) - 1) : (pQueueCtrl)->lastDesc)
+#define MV_NETA_RX_LAST_DESC_PTR(pQueueCtrl) \
+ (((NETA_RX_DESC *)pQueueCtrl.pFirst) + pQueueCtrl.lastDesc)
+
typedef struct {
MV_NETA_QUEUE_CTRL queueCtrl;
@@ -622,6 +625,19 @@
return pRxDesc;
}
+/* Get the next desc pointer following current desc */
+static INLINE NETA_RX_DESC *mvNetaRxqNextDescPtr(MV_NETA_RXQ_CTRL *pRxq, NETA_RX_DESC *pRxDesc)
+{
+ NETA_RX_DESC *pNextDesc;
+
+ if (pRxDesc == MV_NETA_RX_LAST_DESC_PTR(pRxq->queueCtrl))
+ pNextDesc = (NETA_RX_DESC *)pRxq->queueCtrl.pFirst;
+ else
+ pNextDesc = ++pRxDesc;
+
+ return pNextDesc;
+}
+
static INLINE NETA_RX_DESC *mvNetaRxqDescGet(MV_NETA_RXQ_CTRL *pRxq)
{
NETA_RX_DESC *pRxDesc;
diff --git a/board/mv_ebu/common/mv_hal/neta/gbe/mvNetaDebug.c b/board/mv_ebu/common/mv_hal/neta/gbe/mvNetaDebug.c
index 368e9a5..37f5e69 100644
--- a/board/mv_ebu/common/mv_hal/neta/gbe/mvNetaDebug.c
+++ b/board/mv_ebu/common/mv_hal/neta/gbe/mvNetaDebug.c
@@ -490,7 +490,7 @@
i, pRxDesc, pRxDesc->status,
pRxDesc->dataSize, (MV_U32) pRxDesc->bufPhysAddr, (MV_U32) pRxDesc->bufCookie);
- mvOsCacheLineInv(NULL, pRxDesc);
+ mvOsCacheLineInv(pPortCtrl->osHandle, pRxDesc);
}
}
}
@@ -541,7 +541,7 @@
i, pTxDesc, pTxDesc->command, pTxDesc->dataSize,
(MV_U32) pTxDesc->bufPhysAddr, pTxDesc->hw_cmd);
- mvOsCacheLineInv(NULL, pTxDesc);
+ mvOsCacheLineInv(pPortCtrl->osHandle, pTxDesc);
}
}
}
diff --git a/board/mv_ebu/common/mv_hal/neta/pnc/mvPnc.c b/board/mv_ebu/common/mv_hal/neta/pnc/mvPnc.c
index 648d6e3..493ec50 100644
--- a/board/mv_ebu/common/mv_hal/neta/pnc/mvPnc.c
+++ b/board/mv_ebu/common/mv_hal/neta/pnc/mvPnc.c
@@ -138,10 +138,7 @@
|| ctrl_model == MV88F6560_DEV_ID) {
/* Armada KW2 ID */
memcpy(&gbe_pnc_map, &gbe_pnc_map_kw2, sizeof(gbe_pnc_map_kw2));
- } else if (ctrl_model == MV88F6810_DEV_ID
- || ctrl_model == MV88F6811_DEV_ID
- || ctrl_model == MV88F6820_DEV_ID
- || ctrl_model == MV88F6828_DEV_ID) {
+ } else if ((ctrl_model & ~0xFF) == MV_88F68XX) {
/* Armada A38x ID */
memcpy(&gbe_pnc_map, &gbe_pnc_map_38x, sizeof(gbe_pnc_map_38x));
} else {
diff --git a/board/mv_ebu/common/mv_hal/qd-dsdt-3.3/src/msapi/gtSysConfig.c b/board/mv_ebu/common/mv_hal/qd-dsdt-3.3/src/msapi/gtSysConfig.c
index bff020f..10d3c7b 100644
--- a/board/mv_ebu/common/mv_hal/qd-dsdt-3.3/src/msapi/gtSysConfig.c
+++ b/board/mv_ebu/common/mv_hal/qd-dsdt-3.3/src/msapi/gtSysConfig.c
@@ -762,6 +762,8 @@
break;
case GT_88E6172:
dev->numOfPorts = 7;
+ dev->maxPorts = 7;
+ dev->maxPhyNum = 5;
dev->validPortVec = (1 << dev->numOfPorts) - 1;
dev->validPhyVec = 0x1F;
dev->validSerdesVec = 0x8000;
diff --git a/board/mv_ebu/common/mv_hal/sata/sata3/mvSata3AddrDec.c b/board/mv_ebu/common/mv_hal/sata/sata3/mvSata3AddrDec.c
index b30d2be0..7b76744 100644
--- a/board/mv_ebu/common/mv_hal/sata/sata3/mvSata3AddrDec.c
+++ b/board/mv_ebu/common/mv_hal/sata/sata3/mvSata3AddrDec.c
@@ -92,7 +92,7 @@
#define MV_SATA3_WIN_BASE_OFFSET 4
#define MV_SATA3_WIN_BASE_MASK (0xFFFFFFF<<MV_SATA3_WIN_BASE_OFFSET)
-#define MV_SATA3_WIN_SIZE_ALIGN _64K
+#define MV_SATA3_WIN_SIZE_ALIGN _1M
MV_TARGET sata3AddrDecPrioTab[] = {
#if defined(MV_INCLUDE_SDRAM_CS0)
@@ -213,19 +213,14 @@
return MV_ERROR;
}
- baseReg = pAddrDecWin->addrWin.baseLow & MV_SATA3_WIN_BASE_MASK;
+ baseReg = (pAddrDecWin->addrWin.baseLow / MV_SATA3_WIN_SIZE_ALIGN);
+ baseReg = (baseReg << MV_SATA3_WIN_BASE_OFFSET) & MV_SATA3_WIN_BASE_MASK;
sizeReg = (pAddrDecWin->addrWin.size / MV_SATA3_WIN_SIZE_ALIGN) - 1;
sizeReg = sizeReg << MV_SATA3_WIN_SIZE_OFFSET;
/* set attributes */
ctrlReg = (pAddrDecWin->attrib << MV_SATA3_WIN_ATTR_OFFSET);
-#ifdef MV88F68XX
- /* Temp WA for A38x: set attribute with IOCC bit enabled:
- * When using Dual CS, disk detection fails without using IOCC bit enabled */
- ctrlReg |= BIT12;
-#endif
-
/* set target ID */
ctrlReg &= ~MV_SATA3_WIN_TARGET_MASK;
ctrlReg |= (pAddrDecWin->targetId << MV_SATA3_WIN_TARGET_OFFSET);
@@ -276,7 +271,8 @@
/* Extract base address and size */
sizeRegVal = (sizeReg & MV_SATA3_WIN_SIZE_MASK) >> MV_SATA3_WIN_SIZE_OFFSET;
pAddrDecWin->addrWin.size = (sizeRegVal + 1) * MV_SATA3_WIN_SIZE_ALIGN;
- pAddrDecWin->addrWin.baseLow = baseReg & MV_SATA3_WIN_BASE_MASK;
+ pAddrDecWin->addrWin.baseLow = (baseReg & MV_SATA3_WIN_BASE_MASK) >> MV_SATA3_WIN_SIZE_OFFSET;
+ pAddrDecWin->addrWin.baseLow *= MV_SATA3_WIN_SIZE_ALIGN;
pAddrDecWin->addrWin.baseHigh = 0;
/* attrib and targetId */
diff --git a/board/mv_ebu/common/mv_hal/spi/mvSpi.c b/board/mv_ebu/common/mv_hal/spi/mvSpi.c
index 62e2364..8a0fbf3 100644
--- a/board/mv_ebu/common/mv_hal/spi/mvSpi.c
+++ b/board/mv_ebu/common/mv_hal/spi/mvSpi.c
@@ -475,6 +475,25 @@
(spiHalData.ctrlModel == MV_6321_DEV_ID))
MV_SPI_REG_BIT_SET(MV_SPI_IF_CONFIG_REG(spiId), BIT14);
+ /* set relaxed SPI_TMISO_SAMPLE settings, in 1 of the following:
+ * 1. Armada 38x/39x: ERRATA FE-9144572: Tclock @ 250MHz & SPI clock @ 50MHz & clkPhase=clockPolLow=1
+ * 2. Alley-Cat3: always, to avoid timing violation with SCLK = 40/50Mhz*/
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) || defined(CONFIG_ALLEYCAT3)
+ MV_U32 timingReg;
+#ifndef CONFIG_ALLEYCAT3
+ if (spiHalData.tclk == MV_BOARD_TCLK_250MHZ && serialBaudRate == _50MHz
+ && spiTypes[SPI_TYPE_FLASH].clockPolLow == 1
+ && spiTypes[SPI_TYPE_FLASH].clkPhase == 1)
+#endif /* ifndef CONFIG_ALLEYCAT3 */
+ {
+ /* set TMISO_SAMPLE to 0x2: MISO sample occurs 2 core_clk after SPI_CLK edge */
+ timingReg = MV_REG_READ(MV_SPI_TMNG_PARAMS_REG(spiId));
+ timingReg &= ~MV_SPI_TMISO_SAMPLE_MASK;
+ timingReg |= (0x2) << MV_SPI_TMISO_SAMPLE_OFFSET;
+ MV_REG_WRITE(MV_SPI_TMNG_PARAMS_REG(spiId), timingReg);
+ }
+#endif /* CONFIG_ARMADA_38X || CONFIG_ARMADA_39X || CONFIG_ALLEYCAT3 */
+
/* Verify that the CS is deasserted */
mvSpiCsDeassert(spiId);
diff --git a/board/mv_ebu/common/mv_hal/twsi/mvTwsi.c b/board/mv_ebu/common/mv_hal/twsi/mvTwsi.c
index 6be6906..62920d5 100755
--- a/board/mv_ebu/common/mv_hal/twsi/mvTwsi.c
+++ b/board/mv_ebu/common/mv_hal/twsi/mvTwsi.c
@@ -354,7 +354,7 @@
MV_U32 actualFreq = 0, actualN = 0, actualM = 0, val;
if (frequancy > 100000)
- mvOsPrintf("Warning TWSI frequancy is too high, please use up to 100Khz.\n");
+ mvOsPrintf("Warning TWSI frequency is too high, please use up to 100Khz.\n");
DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n", Tclk, frequancy));
/* Calucalte N and M for the TWSI clock baud rate */
diff --git a/board/mv_ebu/common/mv_hal_if/mvSysUsb.c b/board/mv_ebu/common/mv_hal_if/mvSysUsb.c
index 1352b0c..5dd9253 100755
--- a/board/mv_ebu/common/mv_hal_if/mvSysUsb.c
+++ b/board/mv_ebu/common/mv_hal_if/mvSysUsb.c
@@ -68,7 +68,8 @@
#include "usb/mvUsb.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
#include "usb/mvUsbRegs.h"
-
+#include "boardEnv/mvBoardEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
/*******************************************************************************
* mvSysUsbHalInit - Initialize the USB subsystem
*
@@ -88,7 +89,6 @@
MV_STATUS status = MV_OK;
MV_U32 dev;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
-
halData.ctrlModel = mvCtrlModelGet();
halData.ctrlRev = mvCtrlRevGet();
halData.ctrlFamily = mvCtrlDevFamilyIdGet(halData.ctrlModel);
@@ -104,7 +104,9 @@
MAC ID0 (usbActive =0) is connected to Physical MAC ID1 */
int id, mac_id[2] = {1, 0};
- for (id = 0; id < mvCtrlUsbMaxGet(); id++) {
+ for (id = 0; id < maxUsbPorts ; id++) {
+ if (mvBoardIsUsbPortConnected(USB_UNIT_ID,id) == MV_FALSE)
+ continue;
if (maxUsbPorts == 1 && (halData.ctrlFamily == MV_88F67X0 ||
(halData.ctrlRev == MV_88F66XX_A0_ID && halData.ctrlFamily == MV_88F66X0)))
dev = mac_id[id];
@@ -136,7 +138,9 @@
#endif
#ifdef CONFIG_USB_XHCI
MV_U32 reg;
- for (dev = 0; dev < mvCtrlUsb3HostMaxGet() ; dev++) {
+ for (dev = 0; dev < mvCtrlUsb3HostMaxGet(); dev++) {
+ if (mvBoardIsUsbPortConnected(USB3_UNIT_ID,dev) == MV_FALSE)
+ continue;
status = mvUsbUtmiPhyInit(dev, &halData);
if (halData.ctrlFamily == MV_88F66X0 || halData.ctrlFamily == MV_88F67X0) {
/* ALP/A375: Set UTMI PHY Selector:
diff --git a/board/mv_ebu/msys/cmd_sar.c b/board/mv_ebu/msys/cmd_sar.c
index df62592..30d6572 100644
--- a/board/mv_ebu/msys/cmd_sar.c
+++ b/board/mv_ebu/msys/cmd_sar.c
@@ -24,8 +24,13 @@
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "boardEnv/mvBoardEnvLib.h"
-extern MV_BOARD_INFO *marvellAC3BoardInfoTbl[];
-
+#if defined CONFIG_ALLEYCAT3
+ extern MV_BOARD_INFO *marvellAC3BoardInfoTbl[];
+ MV_BOARD_INFO **mvMsysBoardInfoTbl = marvellAC3BoardInfoTbl;
+#else
+ extern MV_BOARD_INFO *marvellBC2BoardInfoTbl[];
+ MV_BOARD_INFO **mvMsysBoardInfoTbl = marvellBC2BoardInfoTbl;
+#endif
/*
bc2 sample and reset register
# 4f # 4e # 4d # 4c #
@@ -53,9 +58,9 @@
CMD_AVS_MODE,
CMD_SLAVE_ADDR,
CMD_DEVICE_NUM,
- CMD_BOARD_ID,
CMD_DDR_ECC_EN,
#endif
+ CMD_BOARD_ID,
CMD_PCIE_MODE,
CMD_BOOTSRC,
CMD_DEVICE_ID,
@@ -74,7 +79,8 @@
0, /* OOB0 connection */
0, /* OOB1 connection */
0, /* Force AMC RC GEN1 PCIe */
- 1, /* PCIe mode */
+ 0, /* Board ID */
+ 0, /* PCIe mode */
3, /* Boot source */
0 }; /* Device ID */
MV_U32 coreClockTbl[] = MV_CORE_CLK_TBL_BC2;
@@ -87,8 +93,8 @@
1, /* AVS Mode */
1, /* I2C/SMI Slave address */
0, /* Device number */
- 0, /* Board ID */
0, /* DDR ECC enable */
+ 0, /* Board ID */
0, /* PCIe mode */
3, /* Boot source */
0 }; /* Device ID */
@@ -156,11 +162,11 @@
return CMD_SLAVE_ADDR;
if (strcmp(cmd, "devicenum") == 0)
return CMD_DEVICE_NUM;
- if (strcmp(cmd, "boardid") == 0)
- return CMD_BOARD_ID;
if (strcmp(cmd, "ddreccenable") == 0)
return CMD_DDR_ECC_EN;
#endif
+ if (strcmp(cmd, "boardid") == 0)
+ return CMD_BOARD_ID;
if (strcmp(cmd, "pcimode") == 0)
return CMD_PCIE_MODE;
if (strcmp(cmd, "bootsrc") == 0)
@@ -301,18 +307,18 @@
printf("\t| 1 | 1 |\n");
printf("\t-----------------------------\n");
break;
- case CMD_BOARD_ID:
- printf("Determines the board ID (0-7)\n");
- printf("\t| ID | Board |\n");
- printf("\t----------------------------------\n");
- for (i = 0; i < AC3_MARVELL_BOARD_NUM ; i++)
- printf("\t| %d | %-22s |\n", i, marvellAC3BoardInfoTbl[i]->boardName );
- printf("\t----------------------------------\n");
- break;
case CMD_DEVICE_NUM:
printf("Determines the device number (0-3)\n");
break;
#endif
+ case CMD_BOARD_ID:
+ printf("Determines the board ID (0-7)\n");
+ printf("\t| ID | Board |\n");
+ printf("\t----------------------------------\n");
+ for (i = 0; i < MV_MARVELL_BOARD_NUM ; i++)
+ printf("\t| %d | %-22s |\n", i, mvMsysBoardInfoTbl[i]->boardName );
+ printf("\t----------------------------------\n");
+ break;
case CMD_PCIE_MODE:
printf("Determines the PCI-E mode:\n");
printf("\t| ID | Mode |\n");
@@ -459,14 +465,14 @@
printf("devicenum Error: failed reading devicenum\n");
break;
+#endif
case CMD_BOARD_ID:
if (mvBoardSarBoardIdGet(&tmp) == MV_OK)
- printf("boardid\t\t\t= %d ==> %s\n", tmp, marvellAC3BoardInfoTbl[tmp]->boardName);
+ printf("boardid\t\t\t= %d ==> %s\n", tmp, mvMsysBoardInfoTbl[tmp]->boardName);
else
printf("boardid Error: failed reading boardid\n");
break;
-#endif
case CMD_PCIE_MODE:
if (mvBoardPcieModeGet(&tmp) == MV_OK)
printf("pcimode \t\t= %d ==> %s\n", tmp, ((tmp == 0) ? "Endpoint" : "Root Complex"));
@@ -565,13 +571,13 @@
case CMD_SLAVE_ADDR:
rc = mvBoardSmiI2c2AddrSet(tmp);
break;
- case CMD_BOARD_ID:
- rc = mvBoardSarBoardIdSet(tmp);
- break;
case CMD_DEVICE_NUM:
rc = mvBoardDeviceNumSet(tmp);
break;
#endif
+ case CMD_BOARD_ID:
+ rc = mvBoardSarBoardIdSet(tmp);
+ break;
case CMD_PCIE_MODE:
rc = mvBoardPcieModeSet(tmp);
break;
@@ -583,15 +589,13 @@
break;
case CMD_DEFAULT:
for (i = 0 ; i < CMD_DUMP; i++) {
-#if defined CONFIG_ALLEYCAT3
if (i == CMD_BOARD_ID) {
MV_U32 brdId = mvBoardIdGet();
- if ((brdId < AC3_MARVELL_BOARD_ID_BASE) || (brdId >= AC3_MARVELL_MAX_BOARD_ID))
+ if ((brdId < MARVELL_BOARD_ID_BASE) || (brdId >= MV_MAX_MARVELL_BOARD_ID))
mvOsPrintf("Bad Board ID returned - %d! Assigning default value!\n", brdId);
else
- defaultValue[i] = brdId - AC3_MARVELL_BOARD_ID_BASE; /* Update default value with real board ID*/
+ defaultValue[i] = brdId - MARVELL_BOARD_ID_BASE; /* Update default value with real board ID*/
}
-#endif /* CONFIG_ALLEYCAT3 */
if (1 == do_sar_write(i, defaultValue[i]))
rc = MV_FALSE;
do_sar_read(i);
@@ -623,12 +627,10 @@
cmd = argv[1];
mode = sar_cmd_get(argv[2]);
-#if defined CONFIG_ALLEYCAT3
- if(mvBoardIdGet() != DB_AC3_ID && mode != CMD_BOARD_ID) {
+ if(mvBoardIdGet() != MV_DEFAULT_BOARD_ID && mode != CMD_BOARD_ID) {
mvOsPrintf("Error: Sample at reset supports modifying only 'boardid' field for current board\n\n");
goto usage;
}
-#endif
if (strcmp(cmd, "list") == 0)
return do_sar_list(mode);
@@ -674,13 +676,13 @@
#endif
"bootsrc - Boot source\n"
"deviceid - Device ID\n"
-#ifdef CONFIG_ALLEYCAT3
-"\t----Legacy fileds----\n"
-"pllclock - PLL2 VCO clock frequency. Valid for rev.A0 only\n"
"\n\tSW SatR fields\n"
"\t--------------\n"
-"ddreccenable - DDR ECC modes\n"
"boardid - Board ID\n"
+#ifdef CONFIG_ALLEYCAT3
+"ddreccenable - DDR ECC modes\n"
+"\t----Legacy fileds----\n"
+"pllclock - PLL2 VCO clock frequency. Valid for rev.A0 only\n"
#endif
);
#endif /*defined(CONFIG_CMD_SAR)*/
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index 332749c..5301aff 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -94,12 +94,39 @@
extern MV_BOARD_INFO *customerBC2BoardInfoTbl[];
extern MV_BOARD_INFO *marvellAC3BoardInfoTbl[];
extern MV_BOARD_INFO *customerAC3BoardInfoTbl[];
+extern MV_BOARD_INFO *marvellBOBKBoardInfoTbl[];
+extern MV_BOARD_INFO *customerBOBKBoardInfoTbl[];
/* Global variables should be removed from BSS (set to a non-zero value)
for avoiding memory corruption during early access upon code relocation */
static MV_BOARD_INFO *board = (MV_BOARD_INFO *)-1;
/* Locals */
static MV_DEV_CS_INFO *mvBoardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+/*******************************************************************************
+* mvBoardisUsbPortConnected
+*
+* DESCRIPTION:
+* return True if requested USB type and port num exists on current board
+*
+* INPUT:
+* usbTypeID - requested USB type : USB3_UNIT_ID / USB_UNIT_ID
+* usbPortNumbder - requested USB port number (according to xHCI MAC port num)
+*
+* OUTPUT: None
+*
+* RETURN: MV_TRUE if requested port/type exist on board
+
+*******************************************************************************/
+MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber)
+{
+ /*BobCat2 SoC have no usb port
+ AlleyCat3 & BobK SoC board has only one usb2 port */
+#ifdef MV_USB
+ if (usbTypeID == USB_UNIT_ID && usbPortNumber == 0)
+ return MV_TRUE;
+#endif
+ return MV_FALSE;
+}
/*******************************************************************************
* mvBoardIdIndexGet
@@ -176,6 +203,12 @@
mvGppTypeSet(0, 0xFFFFFFFF, board->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, board->gppOutEnValMid);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ MV_REG_WRITE(GPP_DATA_OUT_REG(2), board->gppOutValHigh);
+ mvGppPolaritySet(2, 0xFFFFFFFF, board->gppPolarityValHigh);
+ mvGppTypeSet(2, 0xFFFFFFFF, board->gppOutEnValHigh);
+ }
+
#ifndef CONFIG_CUSTOMER_BOARD_SUPPORT
mvBoardOobPortCfgSet();
#endif
@@ -275,10 +308,7 @@
*******************************************************************************/
MV_BOOL mvBoardIsEthConnected(MV_U32 ethNum)
{
- if (ethNum <= mvCtrlEthMaxPortGet())
- return MV_TRUE;
-
- return MV_FALSE;
+ return mvBoardIsGbEPortConnected(ethNum);
}
/*******************************************************************************
@@ -324,6 +354,10 @@
*******************************************************************************/
MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum)
{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (boardId == DB_78X60_AMC_ID && ethPortNum == 0)
+ return MV_FALSE;
return MV_TRUE;
}
/*******************************************************************************
@@ -350,6 +384,30 @@
}
/*******************************************************************************
+* mvBoardPortTypeGet
+*
+* DESCRIPTION:
+* This routine returns port type
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Mode of the port
+*
+*******************************************************************************/
+MV_U32 mvBoardPortTypeGet(MV_U32 ethPortNum)
+{
+ if (mvBoardIsPortInSgmii(ethPortNum))
+ return MV_PORT_TYPE_SGMII;
+ else
+ return MV_PORT_TYPE_RGMII;
+}
+
+/*******************************************************************************
* mvBoardIsPortInMii
*
* DESCRIPTION:
@@ -418,6 +476,8 @@
MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum)
{
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return !mvBoardIsPortInGmii(ethPortNum);
return !mvBoardIsPortInGmii(ethPortNum) && !mvBoardIsPortInSgmii(ethPortNum);
}
/*******************************************************************************
@@ -489,7 +549,63 @@
*******************************************************************************/
MV_U32 mvBoardTclkGet(MV_VOID)
{
- return 200000000; /* constant Tclock @ 200MHz (not Sampled@Reset) */
+ /* U-Boot flow for MSYS can not read FamilyIdGet to derrive Tclk,
+ since FamilyIdGet needs Board ID, via TWSI trasaction, which depends on Tclk reading.
+ MSYS platforms use static Tclk=200MHz (not Sampled@Reset)*/
+#ifdef MV_MSYS /* MV_MSYS is defined only in U-boot for MSYS platforms: AC3/BC2/BobK */
+ return MV_BOARD_TCLK_200MHZ;
+#else
+
+ /* for Linux flow, FamilyIdGet can use BoardIDGet, since Board id is not readen from TWSI,
+ but passed from U-Boot tags instead */
+
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID)
+ /* constant Tclock @ 200MHz (not Sampled@Reset) */
+ return MV_BOARD_TCLK_200MHZ;
+
+ if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_TCLK_MASK) != 0)
+ return MV_BOARD_TCLK_200MHZ;
+ else
+ return MV_BOARD_TCLK_250MHZ;
+#endif
+}
+
+/*******************************************************************************
+* mvBoardSysClkGetAxp - Get the board SysClk of AXP (CPU bus clock , i.e. DDR clock)
+*
+* DESCRIPTION:
+* This routine extract the CPU bus clock.
+*
+* INPUT:
+* countNum - Counter number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit clock cycles in Hertz.
+*
+*******************************************************************************/
+MV_U32 mvBoardSysClkGetAxp(MV_VOID)
+{
+ MV_U32 idx;
+ MV_U32 cpuFreqMhz, ddrFreqMhz;
+ MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL_AXP;
+
+ idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),
+ MV_REG_READ(MPP_SAMPLE_AT_RESET(1)));
+
+ if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */
+ cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */
+ cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */
+ ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr;
+ /* round up to integer MHz */
+ if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5)
+ ddrFreqMhz++;
+
+ return ddrFreqMhz * 1000000;
+ } else
+ return 0xFFFFFFFF;
}
/*******************************************************************************
@@ -513,8 +629,12 @@
MV_U32 idx;
MV_U32 freq_tbl_bc2[] = MV_CORE_CLK_TBL_BC2;
MV_U32 freq_tbl_ac3[] = MV_CORE_CLK_TBL_AC3;
+ MV_U32 freq_tbl_bobk_cetus[] = MV_CORE_CLK_TBL_BOBK_CETUS;
+ MV_U32 freq_tbl_bobk_caelum[] = MV_CORE_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
+ if (family == MV_78460_DEV_ID)
+ return mvBoardSysClkGetAxp();
idx = MSAR_CORE_CLK(MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(0)), MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1)));
if (idx >= 7)
@@ -524,7 +644,20 @@
return freq_tbl_bc2[idx] * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
return freq_tbl_ac3[idx] * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ /* BobK family has two different flavors(Cetus/Caelum) with different settings */
+ switch (mvCtrlModelGet() & ~BOBK_FLAVOR_MASK) {
+ case MV_BOBK_CETUS_98DX4235_DEV_ID:
+ return freq_tbl_bobk_cetus[idx] * 1000000;
+ break;
+ case MV_BOBK_CAELUM_98DX4203_DEV_ID:
+ return freq_tbl_bobk_caelum[idx] * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown Device ID %d, CORE freq get failed\n", mvCtrlModelGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
}
@@ -747,7 +880,8 @@
*******************************************************************************/
MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum)
{
- if ((ethPortNum + 1) <= board->numBoardMacInfo)
+ if ((ethPortNum < board->numBoardMacInfo) &&
+ (board->pBoardMacInfo[ethPortNum].boardMacEnabled == MV_TRUE))
return MV_TRUE;
else
return MV_FALSE;
@@ -772,30 +906,37 @@
MV_VOID mvBoardCpldConfigurationGet(char *str)
{
MV_U8 cpldTwsiDev, cpldConfig;
+ MV_U8 cpldBoardRevReg = CPLD_BOARD_REV_REG;
+ MV_U16 boardModel;
- /* CPLD board configuration print for AC3 */
- if (mvCtrlDevFamilyIdGet(0) != MV_ALLEYCAT3_DEV_ID)
- return;
+ /* Prevent the caller function from printing the same string twice if this function fails */
+ *str = 0;
+
cpldTwsiDev = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_PLD, 0);
/* verify that CPLD device is available on current board, else return*/
if (cpldTwsiDev == 0xff || mvTwsiProbe(cpldTwsiDev, mvBoardTclkGet()) != MV_TRUE)
return;
+ boardModel = mvBoardModelGet();
+ if (boardModel == RD_MTL_BC2_PCB_ID)
+ cpldBoardRevReg = CPLD_RD_MTL_BC2_BOARD_REV_REG;
+
/* Read Board Revision */
- if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_BOARD_REV_REG, &cpldConfig)) {
+ if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, cpldBoardRevReg, &cpldConfig)) {
mvOsPrintf("\n%s: Error: failed reading board Revision from CPLD.\n", __func__);
return;
}
sprintf(str, ", Rev %d" , cpldConfig & CPLD_BOARD_REV_MASK);
/* Read CPLD Revision */
- if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_REV_REG, &cpldConfig)) {
- mvOsPrintf("\n%s: Error: failed reading CPLD Revision from CPLD.\n", __func__);
- return;
+ if (boardModel != RD_MTL_BC2_PCB_ID) {
+ if (MV_ERROR == mvBoardTwsiRead(BOARD_DEV_TWSI_PLD, 0, CPLD_REV_REG, &cpldConfig)) {
+ mvOsPrintf("\n%s: Error: failed reading CPLD Revision from CPLD.\n", __func__);
+ return;
+ }
+ sprintf(str, "%s, CPLD Rev %d", str, cpldConfig & CPLD_BOARD_REV_MASK);
}
-
- sprintf(str, "%s, CPLD Rev %d", str, cpldConfig & CPLD_BOARD_REV_MASK);
}
/* Board devices API managments */
@@ -1008,6 +1149,92 @@
}
/*******************************************************************************
+* mvBoardGetDevBusNum
+*
+* DESCRIPTION:
+* Return the device's bus number.
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* dev bus number else the function returns 0xFFFFFFFF
+*
+*******************************************************************************/
+MV_U32 mvBoardGetDevBusNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO *devEntry = mvBoardGetDevEntry(devNum, devClass);
+
+ if (devEntry)
+ return devEntry->busNum;
+
+ return 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* mvBoardGetDevState
+*
+* DESCRIPTION:
+* Return the device's activity state.
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* dev activity state else the function returns 0xFFFFFFFF
+*
+*******************************************************************************/
+MV_BOOL mvBoardGetDevState(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO *devEntry = mvBoardGetDevEntry(devNum, devClass);
+
+ if (devEntry)
+ return devEntry->active;
+
+ return 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* mvBoardSetDevState
+*
+* DESCRIPTION:
+* Sets the device's activity state.
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+* newState - requested deevice state
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns
+* MV_OK else MV_ERROR
+*
+*******************************************************************************/
+MV_STATUS mvBoardSetDevState(MV_32 devNum, MV_BOARD_DEV_CLASS devClass, MV_BOOL newState)
+{
+ MV_DEV_CS_INFO *devEntry = mvBoardGetDevEntry(devNum, devClass);
+
+ if (devEntry) {
+ devEntry->active = newState;
+ return MV_OK;
+ } else
+ return MV_ERROR;
+}
+
+/*******************************************************************************
* mvBoardTwsiAddrTypeGet -
*
* DESCRIPTION:
@@ -1127,14 +1354,22 @@
static MV_U32 gBoardId = -1;
MV_VOID mvBoardSet(MV_U32 boardId)
{
+ /* Marvell BobK Boards */
+ if (boardId >= BOBK_MARVELL_BOARD_ID_BASE && boardId < BOBK_MARVELL_MAX_BOARD_ID) { /* Marvell Board */
+ board = marvellBOBKBoardInfoTbl[mvBoardIdIndexGet(boardId)];
+ gBoardId = boardId;
/* Marvell Bobcat2 Boards */
- if (boardId >= BC2_MARVELL_BOARD_ID_BASE && boardId < BC2_MARVELL_MAX_BOARD_ID) { /* Marvell Board */
+ } else if (boardId >= BC2_MARVELL_BOARD_ID_BASE && boardId < BC2_MARVELL_MAX_BOARD_ID) { /* Marvell Board */
board = marvellBC2BoardInfoTbl[mvBoardIdIndexGet(boardId)];
gBoardId = boardId;
/* Marvell AlleyCat3 Boards */
} else if (boardId >= AC3_MARVELL_BOARD_ID_BASE && boardId < AC3_MARVELL_MAX_BOARD_ID) { /* Marvell Board */
board = marvellAC3BoardInfoTbl[mvBoardIdIndexGet(boardId)];
gBoardId = boardId;
+ /* Customer BobK Boards */
+ } else if (boardId >= BOBK_CUSTOMER_BOARD_ID_BASE && boardId < BOBK_CUSTOMER_MAX_BOARD_ID) {/*Customer Board*/
+ board = customerBOBKBoardInfoTbl[mvBoardIdIndexGet(boardId)];
+ gBoardId = boardId;
/* Customer Bobcat2 Boards */
} else if (boardId >= BC2_CUSTOMER_BOARD_ID_BASE && boardId < BC2_CUSTOMER_MAX_BOARD_ID) { /* Customer Board */
board = customerBC2BoardInfoTbl[mvBoardIdIndexGet(boardId)];
@@ -1143,14 +1378,24 @@
} else if (boardId >= AC3_CUSTOMER_BOARD_ID_BASE && boardId < AC3_CUSTOMER_MAX_BOARD_ID) { /* Customer Board */
board = customerAC3BoardInfoTbl[mvBoardIdIndexGet(boardId)];
gBoardId = boardId;
+ /* Marvell AXP-AMC Board */
+ } else if (boardId == DB_78X60_AMC_ID) {
+ /* This case should enter only for LSP 3.2/3.4 flow:
+ * This board ID is passed from AXP-AMC U-Boot 2011.12, and shared here only
+ * for Linux usage (AXP family is shared with MSYS family in LSP) */
+ board = marvellAXPboardInfoTbl[0];
+ gBoardId = boardId;
} else {
mvOsPrintf("%s: Error: wrong board Id (%d)\n", __func__, boardId);
#ifdef CONFIG_ALLEYCAT3
gBoardId = AC3_CUSTOMER_BOARD_ID0;
board = customerAC3BoardInfoTbl[gBoardId];
-#else
+#elif defined CONFIG_BOBCAT2
gBoardId = BC2_CUSTOMER_BOARD_ID0;
board = customerBC2BoardInfoTbl[gBoardId];
+#else
+ gBoardId = BOBK_CETUS_CUSTOMER_BOARD_ID0;
+ board = customerBOBKBoardInfoTbl[gBoardId];
#endif
mvOsPrintf("Applying default Customer board ID (%d: %s)\n", gBoardId, board->boardName);
}
@@ -1179,55 +1424,59 @@
if (gBoardId != -1)
return gBoardId;
-#if defined CONFIG_ALLEYCAT3
+#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
- #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+ #if defined CONFIG_ALLEYCAT3
#ifdef CONFIG_CUSTOMER_BOARD_0
gBoardId = AC3_CUSTOMER_BOARD_ID0;
#elif CONFIG_CUSTOMER_BOARD_1
gBoardId = AC3_CUSTOMER_BOARD_ID1;
#endif
- #else /* !CONFIG_CUSTOMER_BOARD_SUPPORT */
-
- /* For Marvell Boards: Temporarily set generic board struct pointer to
- use S@R TWSI address, and read board ID */
- board = marvellAC3BoardInfoTbl[mvBoardIdIndexGet(DB_AC3_ID)];
- gBoardId = DB_AC3_ID; /* Terporary for usage by mvCtrlDevFamilyIdGet */
- MV_U8 readValue;
-
- if (mvBoardSarBoardIdGet(&readValue) != MV_OK || readValue >= AC3_MARVELL_BOARD_NUM) {
- mvOsPrintf("%s: Error obtaining Board ID from EEPROM (%d)\n", __func__, readValue);
- mvOsPrintf("%s: Setting default board: DB-DXAC3-MM\n", __func__);
- readValue = DB_AC3_ID - AC3_MARVELL_BOARD_ID_BASE;
- }
-
- gBoardId = AC3_MARVELL_BOARD_ID_BASE + readValue;
- #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
-
-#else /* CONFIG_BOBCAT2 */
-
- #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
+ #elif defined CONFIG_BOBCAT2
#ifdef CONFIG_CUSTOMER_BOARD_0
gBoardId = BC2_CUSTOMER_BOARD_ID0;
#elif CONFIG_CUSTOMER_BOARD_1
gBoardId = BC2_CUSTOMER_BOARD_ID1;
#endif
- #else /* !CONFIG_CUSTOMER_BOARD_SUPPORT */
-
- #if defined(DB_BOBCAT2)
- gBoardId = DB_DX_BC2_ID;
- #elif defined(RD_BOBCAT2)
- gBoardId = RD_DX_BC2_ID;
- #elif defined(RD_MTL_BOBCAT2)
- gBoardId = RD_MTL_BC2;
- #else
- mvOsPrintf("%s: Board ID must be defined!\n", __func__);
- while (1)
- continue;
+ #else /* BOBK */
+ #ifdef CONFIG_CUSTOMER_BOARD_0
+ gBoardId = BOBK_CETUS_CUSTOMER_BOARD_ID0;
+ #elif CONFIG_CUSTOMER_BOARD_1
+ gBoardId = BOBK_CAELUM_CUSTOMER_BOARD_ID1;
#endif
- #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
+ #endif
-#endif
+#else /* !CONFIG_CUSTOMER_BOARD_SUPPORT */
+
+ MV_U8 readValue;
+ MV_BOARD_INFO **mvBoardInfoTbl =
+ #if defined CONFIG_ALLEYCAT3
+ marvellAC3BoardInfoTbl;
+ #elif defined CONFIG_BOBCAT2
+ marvellBC2BoardInfoTbl;
+ #else /* BOBK */
+ marvellBOBKBoardInfoTbl;
+ #endif
+
+ /* Temporarily set generic board struct pointer, to set/get EEPROM i2c address, and read board ID */
+ board = mvBoardInfoTbl[mvBoardIdIndexGet(MV_DEFAULT_BOARD_ID)];
+ gBoardId = MV_DEFAULT_BOARD_ID; /* Terporary for usage by mvCtrlDevFamilyIdGet */
+
+ if (mvBoardSarBoardIdGet(&readValue) != MV_OK) {
+ mvOsPrintf("%s: Error obtaining Board ID from EEPROM (%d)\n", __func__, readValue);
+ mvOsPrintf("%s: Setting default board to: %s\n", __func__, board->boardName);
+ return MV_DEFAULT_BOARD_ID;
+ }
+ readValue = readValue & (BOARD_ID_INDEX_MASK - 1);
+
+ if (readValue >= MV_MARVELL_BOARD_NUM) {
+ mvOsPrintf("%s: Error: read wrong board ID (%d)\n", __func__, readValue);
+ mvOsPrintf("%s: Setting default board to: %s\n", __func__, board->boardName);
+ return MV_DEFAULT_BOARD_ID;
+ }
+ gBoardId = MARVELL_BOARD_ID_BASE + readValue;
+
+#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
return gBoardId;
}
@@ -1430,9 +1679,9 @@
MV_U8 sar0;
MV_STATUS rc1;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U32 fieldOffs = (family == MV_BOBCAT2_DEV_ID) ? 0 : 2;
+ MV_U32 fieldOffs = (family == MV_ALLEYCAT3_DEV_ID) ? 2 : 0;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
@@ -1452,9 +1701,10 @@
MV_U8 sar0;
MV_STATUS rc1;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U32 fieldOffs = (family == MV_BOBCAT2_DEV_ID) ? 0 : 2;
+ MV_U32 fieldOffs = (family == MV_ALLEYCAT3_DEV_ID) ? 2 : 0;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)
+ && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
@@ -1475,6 +1725,75 @@
DB(mvOsPrintf("Board: Write core FreqOpt S@R succeeded\n"));
return MV_OK;
}
+
+/*******************************************************************************
+* Read the new SW SatR field "bypass_coreclock" from EEPROM(0x50), reg#6 bits[2:0]
+*******************************************************************************/
+MV_STATUS mvBoardBypassCoreFreqGet(MV_U8 *value)
+{
+ MV_U8 sar0;
+ MV_STATUS rc1;
+ MV_U16 family = mvCtrlDevFamilyIdGet(0);
+
+ if (family != MV_BOBK_DEV_ID) {
+ DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
+ return MV_ERROR;
+ }
+
+ /* The Core Frequency in Bypass mode is taken from the first address-value pair of the EEPROM
+ initialization sequence, In order to support normal TWSI init sequence flow, the first pair
+ of DWORDS on EEPROM should contain an address (bytes 0-3) of some scratch pad register
+ (for instance an UART SCR) and a value (bytes 4-7), which will be partially interpreted
+ as Core Freq in bypass mode (bits[2:0] of byte 6)
+ */
+
+ rc1 = mvBoardTwsiRead(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, &sar0);
+ if (MV_ERROR == rc1)
+ return MV_ERROR;
+
+ *value = (sar0 & 0x7);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* Write the new SW SatR field "bypass_coreclock" to EEPROM(0x50), reg#6 bits[2:0]
+*******************************************************************************/
+MV_STATUS mvBoardBypassCoreFreqSet(MV_U8 freqVal)
+{
+ MV_U8 sar0;
+ MV_STATUS rc1;
+ MV_U16 family = mvCtrlDevFamilyIdGet(0);
+
+ if (family != MV_BOBK_DEV_ID) {
+ DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
+ return MV_ERROR;
+ }
+
+ /* The Core Frequency in Bypass mode is taken from the first address-value pair of the EEPROM
+ initialization sequence, In order to support normal TWSI init sequence flow, the first pair
+ of DWORDS on EEPROM should contain an address (bytes 0-3) of some scratch pad register
+ (for instance an UART SCR) and a value (bytes 4-7), which will be partially interpreted
+ as Core Freq in bypass mode (bits[2:0] of byte 6)
+ */
+
+ rc1 = mvBoardTwsiRead(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, &sar0);
+ if (MV_ERROR == rc1)
+ return MV_ERROR;
+
+ sar0 &= ~0x7;
+ sar0 |= (freqVal & 0x7);
+
+ if (MV_OK != mvBoardTwsiWrite(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, sar0)) {
+ DB(mvOsPrintf("Board: Write Bypass core Freq S@R fail\n"));
+ return MV_ERROR;
+ }
+
+
+ DB(mvOsPrintf("Board: Write Bypss core FreqOpt S@R succeeded\n"));
+ return MV_OK;
+}
+
/*******************************************************************************/
MV_STATUS mvBoardCpuFreqGet(MV_U8 *value)
{
@@ -1489,7 +1808,17 @@
(MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar2)))
return MV_ERROR;
- *value = ((((sar2 & 0x1)) << 3) | ((sar & 0x18) >> 3));
+ *value = ((((sar2 & 0x1)) << 2) | ((sar & 0x18) >> 3));
+
+ } else if (family == MV_BOBK_DEV_ID) {
+ MV_U8 sar2;
+
+ /* BOBK */
+ if ((MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar)) ||
+ (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar2)))
+ return MV_ERROR;
+
+ *value = ((((sar2 & 0x1)) << 2) | ((sar & 0x18) >> 3));
} else if (family == MV_ALLEYCAT3_DEV_ID) {
@@ -1534,6 +1863,27 @@
return MV_ERROR;
}
+ } else if (family == MV_BOBK_DEV_ID) {
+ MV_U8 sar2;
+ /* BOBK */
+ if ((MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar)) ||
+ (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar2)))
+ return MV_ERROR;
+
+ sar &= ~0x18;
+ sar2 &= ~0x1;
+ sar |= ((freqVal & 0x03) << 3);
+ sar2 |= ((freqVal & 0x04) >> 2);
+
+ if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) {
+ DB(mvOsPrintf("Board: Write CpuFreq(1) S@R fail\n"));
+ return MV_ERROR;
+ }
+ if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar2)) {
+ DB(mvOsPrintf("Board: Write CpuFreq(2) S@R fail\n"));
+ return MV_ERROR;
+ }
+
} else if (family == MV_ALLEYCAT3_DEV_ID) {
/* AC3 */
@@ -1563,16 +1913,27 @@
MV_U8 sar2;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- if (family != MV_BOBCAT2_DEV_ID) {
+ if (family != MV_BOBCAT2_DEV_ID && family != MV_BOBK_DEV_ID) {
DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
return MV_ERROR; /* AC3 */
}
- /* BC2 */
- if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar2))
- return MV_ERROR;
+ if (family == MV_BOBCAT2_DEV_ID) {
- *value = ((sar2 & 0x0E) >> 1);
+ /* BC2 */
+ if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar2))
+ return MV_ERROR;
+
+ *value = ((sar2 & 0x0E) >> 1);
+
+ } else if (family == MV_BOBK_DEV_ID) {
+
+ /* BOBK */
+ if (MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar2))
+ return MV_ERROR;
+
+ *value = (sar2 & 0x07);
+ }
return MV_OK;
}
@@ -1583,22 +1944,41 @@
MV_U8 sar2;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- if (family != MV_BOBCAT2_DEV_ID) {
+ if (family != MV_BOBCAT2_DEV_ID && family != MV_BOBK_DEV_ID) {
DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
return MV_ERROR; /* AC3 */
}
- /* BC2 */
- if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar2))
- return MV_ERROR;
+ if (family == MV_BOBCAT2_DEV_ID) {
- sar2 &= ~0xE;
- sar2 |= ((freqVal & 0x07) << 1);
+ /* BC2 */
+ if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar2))
+ return MV_ERROR;
- if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar2)) {
- DB(mvOsPrintf("Board: Write TM-Freq S@R fail\n"));
- return MV_ERROR;
+ sar2 &= ~0xE;
+ sar2 |= ((freqVal & 0x07) << 1);
+
+ if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar2)) {
+ DB(mvOsPrintf("Board: Write TM-Freq S@R fail\n"));
+ return MV_ERROR;
+ }
+ } else if (family == MV_BOBK_DEV_ID) {
+
+ /* BOBK */
+ if (MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar2))
+ return MV_ERROR;
+
+ sar2 &= ~0x7;
+ sar2 |= (freqVal & 0x07);
+
+ if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar2)) {
+ DB(mvOsPrintf("Board: Write TM-Freq S@R fail\n"));
+ return MV_ERROR;
+ }
}
+
+ /* BC2 or BOBK*/
+
DB(mvOsPrintf("Board: Write TM-Freq S@R succeeded\n"));
return MV_OK;
@@ -1610,16 +1990,27 @@
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- if (family != MV_BOBCAT2_DEV_ID) {
+ if (family != MV_BOBCAT2_DEV_ID && family != MV_BOBK_DEV_ID) {
DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
return MV_ERROR; /* AC3 */
}
- /* BC2 */
- if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
- return MV_ERROR;
+ if (family == MV_BOBCAT2_DEV_ID) {
- *value = (sar & 0x8) >> 3;
+ /* BC2 */
+ if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
+ return MV_ERROR;
+
+ *value = (sar & 0x8) >> 3;
+
+ } else if (family == MV_BOBK_DEV_ID) {
+
+ /* BOBK */
+ if (MV_ERROR == mvBoardTwsiSatRGet(1, 0, &sar))
+ return MV_ERROR;
+
+ *value = (sar & 0x8) >> 3;
+ }
return MV_OK;
}
@@ -1630,21 +2021,38 @@
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- if (family != MV_BOBCAT2_DEV_ID) {
+ if (family != MV_BOBCAT2_DEV_ID && family != MV_BOBK_DEV_ID) {
DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
return MV_ERROR; /* AC3 */
}
- /* BC2 */
- if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
- return MV_ERROR;
+ if (family == MV_BOBCAT2_DEV_ID) {
- sar &= ~(0x8);
- sar |= ((cpu & 0x1) << 3);
+ /* BC2 */
+ if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
+ return MV_ERROR;
- if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) {
- DB(mvOsPrintf("Board: Write JTAG CPU S@R fail\n"));
- return MV_ERROR;
+ sar &= ~(0x8);
+ sar |= ((cpu & 0x1) << 3);
+
+ if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) {
+ DB(mvOsPrintf("Board: Write JTAG CPU S@R fail\n"));
+ return MV_ERROR;
+ }
+
+ } else if (family == MV_BOBK_DEV_ID) {
+
+ /* BOBK */
+ if (MV_ERROR == mvBoardTwsiSatRGet(1, 0, &sar))
+ return MV_ERROR;
+
+ sar &= ~(0x8);
+ sar |= ((cpu & 0x1) << 3);
+
+ if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) {
+ DB(mvOsPrintf("Board: Write JTAG CPU S@R fail\n"));
+ return MV_ERROR;
+ }
}
DB(mvOsPrintf("Board: Write JTAG CPU S@R succeeded\n"));
@@ -1658,8 +2066,8 @@
MV_U16 family = mvCtrlDevFamilyIdGet(0);
if (family != MV_BOBCAT2_DEV_ID) {
- DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
- return MV_ERROR; /* AC3 */
+ DB(mvOsPrintf("%s: Only Support BC2 controller family\n", __func__));
+ return MV_ERROR; /* AC3/BOBK */
}
/* BC2 */
@@ -1678,8 +2086,8 @@
MV_U16 family = mvCtrlDevFamilyIdGet(0);
if (family != MV_BOBCAT2_DEV_ID) {
- DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
- return MV_ERROR; /* AC3 */
+ DB(mvOsPrintf("%s: Only Support BC2 controller family\n", __func__));
+ return MV_ERROR; /* AC3/BOBK */
}
/* BC2 */
@@ -1705,8 +2113,8 @@
MV_U16 family = mvCtrlDevFamilyIdGet(0);
if (family != MV_BOBCAT2_DEV_ID) {
- DB(mvOsPrintf("%s: AC3 controller family is not supported\n", __func__));
- return MV_ERROR; /* AC3 */
+ DB(mvOsPrintf("%s: Only Support BC2 controller family\n", __func__));
+ return MV_ERROR; /* AC3/BOBK */
}
if (port > 1) {
@@ -1809,9 +2217,9 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U8 twsiDevice = (family == MV_BOBCAT2_DEV_ID) ? 3 : 2;
+ MV_U8 twsiDevice = (family == MV_ALLEYCAT3_DEV_ID) ? 2 : 3;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
@@ -1819,7 +2227,10 @@
if (MV_ERROR == mvBoardTwsiSatRGet(twsiDevice, 0, &sar))
return MV_ERROR;
- *value = (sar & 0x7);
+ if (family == MV_BOBK_DEV_ID)
+ *value = ((sar & 0x0E) >> 1);
+ else
+ *value = (sar & 0x7);
return MV_OK;
}
@@ -1829,9 +2240,9 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U8 twsiDevice = (family == MV_BOBCAT2_DEV_ID) ? 3 : 2;
+ MV_U8 twsiDevice = (family == MV_ALLEYCAT3_DEV_ID) ? 2 : 3;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
@@ -1839,8 +2250,13 @@
if (MV_ERROR == mvBoardTwsiSatRGet(twsiDevice, 0, &sar))
return MV_ERROR;
- sar &= ~(0x7);
- sar |= (val & 0x7);
+ if (family == MV_BOBK_DEV_ID) {
+ sar &= ~(0xE);
+ sar |= ((val & 0x7) << 1);
+ } else {
+ sar &= ~(0x7);
+ sar |= (val & 0x7);
+ }
if (MV_OK != mvBoardTwsiSatRSet(twsiDevice, 0, sar)) {
DB(mvOsPrintf("Board: Write BootDev S@R fail\n"));
@@ -1855,16 +2271,17 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
+ MV_U8 twsiDevice = (family == MV_BOBK_DEV_ID) ? 2 : 0;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
- if (MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar))
- return MV_ERROR;
+ if (MV_ERROR == mvBoardTwsiSatRGet(twsiDevice, 0, &sar))
+ return MV_ERROR;
- *value = (sar & 0x1F);
+ *value = (sar & 0x1F);
return MV_OK;
}
@@ -1874,19 +2291,20 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
+ MV_U8 twsiDevice = (family == MV_BOBK_DEV_ID) ? 2 : 0;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
- if (MV_ERROR == mvBoardTwsiSatRGet(0, 0, &sar))
+ if (MV_ERROR == mvBoardTwsiSatRGet(twsiDevice, 0, &sar))
return MV_ERROR;
sar &= ~(0x1F);
sar |= (val & 0x1F);
- if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) {
+ if (MV_OK != mvBoardTwsiSatRSet(twsiDevice, 0, sar)) {
DB(mvOsPrintf("Board: Write device-id S@R fail\n"));
return MV_ERROR;
}
@@ -1945,17 +2363,24 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U8 bitOffset = (family == MV_BOBCAT2_DEV_ID) ? 4 : 3;
+ MV_U8 bitOffset = (family == MV_ALLEYCAT3_DEV_ID) ? 3 : 4;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
- if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar))
- return MV_ERROR;
+ if ((family == MV_ALLEYCAT3_DEV_ID) || (family == MV_BOBCAT2_DEV_ID)) {
+ if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar))
+ return MV_ERROR;
- *val = (sar & (0x1 << bitOffset)) >> bitOffset;
+ *val = (sar & (0x1 << bitOffset)) >> bitOffset;
+ } else if (family == MV_BOBK_DEV_ID) {
+ if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
+ return MV_ERROR;
+
+ *val = (sar & (0x1 << bitOffset)) >> bitOffset;
+ }
return MV_OK;
}
@@ -1965,22 +2390,35 @@
{
MV_U8 sar;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U8 bitOffset = (family == MV_BOBCAT2_DEV_ID) ? 4 : 3;
+ MV_U8 bitOffset = (family == MV_ALLEYCAT3_DEV_ID) ? 3 : 4;
- if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID)) {
+ if ((family != MV_ALLEYCAT3_DEV_ID) && (family != MV_BOBCAT2_DEV_ID) && (family != MV_BOBK_DEV_ID)) {
DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
return MV_ERROR;
}
- if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar))
- return MV_ERROR;
+ if ((family == MV_ALLEYCAT3_DEV_ID) || (family == MV_BOBCAT2_DEV_ID)) {
+ if (MV_ERROR == mvBoardTwsiSatRGet(2, 0, &sar))
+ return MV_ERROR;
- sar &= ~(0x1 << bitOffset);
- sar |= (val & 0x1) << bitOffset;
+ sar &= ~(0x1 << bitOffset);
+ sar |= (val & 0x1) << bitOffset;
- if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar)) {
- DB(mvOsPrintf("Board: Write pcimode S@R fail\n"));
- return MV_ERROR;
+ if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar)) {
+ DB(mvOsPrintf("Board: Write pcimode S@R fail\n"));
+ return MV_ERROR;
+ }
+ } else if (family == MV_BOBK_DEV_ID) {
+ if (MV_ERROR == mvBoardTwsiSatRGet(3, 0, &sar))
+ return MV_ERROR;
+
+ sar &= ~(0x1 << bitOffset);
+ sar |= (val & 0x1) << bitOffset;
+
+ if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) {
+ DB(mvOsPrintf("Board: Write pcimode S@R fail\n"));
+ return MV_ERROR;
+ }
}
DB(mvOsPrintf("Board: Write pcimode S@R succeeded\n"));
@@ -2182,12 +2620,6 @@
MV_STATUS mvBoardSarBoardIdGet(MV_U8 *value)
{
MV_U8 boardId;
- MV_U16 family = mvCtrlDevFamilyIdGet(0);
-
- if (family != MV_ALLEYCAT3_DEV_ID) {
- DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
- return MV_ERROR;
- }
/* The Board Id is taken from the first address-value pair of the EEPROM initialization sequence
In order to support normal TWSI init sequence flow, the first pair of DWORDS on EEPROM
@@ -2208,14 +2640,21 @@
MV_U8 boardId;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- if (family != MV_ALLEYCAT3_DEV_ID) {
- DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
- return MV_ERROR;
- }
-
- if (val >= AC3_MARVELL_BOARD_NUM) {
- mvOsPrintf("%s: Error: Unsupported board ID (%d)\n", __func__, val);
- return MV_ERROR;
+ if (family == MV_ALLEYCAT3_DEV_ID) {
+ if (val >= AC3_MARVELL_BOARD_NUM) {
+ mvOsPrintf("%s: Error: Unsupported board ID (%d)\n", __func__, val);
+ return MV_ERROR;
+ }
+ } else if (family == MV_BOBK_DEV_ID) {
+ if (val >= BOBK_MARVELL_BOARD_NUM) {
+ mvOsPrintf("%s: Error: Unsupported board ID (%d)\n", __func__, val);
+ return MV_ERROR;
+ }
+ } else if (family == MV_BOBCAT2_DEV_ID) {
+ if (val >= BC2_MARVELL_BOARD_NUM) {
+ mvOsPrintf("%s: Error: Unsupported board ID (%d)\n", __func__, val);
+ return MV_ERROR;
+ }
}
/* The Board Id is taken from the first address-value pair of the EEPROM initalization sequnce
@@ -2367,6 +2806,29 @@
}
/*******************************************************************************
+* mvBoardConfigAutoDetectEnabled
+*
+* DESCRIPTION:
+* Indicate if the board supports auto configuration and detection of
+* modules. This is usually enabled for DB boards only.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if auto-config/detection is enabled.
+* MV_FALSE otherwise.
+*
+*******************************************************************************/
+MV_BOOL mvBoardConfigAutoDetectEnabled()
+{
+ return board->configAutoDetect;
+}
+
+/*******************************************************************************
* mvBoardDebugLeg - Set the board debug Leds
*
* DESCRIPTION: turn on/off status leds.
@@ -2460,6 +2922,53 @@
return MV_NFC_ECC_DISABLE;
#endif
}
+/*******************************************************************************
+* mvBoardCompatibleNameGet
+*
+* DESCRIPTION: return string containing 'compatible' property value
+* needed for Device Tree auto-update parsing sequence
+*
+* INPUT: None
+* OUTPUT: None.
+*
+* RETURN: length of returned string (including special delimiters)
+*
+*******************************************************************************/
+MV_U8 mvBoardCompatibleNameGet(char *pNameBuff)
+{
+ MV_U8 len = 0;
+ MV_U32 boardId;
+ /* i.e: compatible = "marvell,msys", "marvell,msys-bc2", "marvell,msys-bc2-db", "marvell,armada-370-xp"; */
+ len = sprintf(pNameBuff, "marvell,msys") + 1;
+ /*
+ * append next strings after the NULL character that the previous
+ * sprintf wrote. This is how a device tree stores multiple
+ * strings in a property.
+ */
+ boardId = mvBoardIdGet();
+ if (boardId >= BC2_MARVELL_BOARD_ID_BASE && boardId < BC2_MARVELL_MAX_BOARD_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-bc2") + 1;
+ len += sprintf(pNameBuff + len, "marvell,msys-bc2-db") + 1;
+ } else if (boardId >= AC3_MARVELL_BOARD_ID_BASE && boardId < AC3_MARVELL_MAX_BOARD_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-ac3") + 1;
+ len += sprintf(pNameBuff + len, "marvell,msys-ac3-db") + 1;
+ } else if (boardId >= BOBK_MARVELL_BOARD_ID_BASE && boardId < BOBK_MARVELL_MAX_BOARD_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk") + 1;
+ if (boardId == BOBK_CETUS_DB_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-cetus") + 1;
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-cetus-db") + 1;
+ } else if (boardId == BOBK_CAELUM_DB_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-caelum") + 1;
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-caelum-db") + 1;
+ } else if (boardId == BOBK_LEWIS_RD_ID) {
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-lewis") + 1;
+ len += sprintf(pNameBuff + len, "marvell,msys-bobk-lewis-rd") + 1;
+ }
+ }
+ len += sprintf(pNameBuff + len, "marvell,armada-370-xp") + 1;
+
+ return len;
+}
MV_NAND_IF_MODE mvBoardNandIfGet()
{
@@ -2530,3 +3039,141 @@
return MV_OK;
}
+/*******************************************************************************
+* mvBoardisAmc
+* DESCRIPTION: MSYS platform are not AMC compliant - return always false
+*
+* INPUT: None
+* OUTPUT: None.
+* RETURN: MV_FALSE
+*******************************************************************************/
+MV_BOOL mvBoardisAmc(void)
+{
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvBoardPPSmiIndexGet
+* DESCRIPTION: Get the PP SMI index for the board
+*
+* INPUT: None
+* OUTPUT: PP SMI index.
+* RETURN: MV_TRUE
+*******************************************************************************/
+MV_STATUS mvBoardPPSmiIndexGet(MV_U32 *index)
+{
+ *index = board->smiExternalPpIndex;
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvBoardUpdateConfigforDT
+* DESCRIPTION: Update board configuration structure for DT update
+*
+* INPUT: None.
+* OUTPUT: None.
+* RETURN: None.
+*******************************************************************************/
+MV_VOID mvBoardUpdateConfigforDT(MV_VOID)
+{
+
+}
+
+#ifdef CONFIG_MMC
+/*******************************************************************************
+* mvBoardisSdioConnected
+* DESCRIPTION: return true if SDIO connected on board
+*
+* INPUT: None
+* OUTPUT: None.
+* RETURN: MV_TRUE:SDIO connected on board
+* MV_FALSE: else
+*******************************************************************************/
+MV_BOOL mvBoardisSdioConnected(void)
+{
+ return board->isSdMmcConnected;
+}
+#endif
+
+/*******************************************************************************
+* mvBoardGetModelName
+*
+* DESCRIPTION:
+* This function returns a string describing the board model.
+*
+* OUTPUT:
+* pNameBuff - Buffer to contain board model name string. Minimum size 128 chars.
+*
+*******************************************************************************/
+void mvBoardGetModelName(char *pNameBuff)
+{
+ mvOsSPrintf(pNameBuff, "Marvell MSYS %s %s", board->modelName, board->boardName);
+}
+
+/*******************************************************************************
+* mvBoardIsPpSmi
+* DESCRIPTION:
+* checks whether PP_SMI is used or not
+*
+* INPUT: None
+* OUTPUT: None.
+* RETURN: MV_TRUE PP_SMI is used
+* MV_FALSE otherwise
+*******************************************************************************/
+MV_BOOL mvBoardIsPpSmi(void)
+{
+ return board->isSmiExternalPp;
+}
+
+/*******************************************************************************
+* mvBoardPinCtrlNameGet
+*
+* DESCRIPTION:
+* This function returns the compatible string of pinctrl
+*
+* OUTPUT:
+* compatibleBuf - Buffer to contain pinctrl compatible string
+*
+*******************************************************************************/
+void mvBoardPinCtrlNameGet(char *compatibleBuf)
+{
+ mvOsSPrintf(compatibleBuf, "marvell,bc2-ac3-pinctrl");
+}
+
+#ifdef MV_CM3
+/*******************************************************************************
+* mvBoardIsCm3
+* DESCRIPTION:
+* checks whether CM3 is used or not
+*
+* INPUT: None
+* OUTPUT: None.
+* RETURN: MV_TRUE CM3 is used
+* MV_FALSE otherwise
+*******************************************************************************/
+MV_BOOL mvBoardIsCm3(void)
+{
+ return board->isCm3;
+}
+
+/*******************************************************************************
+* mvBoardCm3CompatibleNameGet
+*
+* DESCRIPTION:
+* This function returns the compatible string of cm3
+*
+* OUTPUT:
+* compatibleBuf - Buffer to contain cm3 compatible string
+*
+*******************************************************************************/
+void mvBoardCm3CompatibleNameGet(char *compatibleBuf)
+{
+ if (gBoardId >= BOBK_MARVELL_BOARD_ID_BASE &&
+ gBoardId < BOBK_MARVELL_MAX_BOARD_ID)
+ mvOsSPrintf(compatibleBuf, "marvell,msys-bobk-cm3");
+ else if (gBoardId >= BC2_MARVELL_BOARD_ID_BASE &&
+ gBoardId < BC2_MARVELL_MAX_BOARD_ID)
+ mvOsSPrintf(compatibleBuf, "marvell,msys-bc2-cm3");
+
+}
+#endif
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
index 6c79636..904fea8 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
@@ -83,6 +83,14 @@
#define MV_BOARD_MAX_MPP 9 /* number of MPP conf registers */
#define MV_BOARD_NAME_LEN 0x20
+#define MV_BOARD_MODEL_NAME_LEN 0x50
+
+enum {
+ MV_PORT_TYPE_SGMII,
+ MV_PORT_TYPE_QSGMII,
+ MV_PORT_TYPE_RGMII,
+ MV_PORT_TYPE_UNKNOWN = -1,
+};
typedef enum _devBoardMppTypeClass {
MV_BOARD_AUTO = 0,
@@ -153,6 +161,8 @@
MV_U32 devClass; /* MV_BOARD_DEV_CLASS */
MV_U8 devWidth;
MV_U8 busWidth;
+ MV_U8 busNum;
+ MV_BOOL active;
} MV_DEV_CS_INFO;
typedef struct _boardSwitchInfo {
@@ -187,6 +197,7 @@
MV_BOARD_MAC_SPEED boardMacSpeed;
MV_32 boardEthSmiAddr;
MV_32 boardEthSmiAddr0;
+ MV_BOOL boardMacEnabled;
} MV_BOARD_MAC_INFO;
typedef struct _boardMppInfo {
@@ -255,7 +266,16 @@
MV_BOARD_PEX_INFO boardPexInfo; /* filled in runtime */
MV_U32 norFlashReadParams;
MV_U32 norFlashWriteParams;
+ MV_BOOL isSmiExternalPp;
+ MV_U32 smiExternalPpIndex;
+ MV_BOOL isSdMmcConnected;
+ /* Indicates if auto-detection of modules is enabled on this board. */
+ /* Set to MV_FALSE for any board that is not a DB. */
+ MV_BOOL configAutoDetect;
+
+ char modelName[MV_BOARD_MODEL_NAME_LEN];
+ MV_BOOL isCm3;
} MV_BOARD_INFO;
MV_VOID mvBoardEnvInit(MV_VOID);
@@ -266,11 +286,13 @@
MV_BOOL mvBoardIsEthActive(MV_U32 ethNum);
MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInGmii(MV_U32 ethPortNum);
+MV_U32 mvBoardPortTypeGet(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInMii(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum);
MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum);
MV_32 mvBoardQuadPhyAddr0Get(MV_U32 ethPortNum);
MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx);
+MV_BOOL mvBoardConfigAutoDetectEnabled(void);
MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx);
MV_U32 mvBoardTclkGet(MV_VOID);
MV_U32 mvBoardSysClkGet(MV_VOID);
@@ -289,6 +311,9 @@
MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_U32 mvBoardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_U32 mvBoardGetDevBusNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_BOOL mvBoardGetDevState(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_STATUS mvBoardSetDevState(MV_32 devNum, MV_BOARD_DEV_CLASS devClass, MV_BOOL newState);
MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index);
MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index);
MV_32 mvBoardNandWidthGet(void);
@@ -330,6 +355,8 @@
MV_STATUS mvBoardDramBusWidthSet(MV_U16 conf);
MV_U16 mvBoardDramBusWidthGet(MV_VOID);
MV_STATUS mvBoardCoreFreqGet(MV_U8 *value);
+MV_STATUS mvBoardBypassCoreFreqGet(MV_U8 *value);
+MV_STATUS mvBoardBypassCoreFreqSet(MV_U8 freqVal);
MV_STATUS mvBoardTmFreqGet(MV_U8 *value);
MV_STATUS mvBoardTmFreqSet(MV_U8 freqVal);
MV_STATUS mvBoardJtagCpuGet(MV_U8 *value);
@@ -362,12 +389,28 @@
MV_VOID mvBoardDebugLed(MV_U32 hexNum);
MV_NFC_ECC_MODE mvBoardNandECCModeGet(void);
MV_U32 mvBoardCpssBoardIdSet(MV_U8);
+MV_U8 mvBoardCompatibleNameGet(char *pNameBuff);
MV_NAND_IF_MODE mvBoardNandIfGet(void);
MV_STATUS mvBoardOobPortCfgSet(MV_VOID);
+MV_BOOL mvBoardIsUsbPortConnected(MV_UNIT_ID usbTypeID, MV_U8 usbPortNumber);
+MV_BOOL mvBoardisAmc(void);
+MV_STATUS mvBoardPPSmiIndexGet(MV_U32 *index);
+MV_VOID mvBoardUpdateConfigforDT(MV_VOID);
+#ifdef CONFIG_MMC
+MV_BOOL mvBoardisSdioConnected(void);
+#endif
+void mvBoardGetModelName(char *pNameBuff);
+MV_BOOL mvBoardIsPpSmi(void);
+void mvBoardPinCtrlNameGet(char *compatibleBuf);
+#ifdef MV_CM3
+MV_BOOL mvBoardIsCm3(void);
+void mvBoardCm3CompatibleNameGet(char *compatibleBuf);
+#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
+extern MV_BOARD_INFO *marvellAXPboardInfoTbl[];
#endif /* __INCmvBoardEnvLibh */
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
index 7450bf8..55721f5 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
@@ -98,8 +98,8 @@
MV_BOARD_MAC_INFO bobcat2_customer_board_0_InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_AUTO, 0x0, 0x0 },
- {BOARD_MAC_SPEED_AUTO, 0x1, 0x1 },
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, 0x1, 0x1, MV_TRUE},
};
MV_BOARD_MODULE_TYPE_INFO bobcat2_customer_board_0_InfoBoardModTypeInfo[] = {
@@ -109,12 +109,17 @@
};
MV_DEV_CS_INFO bobcat2_customer_board_0_InfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth, busWidth }*/
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
#endif
-#if defined(MV_INCLUDE_NOR)
- {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */
+#if defined(MV_INCLUDE_NOR) && defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE}, /* NAND DEV */
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#elif defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#elif defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
#endif
};
@@ -170,7 +175,8 @@
.nandFlashControl = BOBCAT2_CUSTOMER_0_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = BOBCAT2_CUSTOMER_0_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = BOBCAT2_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = BOBCAT2_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_FALSE /* Enable modules auto-detection. */
};
MV_BOARD_INFO *customerBC2BoardInfoTbl[] = {
@@ -178,6 +184,230 @@
&bobcat2_customer_board_0_Info,
};
+/*******************************************************************************
+ BobK Cetus customer board - Based on BOBK-CETUS-DB-98DX4235-12XG
+*******************************************************************************/
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_READ_PARAMS 0x000C0282
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS 0x00010305
+/*NAND care support for small page chips*/
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_CONTROL 0x01c00543
+
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NOR_READ_PARAMS 0x403E07CF
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
+
+MV_BOARD_TWSI_INFO bobk_cetus_customer_board_0_InfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO bobk_cetus_customer_board_0_InfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO bobk_cetus_customer_board_0_InfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+MV_DEV_CS_INFO bobk_cetus_customer_board_0_InfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO bobk_cetus_customer_board_0_InfoBoardMppConfigValue[] = {
+ { {
+ BOBK_CETUS_CUSTOMER_0_MPP0_7,
+ BOBK_CETUS_CUSTOMER_0_MPP8_15,
+ BOBK_CETUS_CUSTOMER_0_MPP16_23,
+ BOBK_CETUS_CUSTOMER_0_MPP24_31,
+ BOBK_CETUS_CUSTOMER_0_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO bobk_cetus_customer_board_0_Info = {
+ .boardName = "BOBK-Cetus-Customer-Board-0",
+ .numBoardMppTypeValue = ARRSZ(bobk_cetus_customer_board_0_InfoBoardModTypeInfo),
+ .pBoardModTypeValue = bobk_cetus_customer_board_0_InfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(bobk_cetus_customer_board_0_InfoBoardMppConfigValue),
+ .pBoardMppConfigValue = bobk_cetus_customer_board_0_InfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(bobk_cetus_customer_board_0_InfoBoardDeCsInfo),
+ .pDevCsInfo = bobk_cetus_customer_board_0_InfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bobk_cetus_customer_board_0_InfoBoardTwsiDev),
+ .pBoardTwsiDev = bobk_cetus_customer_board_0_InfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(bobk_cetus_customer_board_0_InfoBoardMacInfo),
+ .pBoardMacInfo = bobk_cetus_customer_board_0_InfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_LOW,
+ .gppOutValMid = BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = BOBK_CETUS_CUSTOMER_0_GPP_POL_LOW,
+ .gppPolarityValMid = BOBK_CETUS_CUSTOMER_0_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = BOBK_CETUS_CUSTOMER_0_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = BOBK_CETUS_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 0,
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_FALSE /* Enable modules auto-detection. */
+};
+
+/*******************************************************************************
+ BobK Caelum customer board - Based on BOBK-CAELUM-DB-98DX4203-48G12XG
+*******************************************************************************/
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_READ_PARAMS 0x000C0282
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_WRITE_PARAMS 0x00010305
+/*NAND care support for small page chips*/
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_CONTROL 0x01c00543
+
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_READ_PARAMS 0x403E07CF
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
+
+MV_BOARD_TWSI_INFO bobk_caelum_customer_board_1_InfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9555_IO_EXPANDER, 0x20, ADDR7_BIT}, /* Qsgmii/sfp mux control PCA9555 IO expander */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO bobk_caelum_customer_board_1_InfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO bobk_caelum_customer_board_1_InfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+MV_DEV_CS_INFO bobk_caelum_customer_board_1_InfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO bobk_caelum_customer_board_1_InfoBoardMppConfigValue[] = {
+ { {
+ BOBK_CAELUM_CUSTOMER_1_MPP0_7,
+ BOBK_CAELUM_CUSTOMER_1_MPP8_15,
+ BOBK_CAELUM_CUSTOMER_1_MPP16_23,
+ BOBK_CAELUM_CUSTOMER_1_MPP24_31,
+ BOBK_CAELUM_CUSTOMER_1_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO bobk_caelum_customer_board_1_Info = {
+ .boardName = "BOBK-Caelum-Customer-Board-1",
+ .numBoardMppTypeValue = ARRSZ(bobk_caelum_customer_board_1_InfoBoardModTypeInfo),
+ .pBoardModTypeValue = bobk_caelum_customer_board_1_InfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(bobk_caelum_customer_board_1_InfoBoardMppConfigValue),
+ .pBoardMppConfigValue = bobk_caelum_customer_board_1_InfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(bobk_caelum_customer_board_1_InfoBoardDeCsInfo),
+ .pDevCsInfo = bobk_caelum_customer_board_1_InfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bobk_caelum_customer_board_1_InfoBoardTwsiDev),
+ .pBoardTwsiDev = bobk_caelum_customer_board_1_InfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(bobk_caelum_customer_board_1_InfoBoardMacInfo),
+ .pBoardMacInfo = bobk_caelum_customer_board_1_InfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_LOW,
+ .gppOutValMid = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = BOBK_CAELUM_CUSTOMER_1_GPP_POL_LOW,
+ .gppPolarityValMid = BOBK_CAELUM_CUSTOMER_1_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 1,
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_FALSE /* Enable modules auto-detection. */
+};
+
+
+MV_BOARD_INFO *customerBOBKBoardInfoTbl[] = {
+ &bobk_cetus_customer_board_0_Info,
+ &bobk_caelum_customer_board_1_Info,
+};
/*******************************************************************************
Alleycat3 board - Based on BOBCAT2-DB-DX
@@ -207,8 +437,8 @@
MV_BOARD_MAC_INFO alleycat3_customer_board_0_InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_AUTO, -1, -1 },
- {BOARD_MAC_SPEED_AUTO, -1, -1 }
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE}
};
MV_BOARD_MODULE_TYPE_INFO alleycat3_customer_board_0_InfoBoardModTypeInfo[] = {
@@ -218,12 +448,17 @@
};
MV_DEV_CS_INFO alleycat3_customer_board_0_InfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth, busWidth }*/
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
#endif
-#if defined(MV_INCLUDE_NOR)
- {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */
+#if defined(MV_INCLUDE_NOR) && defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE}, /* NAND DEV */
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#elif defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#elif defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
#endif
};
@@ -279,7 +514,8 @@
.nandFlashControl = ALLEYCAT3_CUSTOMER_0_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = ALLEYCAT3_CUSTOMER_0_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = ALLEYCAT3_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = ALLEYCAT3_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_FALSE /* Enable modules auto-detection. */
};
MV_BOARD_INFO *customerAC3BoardInfoTbl[] = {
@@ -316,8 +552,8 @@
MV_BOARD_MAC_INFO db_dx_bc2InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_AUTO, -1, -1 },
- {BOARD_MAC_SPEED_AUTO, -1, -1 },
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE},
};
MV_BOARD_MODULE_TYPE_INFO db_dx_bc2InfoBoardModTypeInfo[] = {
@@ -327,12 +563,17 @@
};
MV_DEV_CS_INFO db_dx_bc2InfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth, busWidth }*/
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
#endif
-#if defined(MV_INCLUDE_NOR)
- {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 8, 8} /* NOR DEV */
+#if defined(MV_INCLUDE_NOR) && defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE}, /* NAND DEV */
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#elif defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#elif defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
#endif
};
@@ -393,7 +634,12 @@
.nandFlashControl = DB_DX_BC2_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_BC2_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_BC2_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_BC2_BOARD_NOR_WRITE_PARAMS,
+ .modelName = "BobCat2 Development Board",
+ .isSmiExternalPp = MV_FALSE,
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .isCm3 = MV_TRUE
};
/**********************************************************************************/
@@ -407,8 +653,7 @@
MV_BOARD_MAC_INFO rd_dx_bc2InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_1000M, 0x0, 0x0 },
- {BOARD_MAC_SPEED_1000M, 0x1, 0x1 },
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
MV_BOARD_MODULE_TYPE_INFO rd_dx_bc2InfoBoardModTypeInfo[] = {
@@ -418,9 +663,12 @@
};
MV_DEV_CS_INFO rd_dx_bc2InfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth}*/
+ /*{deviceCS, params, devType, devWidth, busNum, active}*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
#endif
};
@@ -473,7 +721,12 @@
/* NAND init params */
.nandFlashReadParams = RD_DX_BC2_BOARD_NAND_READ_PARAMS,
.nandFlashWriteParams = RD_DX_BC2_BOARD_NAND_WRITE_PARAMS,
- .nandFlashControl = RD_DX_BC2_BOARD_NAND_CONTROL
+ .nandFlashControl = RD_DX_BC2_BOARD_NAND_CONTROL,
+ .modelName = "BobCat2 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE,
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .isCm3 = MV_TRUE
};
/**********************************************************************************/
@@ -485,10 +738,15 @@
/*NAND care support for small page chips*/
#define RD_MTL_BC2_BOARD_NAND_CONTROL 0x01c00543
+MV_BOARD_TWSI_INFO bc2_rd_mtlInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x77, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Ini EPROM */
+};
+
MV_BOARD_MAC_INFO bc2_rd_mtlInfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_1000M, 0x0, 0x0 },
- {BOARD_MAC_SPEED_1000M, 0x1, 0x1 },
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
MV_BOARD_MODULE_TYPE_INFO bc2_rd_mtlInfoBoardModTypeInfo[] = {
@@ -498,9 +756,12 @@
};
MV_DEV_CS_INFO bc2_rd_mtlInfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth}*/
+ /*{deviceCS, params, devType, devWidth, busNum, active}*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
#endif
};
@@ -515,24 +776,24 @@
};
MV_BOARD_INFO bc2_rd_mtlInfo = {
- .boardName = "RD-BC2-MTL-PoE-2QSFP-6SFP",
+ .boardName = "RD-MTL-BC2-48G-12XG2XLG",
.numBoardMppTypeValue = ARRSZ(bc2_rd_mtlInfoBoardModTypeInfo),
- .pBoardModTypeValue = bc2_rd_mtlInfoBoardModTypeInfo,
+ .pBoardModTypeValue = bc2_rd_mtlInfoBoardModTypeInfo,
.numBoardMppConfigValue = ARRSZ(bc2_rd_mtlInfoBoardMppConfigValue),
.pBoardMppConfigValue = bc2_rd_mtlInfoBoardMppConfigValue,
.intsGppMaskLow = 0,
.intsGppMaskMid = 0,
.intsGppMaskHigh = 0,
.numBoardDeviceIf = ARRSZ(bc2_rd_mtlInfoBoardDeCsInfo),
- .pDevCsInfo = bc2_rd_mtlInfoBoardDeCsInfo,
- .numBoardTwsiDev = 0,
- .pBoardTwsiDev = NULL,
+ .pDevCsInfo = bc2_rd_mtlInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bc2_rd_mtlInfoBoardTwsiDev),
+ .pBoardTwsiDev = bc2_rd_mtlInfoBoardTwsiDev,
.numBoardMacInfo = ARRSZ(bc2_rd_mtlInfoBoardMacInfo),
.pBoardMacInfo = bc2_rd_mtlInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = NULL,
.activeLedsNumber = 0,
- .pLedGppPin = NULL,
+ .pLedGppPin = NULL,
.ledsPolarity = 0,
/* GPP values */
@@ -551,9 +812,339 @@
.switchInfoNum = 0,
/* NAND init params */
- .nandFlashReadParams = RD_MTL_BC2_BOARD_NAND_READ_PARAMS,
- .nandFlashWriteParams = RD_MTL_BC2_BOARD_NAND_WRITE_PARAMS,
- .nandFlashControl = RD_MTL_BC2_BOARD_NAND_CONTROL
+ .nandFlashReadParams = RD_MTL_BC2_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = RD_MTL_BC2_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = RD_MTL_BC2_BOARD_NAND_CONTROL,
+ .modelName = "BobCat2 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE,
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .isCm3 = MV_TRUE
+};
+
+/*********************************************************************************/
+/*************************************/
+/* BOBK-CETUS-DB-98DX4235-12XG BOARD */
+/*************************************/
+#define DB_DX_BOBK_BOARD_NAND_READ_PARAMS 0x000C0282
+#define DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS 0x00010305
+/*NAND care support for small page chips*/
+#define DB_DX_BOBK_BOARD_NAND_CONTROL 0x01c00543
+
+#define DB_DX_BOBK_BOARD_NOR_READ_PARAMS 0x403E07CF
+#define DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
+
+/* TODO */
+MV_BOARD_TWSI_INFO db_dx_bobkCetusInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO db_dx_bobkCetusInfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO db_dx_bobkCetusInfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+/* TO DE */
+MV_DEV_CS_INFO db_dx_bobkCetusInfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO db_dx_bobkCetusInfoBoardMppConfigValue[] = {
+ { {
+#if defined(MV_INCLUDE_NOR)
+ DB_DX_BOBK_CETUS_NOR_MPP0_7,
+ DB_DX_BOBK_CETUS_NOR_MPP8_15,
+#else
+ DB_DX_BOBK_CETUS_MPP0_7,
+ DB_DX_BOBK_CETUS_MPP8_15,
+#endif
+ DB_DX_BOBK_CETUS_MPP16_23,
+ DB_DX_BOBK_CETUS_MPP24_31,
+ DB_DX_BOBK_CETUS_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO db_dx_bobkCetusInfo = {
+ .boardName = "DB-98DX4235-12XG",
+ .numBoardMppTypeValue = ARRSZ(db_dx_bobkCetusInfoBoardModTypeInfo),
+ .pBoardModTypeValue = db_dx_bobkCetusInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(db_dx_bobkCetusInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db_dx_bobkCetusInfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(db_dx_bobkCetusInfoBoardDeCsInfo),
+ .pDevCsInfo = db_dx_bobkCetusInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(db_dx_bobkCetusInfoBoardTwsiDev),
+ .pBoardTwsiDev = db_dx_bobkCetusInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(db_dx_bobkCetusInfoBoardMacInfo),
+ .pBoardMacInfo = db_dx_bobkCetusInfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = DB_DX_BOBK_CETUS_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = DB_DX_BOBK_CETUS_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = DB_DX_BOBK_CETUS_GPP_OUT_VAL_LOW,
+ .gppOutValMid = DB_DX_BOBK_CETUS_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = DB_DX_BOBK_CETUS_GPP_POL_LOW,
+ .gppPolarityValMid = DB_DX_BOBK_CETUS_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = DB_DX_BOBK_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = DB_DX_BOBK_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = DB_DX_BOBK_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 0,
+ .modelName = "BobK Cetus Development Board",
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .isCm3 = MV_TRUE
+};
+
+/*********************************************************************************/
+/**************************************/
+/* BOBK-CAELUM-DB-98DX4203-48G12XG BOARD */
+/**************************************/
+
+MV_BOARD_TWSI_INFO db_dx_bobkCaelumInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9555_IO_EXPANDER, 0x20, ADDR7_BIT}, /* Qsgmii/sfp mux control PCA9555 IO expander */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO db_dx_bobkCaelumInfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO db_dx_bobkCaelumInfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+/* TO DE */
+MV_DEV_CS_INFO db_dx_bobkCaelumInfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO db_dx_bobkCaelumInfoBoardMppConfigValue[] = {
+ { {
+#if defined(MV_INCLUDE_NOR)
+ DB_DX_BOBK_CAELUM_NOR_MPP0_7,
+ DB_DX_BOBK_CAELUM_NOR_MPP8_15,
+#else
+ DB_DX_BOBK_CAELUM_MPP0_7,
+ DB_DX_BOBK_CAELUM_MPP8_15,
+#endif
+ DB_DX_BOBK_CAELUM_MPP16_23,
+ DB_DX_BOBK_CAELUM_MPP24_31,
+ DB_DX_BOBK_CAELUM_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO db_dx_bobkCaelumInfo = {
+ .boardName = "DB-98DX4203-48G12XG",
+ .numBoardMppTypeValue = ARRSZ(db_dx_bobkCaelumInfoBoardModTypeInfo),
+ .pBoardModTypeValue = db_dx_bobkCaelumInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(db_dx_bobkCaelumInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db_dx_bobkCaelumInfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(db_dx_bobkCaelumInfoBoardDeCsInfo),
+ .pDevCsInfo = db_dx_bobkCaelumInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(db_dx_bobkCaelumInfoBoardTwsiDev),
+ .pBoardTwsiDev = db_dx_bobkCaelumInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(db_dx_bobkCaelumInfoBoardMacInfo),
+ .pBoardMacInfo = db_dx_bobkCaelumInfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = DB_DX_BOBK_CAELUM_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = DB_DX_BOBK_CAELUM_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = DB_DX_BOBK_CAELUM_GPP_OUT_VAL_LOW,
+ .gppOutValMid = DB_DX_BOBK_CAELUM_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = DB_DX_BOBK_CAELUM_GPP_POL_LOW,
+ .gppPolarityValMid = DB_DX_BOBK_CAELUM_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = DB_DX_BOBK_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = DB_DX_BOBK_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = DB_DX_BOBK_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 1,
+ .modelName = "BobK Caelum Development Board",
+ .isSdMmcConnected = MV_TRUE,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .isCm3 = MV_TRUE
+};
+
+/*********************************************************************************/
+/**************************************/
+/* BOBK-LEWIS-RD-LWS-12XG-A BOARD */
+/**************************************/
+
+
+MV_BOARD_TWSI_INFO rd_dx_bobkLewisInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+};
+
+
+MV_BOARD_MAC_INFO rd_dx_bobkLewisInfoBoardMacInfo[] = {
+/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO rd_dx_bobkLewisInfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+/* TO DE */
+MV_DEV_CS_INFO rd_dx_bobkLewisInfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO rd_dx_bobkLewisInfoBoardMppConfigValue[] = {
+ { {
+ RD_DX_BOBK_LEWIS_MPP0_7,
+ RD_DX_BOBK_LEWIS_MPP8_15,
+ RD_DX_BOBK_LEWIS_MPP16_23,
+ RD_DX_BOBK_LEWIS_MPP24_31,
+ RD_DX_BOBK_LEWIS_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO rd_dx_bobkLewisInfo = {
+ .boardName = "RD-LWS-12XG-A",
+ .numBoardMppTypeValue = ARRSZ(rd_dx_bobkLewisInfoBoardModTypeInfo),
+ .pBoardModTypeValue = rd_dx_bobkLewisInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(rd_dx_bobkLewisInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = rd_dx_bobkLewisInfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(rd_dx_bobkLewisInfoBoardDeCsInfo),
+ .pDevCsInfo = rd_dx_bobkLewisInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(rd_dx_bobkLewisInfoBoardTwsiDev),
+ .pBoardTwsiDev = rd_dx_bobkLewisInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(rd_dx_bobkLewisInfoBoardMacInfo),
+ .pBoardMacInfo = rd_dx_bobkLewisInfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = RD_DX_BOBK_LEWIS_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = RD_DX_BOBK_LEWIS_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = RD_DX_BOBK_LEWIS_GPP_OUT_VAL_LOW,
+ .gppOutValMid = RD_DX_BOBK_LEWIS_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = RD_DX_BOBK_LEWIS_GPP_POL_LOW,
+ .gppPolarityValMid = RD_DX_BOBK_LEWIS_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = DB_DX_BOBK_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = DB_DX_BOBK_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = DB_DX_BOBK_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 0,
+ .modelName = "BobK Lewis Reference Design Board",
+ .isSdMmcConnected = MV_TRUE
};
/*********************************************************************************/
@@ -584,8 +1175,8 @@
MV_BOARD_MAC_INFO db_dx_ac3InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
- {BOARD_MAC_SPEED_AUTO, -1, -1 },
- {BOARD_MAC_SPEED_AUTO, -1, -1 }
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_TRUE}
};
MV_BOARD_MODULE_TYPE_INFO db_dx_ac3InfoBoardModTypeInfo[] = {
@@ -595,12 +1186,17 @@
};
MV_DEV_CS_INFO db_dx_ac3InfoBoardDeCsInfo[] = {
- /*{deviceCS, params, devType, devWidth, busWidth }*/
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
#if defined(MV_INCLUDE_SPI)
- {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
#endif
-#if defined(MV_INCLUDE_NOR)
- {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */
+#if defined(MV_INCLUDE_NOR) && defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE}, /* NAND DEV */
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#elif defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#elif defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
#endif
};
@@ -656,7 +1252,10 @@
.nandFlashControl = DB_DX_AC3_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_AC3_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AlleyCat3 Development Board",
+ .isSmiExternalPp = MV_FALSE
};
/*********************************************************************************/
@@ -715,7 +1314,10 @@
.nandFlashControl = DB_DX_AC3_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_AC3_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AlleyCat3 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE
};
/*********************************************************************************/
/***********************************/
@@ -773,12 +1375,15 @@
.nandFlashControl = DB_DX_AC3_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_AC3_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AlleyCat3 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE
};
/*********************************************************************************/
/***********************************/
-/* ALLEYCAT3-DB-MISL-24G BOARD */
+/* ALLEYCAT3-RD-MTL-2XXG-2XG BOARD */
/***********************************/
MV_BOARD_MPP_INFO db_misl_24G_46_ac3InfoBoardMppConfigValue[] = {
{ {
@@ -791,11 +1396,11 @@
};
MV_BOARD_INFO db_misl_24G_4xg_ac3Info = {
- .boardName = "DB-XC3-24G-4G",
- .numBoardMppTypeValue = ARRSZ(db_dx_ac3InfoBoardModTypeInfo),
+ .boardName = "DB-XC3-24G-4G",
+ .numBoardMppTypeValue = ARRSZ(db_dx_ac3InfoBoardModTypeInfo),
.pBoardModTypeValue = db_dx_ac3InfoBoardModTypeInfo,
- .numBoardMppConfigValue = ARRSZ(db_misl_24G_46_ac3InfoBoardMppConfigValue),
- .pBoardMppConfigValue = db_misl_24G_46_ac3InfoBoardMppConfigValue,
+ .numBoardMppConfigValue = ARRSZ(db_misl_24G_46_ac3InfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db_misl_24G_46_ac3InfoBoardMppConfigValue,
.intsGppMaskLow = 0,
.intsGppMaskMid = 0,
.intsGppMaskHigh = 0,
@@ -832,7 +1437,10 @@
.nandFlashControl = DB_DX_AC3_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_AC3_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AlleyCat3 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE
};
/*********************************************************************************/
@@ -862,8 +1470,8 @@
.pDevCsInfo = db_dx_ac3InfoBoardDeCsInfo,
.numBoardTwsiDev = ARRSZ(db_dx_ac3InfoBoardTwsiDev),
.pBoardTwsiDev = db_dx_ac3InfoBoardTwsiDev,
- .numBoardMacInfo = 0,
- .pBoardMacInfo = NULL,
+ .numBoardMacInfo = ARRSZ(db_dx_ac3InfoBoardMacInfo),
+ .pBoardMacInfo = db_dx_ac3InfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = NULL,
.activeLedsNumber = 0,
@@ -882,18 +1490,122 @@
.gppPolarityValHigh = 0,
/* External Switch Configuration */
- .pSwitchInfo = NULL,
- .switchInfoNum = 0,
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
/* NAND init params */
- .nandFlashReadParams = DB_DX_AC3_BOARD_NAND_READ_PARAMS,
- .nandFlashWriteParams = DB_DX_AC3_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashReadParams = DB_DX_AC3_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_DX_AC3_BOARD_NAND_WRITE_PARAMS,
.nandFlashControl = DB_DX_AC3_BOARD_NAND_CONTROL,
/* NOR init params */
.norFlashReadParams = DB_DX_AC3_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS
+ .norFlashWriteParams = DB_DX_AC3_BOARD_NOR_WRITE_PARAMS,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AlleyCat3 Reference Design Board",
+ .isSmiExternalPp = MV_FALSE
};
+/***************************************************************************************/
+/* ARMADA-XP AMC BOARD - only for Linux usage (AXP family is shared with MSYS in LSP) */
+/***************************************************************************************/
+#define DB_78X60_AMC_BOARD_NAND_READ_PARAMS 0x000C0282
+#define DB_78X60_AMC_BOARD_NAND_WRITE_PARAMS 0x00010305
+/*NAND care support for small page chips*/
+#define DB_78X60_AMC_BOARD_NAND_CONTROL 0x01c00543
+
+MV_U8 db78X60amcInfoBoardDebugLedIf[] = {53, 54, 55, 56}; /* 7 segment MPPs*/
+
+MV_BOARD_TWSI_INFO db78X60amcInfoBoardTwsiDev[] = {
+ /* No TWSI devices on board*/
+};
+
+MV_BOARD_MAC_INFO db78X60amcInfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {BOARD_MAC_SPEED_AUTO, 0x1, 0x0, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, 0xD, 0x0, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, 0xC, 0x0, MV_TRUE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE}
+};
+
+
+MV_BOARD_MODULE_TYPE_INFO db78X60amcInfoBoardModTypeInfo[] = {
+ /* No Modules */
+};
+
+MV_BOARD_GPP_INFO db78X60amcInfoBoardGppInfo[] = {
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {BOARD_GPP_USB_VBUS, 46} /* from MPP map */
+};
+
+MV_DEV_CS_INFO db78X60amcInfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0_AXP, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO db78X60amcInfoBoardMppConfigValue[] = {
+ { {
+ DB_78X60_AMC_MPP0_7,
+ DB_78X60_AMC_MPP8_15,
+ DB_78X60_AMC_MPP16_23,
+ DB_78X60_AMC_MPP24_31,
+ DB_78X60_AMC_MPP32_39,
+ DB_78X60_AMC_MPP40_47,
+ DB_78X60_AMC_MPP48_55,
+ DB_78X60_AMC_MPP56_63,
+ DB_78X60_AMC_MPP64_67,
+ } }
+};
+
+MV_BOARD_INFO db78X60amcInfo = {
+ .boardName = "DB-78460-AMC",
+ .numBoardMppTypeValue = ARRSZ(db78X60amcInfoBoardModTypeInfo),
+ .pBoardModTypeValue = db78X60amcInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(db78X60amcInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db78X60amcInfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(db78X60amcInfoBoardDeCsInfo),
+ .pDevCsInfo = db78X60amcInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(db78X60amcInfoBoardTwsiDev),
+ .pBoardTwsiDev = db78X60amcInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(db78X60amcInfoBoardMacInfo),
+ .pBoardMacInfo = db78X60amcInfoBoardMacInfo,
+ .numBoardGppInfo = ARRSZ(db78X60amcInfoBoardGppInfo),
+ .pBoardGppInfo = db78X60amcInfoBoardGppInfo,
+ .activeLedsNumber = ARRSZ(db78X60amcInfoBoardDebugLedIf),
+ .pLedGppPin = db78X60amcInfoBoardDebugLedIf,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = DB_78X60_AMC_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = DB_78X60_AMC_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = DB_78X60_AMC_GPP_OUT_ENA_HIGH,
+ .gppOutValLow = DB_78X60_AMC_GPP_OUT_VAL_LOW,
+ .gppOutValMid = DB_78X60_AMC_GPP_OUT_VAL_MID,
+ .gppOutValHigh = DB_78X60_AMC_GPP_OUT_VAL_HIGH,
+ .gppPolarityValLow = DB_78X60_AMC_GPP_POL_LOW,
+ .gppPolarityValMid = DB_78X60_AMC_GPP_POL_MID,
+ .gppPolarityValHigh = DB_78X60_AMC_GPP_POL_HIGH,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = DB_78X60_AMC_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_78X60_AMC_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = DB_78X60_AMC_BOARD_NAND_CONTROL,
+ .configAutoDetect = MV_TRUE, /* Enable modules auto-detection. */
+ .modelName = "AMC Development Board"
+};
+
+
/*********************************************************************************/
MV_BOARD_INFO *marvellBC2BoardInfoTbl[] = {
@@ -902,6 +1614,12 @@
&bc2_rd_mtlInfo
};
+MV_BOARD_INFO *marvellBOBKBoardInfoTbl[] = {
+ &db_dx_bobkCetusInfo,
+ &db_dx_bobkCaelumInfo,
+ &rd_dx_bobkLewisInfo
+};
+
MV_BOARD_INFO *marvellAC3BoardInfoTbl[] = {
&db_dx_ac3Info,
&rd_mtl_4xg_ac3Info,
@@ -909,3 +1627,8 @@
&db_misl_24G_4xg_ac3Info,
&rd_mtl_24G_ac3Info
};
+
+/* only for Linux usage (AXP family is shared with MSYS in LSP) */
+MV_BOARD_INFO *marvellAXPboardInfoTbl[] = {
+ &db78X60amcInfo
+};
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
index 3434624..fba63de 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
@@ -80,9 +80,9 @@
/* Bobcat2 Marvell boards */
#define BC2_MARVELL_BOARD_ID_BASE 0x10
-#define DB_DX_BC2_ID (BC2_MARVELL_BOARD_ID_BASE + 0)
-#define RD_DX_BC2_ID (BC2_MARVELL_BOARD_ID_BASE + 1)
-#define RD_MTL_BC2 (BC2_MARVELL_BOARD_ID_BASE + 2)
+#define DB_DX_BC2_ID (BC2_MARVELL_BOARD_ID_BASE + 0)
+#define RD_DX_BC2_ID (BC2_MARVELL_BOARD_ID_BASE + 1)
+#define RD_MTL_BC2 (BC2_MARVELL_BOARD_ID_BASE + 2)
#define BC2_MARVELL_MAX_BOARD_ID (BC2_MARVELL_BOARD_ID_BASE + 3)
#define BC2_MARVELL_BOARD_NUM (BC2_MARVELL_MAX_BOARD_ID - BC2_MARVELL_BOARD_ID_BASE)
@@ -96,17 +96,52 @@
/* AlleyCat3 Marvell boards */
#define AC3_MARVELL_BOARD_ID_BASE 0x30
-#define DB_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 0)
-#define RD_MTL_4XG_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 1)
+#define DB_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 0)
+#define RD_MTL_4XG_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 1)
#define RD_MTL_2XXG_2XG_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 2)
#define DB_MISL_24G4G_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 3)
-#define RD_MTL_24G_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 4)
+#define RD_MTL_24G_AC3_ID (AC3_MARVELL_BOARD_ID_BASE + 4)
#define AC3_MARVELL_MAX_BOARD_ID (AC3_MARVELL_BOARD_ID_BASE + 5)
#define AC3_MARVELL_BOARD_NUM (AC3_MARVELL_MAX_BOARD_ID - AC3_MARVELL_BOARD_ID_BASE)
-#define INVALID_BOARD_ID 0xFFFF
+/* BobK Customer Boards */
+#define BOBK_CUSTOMER_BOARD_ID_BASE 0x40
+#define BOBK_CETUS_CUSTOMER_BOARD_ID0 (BOBK_CUSTOMER_BOARD_ID_BASE + 0)
+#define BOBK_CAELUM_CUSTOMER_BOARD_ID1 (BOBK_CUSTOMER_BOARD_ID_BASE + 1)
+#define BOBK_CUSTOMER_MAX_BOARD_ID (BOBK_CUSTOMER_BOARD_ID_BASE + 2)
+#define BOBK_CUSTOMER_BOARD_NUM (BOBK_CUSTOMER_MAX_BOARD_ID - BOBK_CUSTOMER_BOARD_ID_BASE)
+/* BobK Marvell Boards */
+#define BOBK_MARVELL_BOARD_ID_BASE 0x50
+#define BOBK_CETUS_DB_ID (BOBK_MARVELL_BOARD_ID_BASE + 0)
+#define BOBK_CAELUM_DB_ID (BOBK_MARVELL_BOARD_ID_BASE + 1)
+#define BOBK_LEWIS_RD_ID (BOBK_MARVELL_BOARD_ID_BASE + 2)
+#define BOBK_MARVELL_MAX_BOARD_ID (BOBK_MARVELL_BOARD_ID_BASE + 3)
+#define BOBK_MARVELL_BOARD_NUM (BOBK_MARVELL_MAX_BOARD_ID - BOBK_MARVELL_BOARD_ID_BASE)
+
+/* AXP-AMC board: for Linux 2.6/3.4 usage only (AXP family is shared with MSYS in LSP) */
+#define DB_78X60_AMC_ID 0x6
+
+#define INVALID_BOARD_ID 0xFFFF
#define BOARD_ID_INDEX_MASK 0x10 /* Mask used to return board index via board Id */
+#define RD_MTL_BC2_PCB_ID 0x70
+
+#if defined CONFIG_ALLEYCAT3
+ #define MARVELL_BOARD_ID_BASE AC3_MARVELL_BOARD_ID_BASE
+ #define MV_MAX_MARVELL_BOARD_ID AC3_MARVELL_MAX_BOARD_ID
+ #define MV_MARVELL_BOARD_NUM AC3_MARVELL_BOARD_NUM
+ #define MV_DEFAULT_BOARD_ID DB_AC3_ID
+#elif defined CONFIG_BOBCAT2
+ #define MARVELL_BOARD_ID_BASE BC2_MARVELL_BOARD_ID_BASE
+ #define MV_MAX_MARVELL_BOARD_ID BC2_MARVELL_MAX_BOARD_ID
+ #define MV_MARVELL_BOARD_NUM BC2_MARVELL_BOARD_NUM
+ #define MV_DEFAULT_BOARD_ID DB_DX_BC2_ID
+#else
+ #define MARVELL_BOARD_ID_BASE BOBK_MARVELL_BOARD_ID_BASE
+ #define MV_MAX_MARVELL_BOARD_ID BOBK_MARVELL_MAX_BOARD_ID
+ #define MV_MARVELL_BOARD_NUM BOBK_MARVELL_BOARD_NUM
+ #define MV_DEFAULT_BOARD_ID BOBK_CETUS_DB_ID
+#endif
/********************************************
* Bobcat2 Boards
@@ -274,6 +309,238 @@
#define RD_MTL_BC2_GPP_POL_MID 0x0
/********************************************
+* Bobk Boards
+*********************************************/
+/*******************************************************************************
+* BobK Cetus Customer board - Based on BOBK-CETUS-DB-98DX4235-12XG
+*******************************************************************************/
+
+#define BOBK_CETUS_CUSTOMER_0_MPP0_7 0x22242222
+#define BOBK_CETUS_CUSTOMER_0_MPP8_15 0x11122222
+#define BOBK_CETUS_CUSTOMER_0_MPP16_23 0x44444044
+#define BOBK_CETUS_CUSTOMER_0_MPP24_31 0x14444444
+#define BOBK_CETUS_CUSTOMER_0_MPP32_39 0x00000001
+
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_MID (~(0))
+
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_MID 0x0
+
+#define BOBK_CETUS_CUSTOMER_0_GPP_POL_LOW 0x0
+#define BOBK_CETUS_CUSTOMER_0_GPP_POL_MID 0x0
+
+/*******************************************************************************
+* BobK Caelum Customer board - Based on BOBK-CAELUM-DB-98DX4203-48G12XG
+*******************************************************************************/
+
+#define BOBK_CAELUM_CUSTOMER_1_MPP0_7 0x22242222
+#define BOBK_CAELUM_CUSTOMER_1_MPP8_15 0x11122222
+#define BOBK_CAELUM_CUSTOMER_1_MPP16_23 0x44444044
+#define BOBK_CAELUM_CUSTOMER_1_MPP24_31 0x14444444
+#define BOBK_CAELUM_CUSTOMER_1_MPP32_39 0x00000001
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_MID (~(0))
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_MID 0x0
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_POL_LOW 0x0
+#define BOBK_CAELUM_CUSTOMER_1_GPP_POL_MID 0x0
+
+
+/************************************/
+/* BOBK-CETUS-DB-98DX4235-12XG */
+/************************************/
+#define DB_DX_BOBK_CETUS_MPP0_7 0x22242222
+#define DB_DX_BOBK_CETUS_MPP8_15 0x11122222
+#define DB_DX_BOBK_CETUS_MPP16_23 0x44444044
+#define DB_DX_BOBK_CETUS_MPP24_31 0x14444444
+#define DB_DX_BOBK_CETUS_MPP32_39 0x00000001
+
+#define DB_DX_BOBK_CETUS_NOR_MPP0_7 0x44444444
+#define DB_DX_BOBK_CETUS_NOR_MPP8_15 0x11122244
+
+/* GPPs
+MPP# NAME IN/OUT
+----------------------------------------------
+0 SPI_MOSI (out)
+1 SPI_MISO (in)
+2 SPI_SCK (out)
+3 SPI_CS0n (out)
+4 DEV_CSn[0] (out) NF CS (Boot)
+5 SD_CMD (in/out)
+6 SD_CLK (out)
+7 SD_D[0] (in/out)
+8 SD_D[1] (in/out)
+9 SD_D[2] (in/out)
+10 SD_D[3] (in/out)
+11 UART1_RXD (in)
+12 UART1_TXD (out)
+13 INTERRUPT_OUTn (out)
+14 I2C_SCL (in/out)
+15 I2C_SDA (in/out)
+
+16 DEV_Oen_NF_Ren (out)
+17 DEV_CLK_OUT (out) Test point
+18 GPIO[18] (in/out) INT_in / SD_WP / VC2_GPP
+19 NF_RBn (in)
+20 DEV_WEn[0] (out)
+21 DEV_AD[0] (in/out)
+22 DEV_AD[1] (in/out)
+23 DEV_AD[2] (in/out)
+24 DEV_AD[3] (in/out)
+25 DEV_AD[4] (in/out)
+26 DEV_AD[5] (in/out)
+27 DEV_AD[6] (in/out)
+28 DEV_AD[7] (in/out)
+29 NF_CLE_DEV_A[0] (out)
+30 NF_ALE_DEV_A[1] (out)
+31 SLV_SMI_MDC (in)
+32 SLV_SMI_MDIO (in/out)
+
+*/
+#define DB_DX_BOBK_CETUS_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define DB_DX_BOBK_CETUS_GPP_OUT_ENA_MID (~(0))
+
+#define DB_DX_BOBK_CETUS_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define DB_DX_BOBK_CETUS_GPP_OUT_VAL_MID 0x0
+
+#define DB_DX_BOBK_CETUS_GPP_POL_LOW 0x0
+#define DB_DX_BOBK_CETUS_GPP_POL_MID 0x0
+
+/*************************************/
+/* BOBK-CAELUM-DB-98DX4203-48G12XG */
+/*************************************/
+#define DB_DX_BOBK_CAELUM_MPP0_7 0x22242222
+#define DB_DX_BOBK_CAELUM_MPP8_15 0x11122222
+#define DB_DX_BOBK_CAELUM_MPP16_23 0x44444044
+#define DB_DX_BOBK_CAELUM_MPP24_31 0x14444444
+#define DB_DX_BOBK_CAELUM_MPP32_39 0x00000001
+
+#define DB_DX_BOBK_CAELUM_NOR_MPP0_7 0x44444444
+#define DB_DX_BOBK_CAELUM_NOR_MPP8_15 0x11122244
+
+/* GPPs
+MPP# NAME IN/OUT
+----------------------------------------------
+0 SPI_MOSI (out)
+1 SPI_MISO (in)
+2 SPI_SCK (out)
+3 SPI_CS0n (out)
+4 DEV_CSn[0] (out) NF CS (Boot)
+5 SD_CMD (in/out)
+6 SD_CLK (out)
+7 SD_D[0] (in/out)
+8 SD_D[1] (in/out)
+9 SD_D[2] (in/out)
+10 SD_D[3] (in/out)
+11 UART1_RXD (in)
+12 UART1_TXD (out)
+13 INTERRUPT_OUTn (out)
+14 I2C_SCL (in/out)
+15 I2C_SDA (in/out)
+
+16 DEV_Oen_NF_Ren (out)
+17 DEV_CLK_OUT (out) Test point
+18 GPIO[18] (in/out) INT_in / SD_WP / VC2_GPP
+19 NF_RBn (in)
+20 DEV_WEn[0] (out)
+21 DEV_AD[0] (in/out)
+22 DEV_AD[1] (in/out)
+23 DEV_AD[2] (in/out)
+24 DEV_AD[3] (in/out)
+25 DEV_AD[4] (in/out)
+26 DEV_AD[5] (in/out)
+27 DEV_AD[6] (in/out)
+28 DEV_AD[7] (in/out)
+29 NF_CLE_DEV_A[0] (out)
+30 NF_ALE_DEV_A[1] (out)
+31 SLV_SMI_MDC (in)
+32 SLV_SMI_MDIO (in/out)
+
+*/
+#define DB_DX_BOBK_CAELUM_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define DB_DX_BOBK_CAELUM_GPP_OUT_ENA_MID (~(0))
+
+#define DB_DX_BOBK_CAELUM_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define DB_DX_BOBK_CAELUM_GPP_OUT_VAL_MID 0x0
+
+#define DB_DX_BOBK_CAELUM_GPP_POL_LOW 0x0
+#define DB_DX_BOBK_CAELUM_GPP_POL_MID 0x0
+
+
+/************************************/
+/* BOBK-LEWIS-RD-LWS-12XG-A */
+/************************************/
+#define RD_DX_BOBK_LEWIS_MPP0_7 0x00042222 /* 0-3:SPI, 4:NF_CEn, 5:SFP_Data, 6:DIAG LED, 7:TWSI_SEL1 */
+#define RD_DX_BOBK_LEWIS_MPP8_15 0x11000000 /* 8:TWSI_SEL2,9:SFP_TX,10,TMP_INT,11:INIT_Done,12:MPP12,
+ 13:USB_OC,14-15:I2C_[SCLK,SDA] */
+#define RD_DX_BOBK_LEWIS_MPP16_23 0x44444004 /* 16:NF_REn, 17:TWSI_SEL0, 18:NA, 19-23:NF_[Busy,WEn,IO[0,1,2]] */
+#define RD_DX_BOBK_LEWIS_MPP24_31 0x14444444 /* 24-30: NF_IO[3,4,5,6,7],NF_CLE,NF_ALE, 31: SMI_MST_MDC(SMI) */
+#define RD_DX_BOBK_LEWIS_MPP32_39 0x00000001 /* 32: SMI_MST_MDIO(SMI) */
+
+
+/* GPPs
+MPP# NAME IN/OUT
+----------------------------------------------
+0 SPI_SI (in/out)
+1 SPI_SO (in/out)
+2 SPI_SCK (in/out)
+3 SPI_CS0n (in/out)
+4 NF_CEn (in/out) NAND Flash
+5 SFP_Data (in)
+6 DIAG LED (out)
+7 TWSI_SEL1 (out)
+8 TWSI_SEL2 (out)
+9 SFP_TX_DIS (out)
+10 TMP_INT (in)
+11 INIT_Done (in)
+12 MPP12 (N/A)
+13 USB_OC (in)
+14 I2C_SCLK (out)
+15 I2C_SDA (in/out)
+
+16 NF_REn (in/out)NAND Flash
+17 TWSI_SEL0 (out)
+18 NA (NA)
+19 NF_Busy (in/out)NAND Flash
+20 NF_WEn (in/out)NAND Flash
+21 NF_IO[0] (in/out)NAND Flash
+22 NF_IO[1] (in/out)NAND Flash
+23 NF_IO[2] (in/out)NAND Flash
+24 NF_IO[3] (in/out)NAND Flash
+25 NF_IO[4] (in/out)NAND Flash
+26 NF_IO[5] (in/out)NAND Flash
+27 NF_IO[6] (in/out)NAND Flash
+28 NF_IO[7] (in/out)NAND Flash
+29 NF_CLE (in/out)NAND Flash
+30 NF_ALE (in/out)NAND Flash
+31 SMI_MST_MDC (out)
+32 SMI_MST_MDIO (in/out)
+
+*/
+#define RD_DX_BOBK_LEWIS_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT7 | BIT8\
+ | BIT9 | BIT14 | BIT17 | BIT31))
+#define RD_DX_BOBK_LEWIS_GPP_OUT_ENA_MID (~(0))
+
+#define RD_DX_BOBK_LEWIS_GPP_OUT_VAL_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT9\
+ | BIT14 | BIT17 | BIT31))
+#define RD_DX_BOBK_LEWIS_GPP_OUT_VAL_MID 0x0
+
+#define RD_DX_BOBK_LEWIS_GPP_POL_LOW 0x0
+#define RD_DX_BOBK_LEWIS_GPP_POL_MID 0x0
+
+/********************************************
* AlleyCat3 Boards
*********************************************/
/*******************************************************************************
@@ -424,8 +691,8 @@
/*********************************/
/* RD_DX_2XXG_2XG_AC3 (MTL2) */
/*********************************/
-#define RD_MTL_2XXG_2XG_AC3_MPP0_7 RD_MTL_4XG_AC3_MPP0_7
-#define RD_MTL_2XXG_2XG_AC3_MPP8_15 RD_MTL_4XG_AC3_MPP8_15
+#define RD_MTL_2XXG_2XG_AC3_MPP0_7 RD_MTL_4XG_AC3_MPP0_7
+#define RD_MTL_2XXG_2XG_AC3_MPP8_15 RD_MTL_4XG_AC3_MPP8_15
#define RD_MTL_2XXG_2XG_AC3_MPP16_23 RD_MTL_4XG_AC3_MPP16_23
#define RD_MTL_2XXG_2XG_AC3_MPP24_31 RD_MTL_4XG_AC3_MPP24_31
#define RD_MTL_2XXG_2XG_AC3_MPP32_39 RD_MTL_4XG_AC3_MPP32_39
@@ -434,8 +701,8 @@
#define RD_MTL_2XXG_2XG_AC3_GPP_OUT_ENA_MID RD_MTL_4XG_AC3_GPP_OUT_ENA_MID
#define RD_MTL_2XXG_2XG_AC3_GPP_OUT_VAL_LOW RD_MTL_4XG_AC3_GPP_OUT_VAL_LOW
#define RD_MTL_2XXG_2XG_AC3_GPP_OUT_VAL_MID RD_MTL_4XG_AC3_GPP_OUT_VAL_MID
-#define RD_MTL_2XXG_2XG_AC3_GPP_POL_LOW RD_MTL_4XG_AC3_GPP_POL_LOW
-#define RD_MTL_2XXG_2XG_AC3_GPP_POL_MID RD_MTL_4XG_AC3_GPP_POL_MID
+#define RD_MTL_2XXG_2XG_AC3_GPP_POL_LOW RD_MTL_4XG_AC3_GPP_POL_LOW
+#define RD_MTL_2XXG_2XG_AC3_GPP_POL_MID RD_MTL_4XG_AC3_GPP_POL_MID
/**************************************/
/* DB-XC3-24G4G_2XG_AC3 (RD_MISL) */
@@ -469,5 +736,56 @@
#define RD_MTL_24G_AC3_GPP_POL_LOW RD_MTL_4XG_AC3_GPP_POL_LOW
#define RD_MTL_24G_AC3_GPP_POL_MID RD_MTL_4XG_AC3_GPP_POL_MID
+/**********************************************************************************/
+/* ArmadaXP Boards : only for Linux usage (AXP family is shared with MSYS in LSP) */
+/**********************************************************************************/
+/********************/
+/* DB-78460-AMC */
+/********************/
+
+#define DB_78X60_AMC_MPP0_7 0x11111111
+#define DB_78X60_AMC_MPP8_15 0x00001111
+#define DB_78X60_AMC_MPP16_23 0x00000000
+#define DB_78X60_AMC_MPP24_31 0x00000000
+#define DB_78X60_AMC_MPP32_39 0x11110000
+#define DB_78X60_AMC_MPP40_47 0x00004000
+#define DB_78X60_AMC_MPP48_55 0x00001113
+#define DB_78X60_AMC_MPP56_63 0x11111110
+#define DB_78X60_AMC_MPP64_67 0x00000111
+
+/* GPPs
+MPP# NAME IN/OUT
+----------------------------------------------
+16 MB_INT# IN
+17 Phy1_INT# IN
+18 Phy2_INT# IN
+19 Brd_Led_0 IN (for next board)
+21 Brd_Led_1 OUT
+23 Brd_Led_2 OUT
+29 Brd_Led_3 OUT
+30 Brd_Led_4 OUT
+34 Dbg_JP0 IN
+35 Dbg_JP1 IN
+40 Dbg_JP2 IN
+41 Dbg_JP3 IN
+42 Dbg_JP4 IN
+53 7 Segment 0 OUT
+54 7 Segment 1 OUT
+55 7 Segment 2 OUT
+56 7 Segment 3 OUT
+*/
+
+#define DB_78X60_AMC_GPP_OUT_ENA_LOW (~(BIT19 | BIT21 | BIT22 | BIT23 | BIT29 | BIT30))
+#define DB_78X60_AMC_GPP_OUT_ENA_MID (~(BIT21 | BIT22 | BIT23 | BIT24))
+#define DB_78X60_AMC_GPP_OUT_ENA_HIGH (~(0x0))
+
+#define DB_78X60_AMC_GPP_OUT_VAL_LOW 0x0
+#define DB_78X60_AMC_GPP_OUT_VAL_MID 0x0
+#define DB_78X60_AMC_GPP_OUT_VAL_HIGH 0x0
+
+#define DB_78X60_AMC_GPP_POL_LOW 0x0
+#define DB_78X60_AMC_GPP_POL_MID 0x0
+#define DB_78X60_AMC_GPP_POL_HIGH 0x0
+
#endif /* __INCmvBoardEnvSpech */
diff --git a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
index 63cf76a..a7a143f 100644
--- a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
+++ b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
@@ -96,17 +96,42 @@
{
MV_U32 idx;
MV_U32 freqMhz;
+ MV_U32 cpuClk[] = MV_CPU_CLK_TBL_AXP;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U32 sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
+ MV_U32 sar2;
+
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ idx = MSAR_CPU_CLK_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),
+ MV_REG_READ(MPP_SAMPLE_AT_RESET(1)));
+ return cpuClk[idx] * 1000000;
+ }
+
+ sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
idx = MSAR_CPU_DDR_CLK(0, sar2);
if (family == MV_BOBCAT2_DEV_ID)
freqMhz = bc2ClockRatioTbl[idx].cpuFreq * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].cpuFreq * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvCtrlModelGet()) {
+ case MV_BOBK_CETUS_98DX4235_DEV_ID:
+ case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+ /* LEWIS RD board's CPU freq setting is the same as CETUS board */
+ freqMhz = bobkCetusClockRatioTbl[idx].cpuFreq * 1000000;
+ break;
+ case MV_BOBK_CAELUM_98DX4203_DEV_ID:
+ freqMhz = bobkCaelumClockRatioTbl[idx].cpuFreq * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown DeviceID %d, CPU freq get failed\n", mvCtrlModelGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
return freqMhz;
@@ -134,6 +159,8 @@
MV_U32 freqMhz;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
MV_U32 sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
@@ -142,7 +169,21 @@
freqMhz = bc2ClockRatioTbl[idx].ddrFreq * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].ddrFreq * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvCtrlModelGet()) {
+ case MV_BOBK_CETUS_98DX4235_DEV_ID:
+ case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+ /* LEWIS RD board's CPU freq setting is the same as CETUS board */
+ freqMhz = bobkCetusClockRatioTbl[idx].ddrFreq * 1000000;
+ break;
+ case MV_BOBK_CAELUM_98DX4203_DEV_ID:
+ freqMhz = bobkCaelumClockRatioTbl[idx].ddrFreq * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown DeviceID %d, DDR freq get failed\n", mvCtrlModelGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
return freqMhz;
@@ -170,20 +211,37 @@
MV_U32 freqMhz;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U32 sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
+ MV_U32 sar2;
+
+ if (family == MV_78460_DEV_ID)
+ return AXP_PLL_IN_CLK;
+
+ sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
idx = MSAR_CPU_DDR_CLK(0, sar2);
- switch (family) {
- case MV_BOBCAT2_DEV_ID:
+ if (family == MV_BOBCAT2_DEV_ID)
freqMhz = bc2ClockRatioTbl[idx].pllClk * 1000000;
- break;
- case MV_ALLEYCAT3_DEV_ID:
+ else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].pllClk * 1000000;
- break;
- default:
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvCtrlModelGet()) {
+ case MV_BOBK_CETUS_98DX4235_DEV_ID:
+ case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+ /* LEWIS RD board's CPU freq setting is the same as CETUS board */
+ freqMhz = bobkCetusClockRatioTbl[idx].pllClk * 1000000;
+ break;
+ case MV_BOBK_CAELUM_98DX4203_DEV_ID:
+ freqMhz = bobkCaelumClockRatioTbl[idx].pllClk * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown DeviceID %d, PLL freq get failed\n", mvCtrlModelGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
- }
return freqMhz;
}
@@ -200,6 +258,10 @@
*******************************************************************************/
MV_U32 mvCpuL2ClkGet(MV_VOID)
{
+ MV_U32 idx;
+ MV_U32 freqMhz, l2FreqMhz;
+ MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL_AXP;
+
/* MV_U32 idx;
MV_U32 freqMhz;
MV_CPUDDR_MODE clockRatioTbl[8] = MV_CPU_DDR_CLK_TBL;
@@ -207,7 +269,24 @@
idx = MSAR_CPU_DDR_CLK(0, sar2);
freqMhz = clockRatioTbl[idx].cpuFreq * 1000000; */
- return 200000000;
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID)
+ return 200000000;
+
+ idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),
+ MV_REG_READ(MPP_SAMPLE_AT_RESET(1)));
+
+ if (clockRatioTbl[idx].vco2cpu != 0) {
+ freqMhz = mvCpuPclkGet() / 1000000; /* CPU freq */
+ freqMhz *= clockRatioTbl[idx].vco2cpu; /* VCO freq */
+ l2FreqMhz = freqMhz / clockRatioTbl[idx].vco2l2c;
+ /* round up to integer MHz */
+ if (((freqMhz % clockRatioTbl[idx].vco2l2c) * 10 / clockRatioTbl[idx].vco2l2c) >= 5)
+ l2FreqMhz++;
+
+ return l2FreqMhz * 1000000;
+ } else {
+ return (MV_U32)-1;
+ }
}
/*******************************************************************************
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
index a34dba4..711531f 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvAddrDec.c
@@ -91,7 +91,8 @@
#endif
/* Default Attributes array */
-MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY;
+MV_TARGET_ATTRIB mvTargetDefaultsArrayMsys[] = TARGETS_DEF_ARRAY;
+MV_TARGET_ATTRIB mvTargetDefaultsArrayAxp[] = TARGETS_DEF_ARRAY_AXP;
/*******************************************************************************
* mvCtrlAttribGet -
@@ -107,6 +108,13 @@
*******************************************************************************/
MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib)
{
+ MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+ else
+ mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib;
targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId;
@@ -115,6 +123,13 @@
/*******************************************************************************/
MV_STATUS mvCtrlAttribSet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib)
{
+ MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+ else
+ mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib = targetAttrib->attrib;
mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId= targetAttrib->targetId;
@@ -137,6 +152,13 @@
{
MV_TARGET target;
MV_TARGET x;
+ MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+ else
+ mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
for (target = SDRAM_CS0; target < MAX_TARGETS; target++) {
x = MV_CHANGE_BOOT_CS(target);
if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) &&
@@ -165,6 +187,13 @@
{
MV_TARGET target;
MV_TARGET x;
+ MV_TARGET_ATTRIB *mvTargetDefaultsArray;
+
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvTargetDefaultsArray = mvTargetDefaultsArrayAxp;
+ else
+ mvTargetDefaultsArray = mvTargetDefaultsArrayMsys;
+
for (target = SDRAM_CS0; target < MAX_TARGETS; target++) {
x = MV_CHANGE_BOOT_CS(target);
if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) &&
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index be1616d..17cec27 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -89,6 +89,8 @@
#include "ddr2_3/mvDramIfRegs.h"
#include "twsi/mvTwsiSpec.h"
+#include "device/mvDevice.h"
+#include "mvDeviceId.h"
/* defines */
#undef MV_DEBUG
@@ -101,22 +103,62 @@
/* MSYS family linear id */
#define MV_MSYS_BC2_INDEX 0
#define MV_MSYS_AC3_INDEX 1
-#define MV_MSYS_INDEX_MAX 2
+#define MV_78460_INDEX 2
+#define MV_MSYS_BOBK_INDEX 3
+#define MV_MSYS_AXP_INDEX_MAX 4
-MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MV_MSYS_INDEX_MAX] = {
-/* BC2 AC3 */
-/* DRAM_UNIT_ID */ { 1, 1, },
-/* PEX_UNIT_ID */ { 1, 1, },
-/* ETH_GIG_UNIT_ID */ { 2, 2, },
-/* XOR_UNIT_ID */ { 1, 1, },
-/* UART_UNIT_ID */ { 2, 2, },
-/* SPI_UNIT_ID */ { 2, 1, },
-/* SDIO_UNIT_ID */ { 1, 1, },
-/* I2C_UNIT_ID */ { 2, 2, },
-/* USB_UNIT_ID */ { 0, 1, },
-/* USB3_UNIT_ID */ { 0, 0, },
+MV_UNIT_ID mvCtrlSocUnitNums[MAX_UNITS_ID][MV_MSYS_AXP_INDEX_MAX] = {
+/* BC2 AC3 78460 BOBK*/
+/* DRAM_UNIT_ID */ { 1, 1, 1, 1,},
+/* PEX_UNIT_ID */ { 1, 1, 4, 1,},
+/* ETH_GIG_UNIT_ID */ { 2, 2, 4, 2,},
+/* XOR_UNIT_ID */ { 1, 1, 4, 1,},
+/* UART_UNIT_ID */ { 2, 2, 4, 2,},
+/* SPI_UNIT_ID */ { 1, 1, 2, 1,},
+/* SDIO_UNIT_ID */ { 1, 1, 1, 1,},
+/* I2C_UNIT_ID */ { 2, 2, 2, 2,},
+/* USB_UNIT_ID */ { 0, 1, 3, 1,},
+/* USB3_UNIT_ID */ { 0, 0, 0, 0,},
+/* NAND_UNIT_ID */ { 1, 1, 1, 1,},
+/* DEVBUS_UNIT_ID */ { 0, 0, 0, 0,},
+/* IDMA_UNIT_ID */ { 0, 0, 4, 0,},
+/* SATA_UNIT_ID */ { 0, 0, 2, 0,},
+/* TDM_UNIT_ID */ { 0, 0, 1, 0,},
+/* CESA_UNIT_ID */ { 0, 0, 2, 0,},
+/* AUDIO_UNIT_ID */ { 0, 0, 0, 0,},
+/* TS_UNIT_ID */ { 0, 0, 0, 0,},
+/* XPON_UNIT_ID */ { 0, 0, 0, 0,},
+/* BM_UNIT_ID */ { 0, 0, 1, 0,},
+/* PNC_UNIT_ID */ { 0, 0, 1, 0,},
};
+MV_U32 mvDev2CpuMapTable[20][2] = {
+/* Dev ID cores# */
+ {MV_BOBCAT2_DEV_ID, 2},
+ {MV_BOBK_CETUS_98DX4235_DEV_ID, 2},
+ {MV_BOBK_CAELUM_98DX4203_DEV_ID, 2},
+ {MV_BOBK_LEWIS_98DX8212_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX3336_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX3335_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX3334_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX3333_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX1233_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DX1235_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DX3236_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DX3235_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DX3234_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DX3233_DEV_ID, 1},
+ {MV_ALLEYCAT3_98DXH333_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX1333_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX1335_DEV_ID, 2},
+ {MV_ALLEYCAT3_98DX1336_DEV_ID, 2},
+ {MV_78460_DEV_ID, 4},
+ {MV_MAX_DEV_ID, 0},
+};
+
+
+
+
static MV_U32 mvCtrlDevIdIndexGet(MV_U32 devId)
{
MV_U32 index;
@@ -128,12 +170,36 @@
case MV_ALLEYCAT3_DEV_ID:
index = MV_MSYS_AC3_INDEX;
break;
+ case MV_78460_DEV_ID:
+ index = MV_78460_INDEX;
+ break;
+ case MV_BOBK_DEV_ID:
+ index = MV_MSYS_BOBK_INDEX;
+ break;
default:
index = MV_MSYS_AC3_INDEX;
}
return index;
}
+/******************************************************************************
+* mvCtrlIsUsbSerDesConnected
+*
+* DESCRIPTION: check if SerDes lane is connected to USB3 host.
+*
+*
+* INPUT: None
+*
+* OUTPUT: None
+*
+* RETURN:return true if SerDes lane is connected to USB3 host, false otherwise.
+*
+*
+*******************************************************************************/
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort)
+{
+ return MV_FALSE;/*return false because in msys there is no usb3*/
+}
MV_U32 mvCtrlSocUnitInfoNumGet(MV_UNIT_ID unit)
{
@@ -147,11 +213,34 @@
devIdIndex = mvCtrlDevIdIndexGet(mvCtrlModelGet());
return mvCtrlSocUnitNums[unit][devIdIndex];
}
-
-MV_U32 mvCtrlGetCpuNum(MV_VOID)
+/******************************************************************************
+* mvCtrlGetCpuNum
+*
+* DESCRIPTION: Get the number of CPU cores
+*
+*
+* INPUT: None
+*
+* OUTPUT: None
+*
+* RETURN:cpu cores number or 0 if the deviceID not found in device IDs table
+*
+*
+*******************************************************************************/
+MV_U32 mvCtrlGetCpuNum(MV_VOID)
{
+ MV_U32 table_index = 0;
+ MV_U32 deviceId = mvCtrlModelGet();
+
+ while (mvDev2CpuMapTable[table_index][0] != MV_MAX_DEV_ID) {
+ if (deviceId == mvDev2CpuMapTable[table_index][0])
+ return mvDev2CpuMapTable[table_index][1];
+ table_index++;
+ }
+ mvOsPrintf("%s: Error: DevID (%#X) is not found in CPU cores count per device table!\n", __func__, deviceId);
return 0;
}
+
MV_BOOL mvCtrlIsValidSatR(MV_VOID)
{
return MV_TRUE;
@@ -248,7 +337,9 @@
MV_U32 mppGroup;
MV_U32 mppVal;
MV_U32 i, gppMask;
-
+ MV_U32 maxGroup = mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID ?
+ MV_MPP_MAX_GROUP_AXP : MV_MPP_MAX_GROUP;
+ MV_STATUS status;
/* Disable MBus Error Propagation */
MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8);
@@ -260,23 +351,23 @@
mvBoardMppModulesScan();
/* Read MPP config values from board level and write MPP options to HW */
- for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) {
+ for (mppGroup = 0; mppGroup < maxGroup; mppGroup++) {
mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */
MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
}
/* disable all GPIO interrupts */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++) {
+ for (i = 0; i < maxGroup; i++) {
MV_REG_WRITE(GPP_INT_MASK_REG(i), 0x0);
MV_REG_WRITE(GPP_INT_LVL_REG(i), 0x0);
}
/* clear all int */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++)
+ for (i = 0; i < maxGroup; i++)
MV_REG_WRITE(GPP_INT_CAUSE_REG(i), 0x0);
/* Set gpp interrupts as needed */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++) {
+ for (i = 0; i < maxGroup; i++) {
gppMask = mvBoardGpioIntMaskGet(i);
mvGppTypeSet(i, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(i, gppMask , (MV_GPP_IN_INVERT & gppMask));
@@ -286,15 +377,22 @@
mvBoardOtherModulesScan();
/* Update interfaces configuration based on above scan */
- if (MV_OK != mvCtrlSerdesPhyConfig())
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ status = mvCtrlSerdesPhyConfigAxp();
+ else
+ status = mvCtrlSerdesPhyConfig();
+
+ if (status != MV_OK)
mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n");
- mvCtrlDevBusInit();
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID) {
+ mvCtrlDevBusInit();
#ifdef ERRATA_GL_5956802
/* SW WA for ERRATA 5956802 - disable the external i2c debugger access */
MV_REG_BIT_RESET(TWSI_CONFIG_DEBUG_REG, TWSI_DEBUG_SLAVE_PORT0_EN);
#endif
+ }
mvOsDelay(100);
@@ -318,9 +416,14 @@
*******************************************************************************/
MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup)
{
- MV_U32 ret;
+ MV_U32 ret, maxGroup;
- if (mppGroup >= MV_MPP_MAX_GROUP)
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ maxGroup = MV_MPP_MAX_GROUP_AXP;
+ else
+ maxGroup = MV_MPP_MAX_GROUP;
+
+ if (mppGroup >= maxGroup)
mppGroup = 0;
ret = MPP_CONTROL_REG(mppGroup);
@@ -348,6 +451,8 @@
*******************************************************************************/
MV_U32 mvCtrlPexMaxIfGet(MV_VOID)
{
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return MV_PEX_MAX_IF;
return mvCtrlSocUnitInfoNumGet(PEX_UNIT_ID);
}
@@ -437,6 +542,8 @@
*******************************************************************************/
MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID)
{
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return mvCtrlEthMaxPortGet();
return 2;
}
@@ -558,6 +665,64 @@
#endif
/*******************************************************************************
+* mvCtrlModelGetAxp - Get Marvell controller device model (Id) for AXP devices
+*
+* DESCRIPTION:
+* This function returns 16bit describing the device model (ID) as defined
+* in PCI Device and Vendor ID configuration register offset 0x0.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 16bit desscribing Marvell controller ID
+*
+*******************************************************************************/
+MV_U16 mvCtrlModelGetAxp(MV_VOID)
+{
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ MV_U32 pexPower;
+#endif
+ MV_U32 devId;
+ MV_U16 model = 0;
+ MV_U32 reg, reg2;
+ static MV_U16 modelId = 0xffff;
+
+ if (modelId != 0xffff)
+ return modelId;
+
+ /* if PEX0 clocks are disabled - enabled it to read */
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Check pex power state */
+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0);
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
+#endif
+ reg = MV_REG_READ(POWER_MNG_CTRL_REG);
+ if ((reg & AXP_PMC_PEXSTOPCLOCK_MASK(0)) == AXP_PMC_PEXSTOPCLOCK_STOP(0)) {
+ reg2 = ((reg & ~AXP_PMC_PEXSTOPCLOCK_MASK(0)) | AXP_PMC_PEXSTOPCLOCK_EN(0));
+ MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2);
+ }
+
+ devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID));
+
+ /* Reset the original value of the PEX0 clock */
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Return to power off state */
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
+#endif
+
+ model = (MV_U16) ((devId >> 16) & 0xFFFF);
+
+ modelId = model;
+ return model;
+}
+
+/*******************************************************************************
* mvCtrlModelGet - Get Marvell controller device model (Id)
*
* DESCRIPTION:
@@ -578,11 +743,15 @@
{
MV_U32 ctrlId = MV_REG_READ(DEV_ID_REG);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return mvCtrlModelGetAxp();
+
ctrlId = (ctrlId & (DEVICE_ID_MASK)) >> DEVICE_ID_OFFS;
switch (ctrlId & ~DEVICE_FLAVOR_MASK) {
case MV_BOBCAT2_DEV_ID:
case MV_ALLEYCAT3_DEV_ID:
+ case MV_BOBK_DEV_ID:
return ctrlId;
default:
mvOsPrintf("%s: Error: Failed to obtain Controller Device ID\n", __func__);
@@ -609,8 +778,30 @@
*******************************************************************************/
MV_U8 mvCtrlRevGet(MV_VOID)
{
- MV_U32 value = MV_DFX_REG_READ(DEV_REV_ID_REG);
- return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ MV_U32 pexPower;
+#endif
+ MV_U32 value;
+ MV_U8 revNum;
+
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID) {
+ value = MV_DFX_REG_READ(DEV_REV_ID_REG);
+ return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
+ }
+
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Check pex power state */
+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0);
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
+#endif
+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID));
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Return to power off state */
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
+#endif
+ return (revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
}
/*******************************************************************************
@@ -631,7 +822,11 @@
*******************************************************************************/
MV_STATUS mvCtrlNameGet(char *pNameBuff)
{
- mvOsSPrintf(pNameBuff, "%s", SOC_NAME_PREFIX);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvOsSPrintf(pNameBuff, "%s", "");
+ else
+ mvOsSPrintf(pNameBuff, "%s", SOC_NAME_PREFIX);
+
return MV_OK;
}
@@ -701,7 +896,26 @@
mvOsSPrintf(pNameBuff, " Rev %s", revArrayAC3[revId]);
return;
}
+ } else if (ctrlFamily == MV_78460_DEV_ID) {
+ switch (mvCtrlModelRevGet()) {
+ case MV_78460_A0_ID:
+ mvOsSPrintf(pNameBuff, "%s", MV_78460_A0_NAME);
+ return;
+ case MV_78460_B0_ID:
+ mvOsSPrintf(pNameBuff, "%s", MV_78460_B0_NAME);
+ return;
+ default:
+ break;
+ }
+ } else if (ctrlFamily == MV_BOBK_DEV_ID) {
+ char *revArrayBOBK[] = MV_BOBK_ID_ARRAY;
+
+ switch (revId) {
+ case MV_BOBK_A0_ID:
+ mvOsSPrintf(pNameBuff, " Rev %s", revArrayBOBK[revId]);
+ return;
+ }
} else
mvOsPrintf("%s: Error: Wrong controller model %#x\n", __func__, ctrlFamily);
@@ -751,17 +965,22 @@
{
MV_U32 boardId = mvBoardIdGet();
- if ((boardId >= BC2_CUSTOMER_BOARD_ID_BASE) && (boardId < BC2_MARVELL_MAX_BOARD_ID))
+ if (boardId == DB_78X60_AMC_ID)
+ return MV_78460_DEV_ID;
+ else if ((boardId >= BC2_CUSTOMER_BOARD_ID_BASE) && (boardId < BC2_MARVELL_MAX_BOARD_ID))
return MV_BOBCAT2_DEV_ID;
else if ((boardId >= AC3_CUSTOMER_BOARD_ID_BASE) && (boardId < AC3_MARVELL_MAX_BOARD_ID))
return MV_ALLEYCAT3_DEV_ID;
+ else if ((boardId >= BOBK_CUSTOMER_BOARD_ID_BASE) && (boardId < BOBK_MARVELL_MAX_BOARD_ID))
+ return MV_BOBK_DEV_ID;
else {
mvOsPrintf("%s: ERR. Invalid Board ID (%d) ,Using BC2 as default family\n", __func__, boardId);
return MV_BOBCAT2_DEV_ID;
}
}
-static const char *cntrlName[] = TARGETS_NAME_ARRAY;
+static const char * const cntrlNameMsys[] = TARGETS_NAME_ARRAY;
+static const char * const cntrlNameAxp[] = TARGETS_NAME_ARRAY_AXP;
/*******************************************************************************
* mvCtrlTargetNameGet - Get Marvell controller target name
@@ -783,7 +1002,10 @@
if (target >= MAX_TARGETS)
return "target unknown";
- return cntrlName[target];
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return cntrlNameAxp[target];
+ else
+ return cntrlNameMsys[target];
}
#if defined(MV_INCLUDE_PEX)
@@ -1161,8 +1383,10 @@
if (mvCtrlDevFamilyIdGet(0) == MV_BOBCAT2_DEV_ID)
satr = MSAR_BC2_BOOT_MODE(satr, 0);
- else
+ else if (mvCtrlDevFamilyIdGet(0) == MV_ALLEYCAT3_DEV_ID)
satr = MSAR_AC3_BOOT_MODE(satr, 0);
+ else
+ satr = MSAR_BOBK_BOOT_MODE(satr, 0);
if (satr == SAR1_BOOT_FROM_NOR)
return MV_TRUE;
@@ -1192,8 +1416,10 @@
if (mvCtrlDevFamilyIdGet(0) == MV_BOBCAT2_DEV_ID)
satr = MSAR_BC2_BOOT_MODE(satr, 0);
- else
+ else if (mvCtrlDevFamilyIdGet(0) == MV_ALLEYCAT3_DEV_ID)
satr = MSAR_AC3_BOOT_MODE(satr, 0);
+ else
+ satr = MSAR_BOBK_BOOT_MODE(satr, 0);
if (satr == SAR1_BOOT_FROM_SPI)
return MV_TRUE;
@@ -1223,8 +1449,10 @@
if (mvCtrlDevFamilyIdGet(0) == MV_BOBCAT2_DEV_ID)
satr = MSAR_BC2_BOOT_MODE(satr, 0);
- else
+ else if (mvCtrlDevFamilyIdGet(0) == MV_ALLEYCAT3_DEV_ID)
satr = MSAR_AC3_BOOT_MODE(satr, 0);
+ else
+ satr = MSAR_BOBK_BOOT_MODE(satr, 0);
if (satr == SAR1_BOOT_FROM_NAND)
return MV_TRUE;
@@ -1266,33 +1494,84 @@
*******************************************************************************/
MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
{
+ MV_U32 mask;
switch (unitId) {
#if defined(MV_INCLUDE_PEX)
case PEX_UNIT_ID:
- if (enable == MV_FALSE)
- MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mask = AXP_PMC_PEXSTOPCLOCK_MASK(index);
else
- MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+ mask = PMC_PEXSTOPCLOCK_MASK;
+
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
break;
#endif
#if defined(MV_INCLUDE_GIG_ETH)
case ETH_GIG_UNIT_ID:
- if (enable == MV_FALSE)
- MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mask = AXP_PMC_GESTOPCLOCK_MASK(index);
else
- MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+ mask = PMC_GESTOPCLOCK_MASK(index);
+
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
break;
#endif
#if defined(MV_INCLUDE_SDIO)
case SDIO_UNIT_ID:
- if (enable == MV_FALSE)
- MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mask = AXP_PMC_SDIOSTOPCLOCK_MASK;
else
- MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+ mask = PMC_SDIOSTOPCLOCK_MASK;
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, mask);
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, mask);
+
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_CESASTOPCLOCK_MASK);
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_CESASTOPCLOCK_MASK);
+
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_USBSTOPCLOCK_MASK(index));
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_USBSTOPCLOCK_MASK(index));
+
+ break;
+#endif
+#if defined(MV_INCLUDE_INTEG_SATA)
+ case SATA_UNIT_ID:
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_SATASTOPCLOCK_MASK(index));
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_SATASTOPCLOCK_MASK(index));
+
+ break;
+#endif
+#if defined(MV_INCLUDE_TDM)
+ case TDM_UNIT_ID:
+ if (enable == MV_FALSE)
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, AXP_PMC_TDMSTOPCLOCK_MASK);
+ else
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, AXP_PMC_TDMSTOPCLOCK_MASK);
break;
#endif
default:
@@ -1315,13 +1594,22 @@
{
#if defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_SDIO)
MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG);
+ MV_U32 mask, stop;
#endif
MV_BOOL state = MV_TRUE;
switch (unitId) {
#if defined(MV_INCLUDE_PEX)
case PEX_UNIT_ID:
- if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP)
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ mask = AXP_PMC_PEXSTOPCLOCK_MASK(index);
+ stop = AXP_PMC_PEXSTOPCLOCK_STOP(index);
+ } else {
+ mask = PMC_PEXSTOPCLOCK_MASK;
+ stop = PMC_PEXSTOPCLOCK_STOP;
+ }
+
+ if ((reg & mask) == stop)
state = MV_FALSE;
else
state = MV_TRUE;
@@ -1329,7 +1617,15 @@
#endif
#if defined(MV_INCLUDE_GIG_ETH)
case ETH_GIG_UNIT_ID:
- if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index))
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ mask = AXP_PMC_GESTOPCLOCK_MASK(index);
+ stop = AXP_PMC_GESTOPCLOCK_STOP(index);
+ } else {
+ mask = PMC_GESTOPCLOCK_MASK(index);
+ stop = PMC_GESTOPCLOCK_STOP(index);
+ }
+
+ if ((reg & mask) == stop)
state = MV_FALSE;
else
state = MV_TRUE;
@@ -1337,7 +1633,49 @@
#endif
#if defined(MV_INCLUDE_SDIO)
case SDIO_UNIT_ID:
- if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP)
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ mask = AXP_PMC_SDIOSTOPCLOCK_MASK;
+ stop = AXP_PMC_SDIOSTOPCLOCK_STOP;
+ } else {
+ mask = PMC_SDIOSTOPCLOCK_MASK;
+ stop = PMC_SDIOSTOPCLOCK_STOP;
+ }
+
+ if ((reg & mask) == stop)
+ state = MV_FALSE;
+ else
+ state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if ((reg & AXP_PMC_CESASTOPCLOCK_MASK) == AXP_PMC_CESASTOPCLOCK_STOP)
+ state = MV_FALSE;
+ else
+ state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID)
+ state = MV_TRUE;
+ else if ((reg & AXP_PMC_USBSTOPCLOCK_MASK(index)) == AXP_PMC_USBSTOPCLOCK_STOP(index))
+ state = MV_FALSE;
+ else
+ state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_SATA)
+ case SATA_UNIT_ID:
+ if ((reg & AXP_PMC_SATASTOPCLOCK_MASK(index)) == AXP_PMC_SATASTOPCLOCK_STOP(index))
+ state = MV_FALSE;
+ else
+ state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_TDM)
+ case TDM_UNIT_ID:
+ if ((reg & AXP_PMC_TDMSTOPCLOCK_MASK) == AXP_PMC_TDMSTOPCLOCK_STOP)
state = MV_FALSE;
else
state = MV_TRUE;
@@ -1366,9 +1704,16 @@
MV_U32 mvCtrlDDRBudWidth(MV_VOID)
{
MV_U32 reg;
- reg = MV_REG_READ(REG_SDRAM_CONFIG_ADDR);
- return (reg & (1 << REG_SDRAM_CONFIG_DDR_BUS_OFFS)) ? 32 : 16;
+ reg = MV_REG_READ(REG_SDRAM_CONFIG_ADDR);
+ reg = reg & (1 << REG_SDRAM_CONFIG_DDR_BUS_OFFS);
+
+ /* Bobcat2 and BobK have 64/16 DDR Bus width */
+ if (mvCtrlDevFamilyIdGet(0) == MV_BOBCAT2_DEV_ID || mvCtrlDevFamilyIdGet(0) == MV_BOBK_DEV_ID)
+ return reg ? 64 : 32;
+ else /* Alley-Cat3 have 32/16 DDR Bus width */
+ return reg ? 32 : 16;
+
}
MV_BOOL mvCtrlDDRThruXbar(MV_VOID)
{
@@ -1386,6 +1731,166 @@
return (reg & (0x1 << REG_SDRAM_CONFIG_ECC_OFFS)) ? MV_TRUE : MV_FALSE;
}
+static const MV_U8 serdesCfg[][8] = SERDES_CFG_AXP;
+
+/*******************************************************************************
+* mvCtrlSerdesPhyConfigAxp
+*
+* DESCRIPTION:
+* Configure Serdes MUX and init PHYs connected to SERDES lines for AXP.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Status
+*
+*******************************************************************************/
+MV_STATUS mvCtrlSerdesPhyConfigAxp(MV_VOID)
+{
+ MV_U32 socCtrlReg, RegX4, serdesLine0_7;
+ MV_U32 serdesLineCfg;
+ MV_U8 serdesLineNum;
+ MV_U8 pexIf;
+ MV_U8 pexUnit;
+ MV_STATUS status = MV_OK;
+ MV_U32 pexIfNum = mvCtrlPexMaxIfGet();
+ MV_U8 maxSerdesLines = 16; /* Valid for MV_78460_DEV_ID */
+ MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet();
+
+ /* This is a mapping of the final power management clock
+ * gating control register value @ 0x18220
+ */
+ MV_U32 powermngmntctrlregmap = 0x0;
+ MV_U32 tmpcounter = 0;
+
+ /* Check if no SERDESs available - FPGA */
+ if (maxSerdesLines == 0)
+ return MV_OK;
+
+ memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO));
+ socCtrlReg = MV_REG_READ(SOC_CTRL_REG);
+ RegX4 = MV_REG_READ(GEN_PURP_RES_2_REG);
+ boardPexInfo->pexUnitCfg[0].pexCfg = ((RegX4 & 0x0F) == 0x0F) ? PEX_BUS_MODE_X4 : PEX_BUS_MODE_X1;
+ boardPexInfo->pexUnitCfg[1].pexCfg = ((RegX4 & 0x0F0) == 0x0F0) ? PEX_BUS_MODE_X4 : PEX_BUS_MODE_X1;
+ boardPexInfo->pexUnitCfg[2].pexCfg = ((RegX4 & 0x0F00) == 0x0F00) ? PEX_BUS_MODE_X4 : PEX_BUS_MODE_X1;
+ boardPexInfo->pexUnitCfg[3].pexCfg = ((RegX4 & 0x0F000) == 0x0F000) ? PEX_BUS_MODE_X4 : PEX_BUS_MODE_X1;
+
+ serdesLine0_7 = MV_REG_READ(SERDES_LINE_MUX_REG_0_7);
+ /* Prepare PHY parameters for each step according to MUX selection */
+ for (pexIf = 0; pexIf < pexIfNum; pexIf++) {
+ /* For each serdes lane */
+ pexUnit = (pexIf < 9) ? (pexIf >> 2) : 3;
+ if ((socCtrlReg & (1 << pexUnit)) == 0) {
+ boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_DISABLED;
+ continue;
+ }
+ if (pexIf < 8) {
+ serdesLineCfg = (serdesLine0_7 >> (pexIf << 2)) & 0xF;
+ if (serdesLineCfg != serdesCfg[pexIf][SERDES_UNIT_PEX])
+ continue;
+ }
+ boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexIf;
+ boardPexInfo->boardPexIfNum++;
+ boardPexInfo->pexUnitCfg[pexUnit].pexLaneStat[pexIf] = 0x1;
+ powermngmntctrlregmap = powermngmntctrlregmap | (0x1 << (pexIf + 5));
+ if (pexIf < 8) {
+ if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4) {
+ powermngmntctrlregmap |= (0xf << (pexIf + 5));
+ pexIf += 3;
+ } else
+ powermngmntctrlregmap |= (0x1 << (pexIf + 5));
+ } else
+ powermngmntctrlregmap |= (0x1 << (18 + pexIf));
+ }
+
+ for (serdesLineNum = 0; serdesLineNum < 8; serdesLineNum++) {
+ serdesLineCfg = (serdesLine0_7 >> (serdesLineNum << 2)) & 0xF;
+ if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SATA]) {
+ if ((serdesLineNum == 4) || (serdesLineNum == 6))
+ powermngmntctrlregmap |= AXP_PMC_SATASTOPCLOCK_MASK(0);
+ else if (serdesLineNum == 5)
+ powermngmntctrlregmap |= AXP_PMC_SATASTOPCLOCK_MASK(1);
+ else
+ goto err_cfg;
+
+ } else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII0])
+ powermngmntctrlregmap |= AXP_PMC_GESTOPCLOCK_MASK(0);
+ else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII1])
+ powermngmntctrlregmap |= AXP_PMC_GESTOPCLOCK_MASK(1);
+ else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII2])
+ powermngmntctrlregmap |= AXP_PMC_GESTOPCLOCK_MASK(2);
+ else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII3])
+ powermngmntctrlregmap |= AXP_PMC_GESTOPCLOCK_MASK(3);
+ else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII])
+ powermngmntctrlregmap |= AXP_PMC_GESTOPCLOCK_MASK(0) |
+ AXP_PMC_GESTOPCLOCK_MASK(1) |
+ AXP_PMC_GESTOPCLOCK_MASK(2) |
+ AXP_PMC_GESTOPCLOCK_MASK(3);
+ }
+
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Enabling port GE0 always since we need SMI 0 to access other PHYs*/
+ powermngmntctrlregmap = powermngmntctrlregmap | BIT4;
+ /* Check if GE1 is not enabled via MPPs and not Serdes - if yes you have to enable the clock*/
+ if (MV_TRUE == mvBoardIsGbEPortConnected(1))
+ powermngmntctrlregmap = powermngmntctrlregmap | AXP_PMC_GESTOPCLOCK_MASK(1);
+
+ /* Hard core enable DDR, USB, SDIO, LCD, XOR, IDMA, CESA cause we don't support this at this momemt*/
+ powermngmntctrlregmap = powermngmntctrlregmap | (BIT0 | BIT13 | (0x1FF<<16) |
+ BIT24 | BIT25 | BIT28 | BIT31);
+ DB(mvOsPrintf("%s:Shutting down unused interfaces:\n", __func__));
+ /* Now report everything to the screen*/
+ if (!(powermngmntctrlregmap & AXP_PMC_SATASTOPCLOCK_MASK(0))) {
+ DB(mvOsPrintf("%s: SATA0\n", __func__));
+ mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE);
+ }
+ if (!(powermngmntctrlregmap & AXP_PMC_SATASTOPCLOCK_MASK(1))) {
+ DB(mvOsPrintf("%s: SATA1\n", __func__));
+ mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE);
+ }
+ for (tmpcounter = 0; tmpcounter < 4; tmpcounter++) {
+ if (!(powermngmntctrlregmap & (1 << (4 - tmpcounter)))) {
+ DB(mvOsPrintf("%s: GBE%d\n", __func__, tmpcounter));
+ mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, tmpcounter, MV_FALSE);
+ }
+ }
+ for (tmpcounter = 0; tmpcounter < 8; tmpcounter++) {
+ if (!(powermngmntctrlregmap & (1 << (5 + tmpcounter)))) {
+ DB(mvOsPrintf("%s: PEX%d.%d\n", __func__, tmpcounter>>2, tmpcounter % 4));
+ mvCtrlPwrClckSet(PEX_UNIT_ID, tmpcounter, MV_FALSE);
+ }
+ }
+ if (!(powermngmntctrlregmap & BIT26)) {
+ DB(mvOsPrintf("%s: PEX2\n", __func__));
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 8, MV_FALSE);
+ }
+ if (!(powermngmntctrlregmap & BIT27)) {
+ DB(mvOsPrintf("%s: PEX3\n", __func__));
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 9, MV_FALSE);
+ }
+
+ if (!(powermngmntctrlregmap & BIT25)) {
+ DB(mvOsPrintf("%s: TDM\n", __func__));
+ mvCtrlPwrClckSet(TDM_UNIT_ID, 0, MV_FALSE);
+ }
+
+ /* Apply clock gating */
+ MV_REG_WRITE(POWER_MNG_CTRL_REG, MV_REG_READ(POWER_MNG_CTRL_REG) & powermngmntctrlregmap);
+ /* The Sata driver doesn't support clock gating at this point so we enable the logic to the block*/
+ MV_REG_WRITE(POWER_MNG_CTRL_REG, MV_REG_READ(POWER_MNG_CTRL_REG) | (BIT15 | BIT30));
+#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */
+
+ return status;
+err_cfg:
+ DB(mvOsPrintf("%s: Wrong CFG (%#x) for SERDES line %d.\n",
+ __func__, serdesLineCfg, serdesLineNum));
+ return MV_ERROR;
+}
+
/*******************************************************************************
* mvCtrlSerdesPhyConfig
*
@@ -1548,6 +2053,53 @@
}
/*******************************************************************************
+* mvCtrlNandClkSetAxp
+*
+* DESCRIPTION:
+* Set the division ratio of ECC Clock for AXP
+*
+*******************************************************************************/
+static int mvCtrlNandClkSetAxp(int nfc_clk_freq, MV_U32 pll_clk)
+{
+ int divider;
+
+ /* Set the division ratio of ECC Clock 0x00018748[13:8] (by default it's
+ * double of core clock)
+ */
+ MV_U32 nVal = MV_REG_READ(AXP_CORE_DIV_CLK_CTRL(1));
+
+ /* Calculate nand divider for requested nfc_clk_freq. If integer divider
+ * cannot be achieved, it will be rounded-up, which will result in
+ * setting the closest lower frequency.
+ * ECC engine clock = (PLL frequency / divider)
+ * NFC clock = ECC clock / 2
+ */
+ divider = DIV_ROUND_UP(pll_clk, (2 * nfc_clk_freq));
+ DB(mvOsPrintf("%s: divider %d\n", __func__, divider));
+
+ nVal &= ~(AXP_NAND_ECC_DIVCLK_RATIO_MASK);
+ nVal |= (divider << AXP_NAND_ECC_DIVCLK_RATIO_OFFS);
+ MV_REG_WRITE(AXP_CORE_DIV_CLK_CTRL(1), nVal);
+
+ /* Set reload force of ECC clock 0x00018740[7:0] to 0x2 (meaning you
+ * will force only the ECC clock)
+ */
+ nVal = MV_REG_READ(AXP_CORE_DIV_CLK_CTRL(0));
+ nVal &= ~(AXP_CORE_DIVCLK_RELOAD_FORCE_MASK);
+ nVal |= AXP_CORE_DIVCLK_RELOAD_FORCE_VAL;
+ MV_REG_WRITE(AXP_CORE_DIV_CLK_CTRL(0), nVal);
+
+ /* Set reload ratio bit 0x00018740[8] to 1'b1 */
+ MV_REG_BIT_SET(AXP_CORE_DIV_CLK_CTRL(0), AXP_CORE_DIVCLK_RELOAD_RATIO_MASK);
+ mvOsDelay(1); /* msec */
+ /* Set reload ratio bit 0x00018740[8] to 0'b1 */
+ MV_REG_BIT_RESET(AXP_CORE_DIV_CLK_CTRL(0), AXP_CORE_DIVCLK_RELOAD_RATIO_MASK);
+
+ /* Return calculated nand clock frequency */
+ return (pll_clk)/(2 * divider);
+}
+
+/*******************************************************************************
* mvCtrlNandClkSet
*
* DESCRIPTION:
@@ -1565,9 +2117,14 @@
int mvCtrlNandClkSet(int nfc_clk_freq)
{
int divider;
- MV_U32 nVal = MV_DFX_REG_READ(CORE_DIV_CLK_CTRL(2));
+ MV_U32 nVal;
MV_U32 pll_clk = mvCpuPllClkGet();
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return mvCtrlNandClkSetAxp(nfc_clk_freq, pll_clk);
+
+ nVal = MV_DFX_REG_READ(CORE_DIV_CLK_CTRL(2));
+
/*
* Calculate nand divider for requested nfc_clk_freq. If integer divider
* cannot be achieved, it will be rounded-up, which will result in
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.h
index 624d149..1e11379 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.h
@@ -82,6 +82,18 @@
/* typedefs */
typedef MV_STATUS(*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*);
+/* SERDES description - AXP only */
+typedef enum {
+ SERDES_UNIT_UNCONNECTED = 0x0,
+ SERDES_UNIT_PEX = 0x1,
+ SERDES_UNIT_SATA = 0x2,
+ SERDES_UNIT_SGMII0 = 0x3,
+ SERDES_UNIT_SGMII1 = 0x4,
+ SERDES_UNIT_SGMII2 = 0x5,
+ SERDES_UNIT_SGMII3 = 0x6,
+ SERDES_UNIT_QSGMII = 0x7,
+ SERDES_UNIT_LAST
+} MV_SERDES_UNIT_INDX;
typedef enum {
PEX_BUS_DISABLED = 0,
@@ -162,11 +174,12 @@
MV_U32 mvCtrlEthMaxPortGet(MV_VOID);
MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID);
-#if defined(MV_INCLUDE_USB)
MV_U32 mvCtrlUsbMaxGet(MV_VOID);
+#if defined(MV_INCLUDE_USB)
MV_U32 mvCtrlUsb3MaxGet(MV_VOID);
MV_U32 mvCtrlUsb3HostMaxGet(MV_VOID);
MV_VOID mvCtrlUtmiPhySelectorSet(MV_U32 usbUnitId);
+MV_BOOL mvCtrlIsUsbSerDesConnected(MV_U32 usbPort);
#endif
#if defined(MV_INCLUDE_XOR)
MV_U32 mvCtrlXorMaxChanGet(MV_VOID);
@@ -197,6 +210,7 @@
MV_BOOL mvCtrlIsBootFromNAND(MV_VOID);
MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index);
MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID);
+MV_STATUS mvCtrlSerdesPhyConfigAxp(MV_VOID);
MV_BOOL mvCtrlIsDLBEnabled(MV_VOID);
MV_U32 mvCtrlDDRBudWidth(MV_VOID);
MV_BOOL mvCtrlDDRThruXbar(MV_VOID);
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index f1d2632..bc7c468 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -151,6 +151,73 @@
#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port))
+/* Power Management Clock Gating Control Register - AXP only */
+
+#define AXP_PMC_TDMSTOPCLOCK_OFFS 25
+#define AXP_PMC_TDMSTOPCLOCK_MASK (1 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+#define AXP_PMC_TDMSTOPCLOCK_EN (1 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+#define AXP_PMC_TDMSTOPCLOCK_STOP (0 << AXP_PMC_TDMSTOPCLOCK_OFFS)
+
+#define AXP_PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port)))
+#define AXP_PMC_PEXSTOPCLOCK_MASK(port) (1 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+#define AXP_PMC_PEXSTOPCLOCK_EN(port) (1 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+#define AXP_PMC_PEXSTOPCLOCK_STOP(port) (0 << AXP_PMC_PEXSTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_USBSTOPCLOCK_OFFS(port) ((port) < 3 ? (18 + (port)) : 0)
+#define AXP_PMC_USBSTOPCLOCK_MASK(port) (1 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+#define AXP_PMC_USBSTOPCLOCK_EN(port) (1 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+#define AXP_PMC_USBSTOPCLOCK_STOP(port) (0 << AXP_PMC_USBSTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_SDIOSTOPCLOCK_OFFS 17
+#define AXP_PMC_SDIOSTOPCLOCK_MASK (1 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+#define AXP_PMC_SDIOSTOPCLOCK_EN (1 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+#define AXP_PMC_SDIOSTOPCLOCK_STOP (0 << AXP_PMC_SDIOSTOPCLOCK_OFFS)
+
+#define AXP_PMC_RUNITSTOPCLOCK_OFFS 24
+#define AXP_PMC_RUNITSTOPCLOCK_MASK (1 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+#define AXP_PMC_RUNITSTOPCLOCK_EN (1 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+#define AXP_PMC_RUNITSTOPCLOCK_STOP (0 << AXP_PMC_RUNITSTOPCLOCK_OFFS)
+
+#define AXP_PMC_XORSTOPCLOCK_OFFS 22
+#define AXP_PMC_XORSTOPCLOCK_MASK (1 << AXP_PMC_XORSTOPCLOCK_OFFS)
+#define AXP_PMC_XORSTOPCLOCK_EN (1 << AXP_PMC_XORSTOPCLOCK_OFFS)
+#define AXP_PMC_XORSTOPCLOCK_STOP (0 << AXP_PMC_XORSTOPCLOCK_OFFS)
+
+#define AXP_PMC_SATASTOPCLOCK_OFFS(ch) (ch == 0 ? 14 : 29)
+#define AXP_PMC_SATASTOPCLOCK_MASK(ch) (3 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+#define AXP_PMC_SATASTOPCLOCK_EN(ch) (3 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+#define AXP_PMC_SATASTOPCLOCK_STOP(ch) (0 << AXP_PMC_SATASTOPCLOCK_OFFS(ch))
+
+#define AXP_PMC_CESASTOPCLOCK_OFFS 23
+#define AXP_PMC_CESASTOPCLOCK_MASK (1 << AXP_PMC_CESASTOPCLOCK_OFFS)
+#define AXP_PMC_CESASTOPCLOCK_EN (1 << AXP_PMC_CESASTOPCLOCK_OFFS)
+#define AXP_PMC_CESASTOPCLOCK_STOP (0 << AXP_PMC_CESASTOPCLOCK_OFFS)
+
+#define AXP_PMC_GESTOPCLOCK_OFFS(port) ((port) < 4 ? (4 - (port)) : 0)
+#define AXP_PMC_GESTOPCLOCK_MASK(port) (1 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+#define AXP_PMC_GESTOPCLOCK_EN(port) (1 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+#define AXP_PMC_GESTOPCLOCK_STOP(port) (0 << AXP_PMC_GESTOPCLOCK_OFFS(port))
+
+#define AXP_PMC_NETASTOPCLOCK_OFFS 13
+#define AXP_PMC_NETASTOPCLOCK_MASK (1 << AXP_PMC_NETASTOPCLOCK_OFFS)
+#define AXP_PMC_NETASTOPCLOCK_EN (1 << AXP_PMC_NETASTOPCLOCK_OFFS)
+#define AXP_PMC_NETASTOPCLOCK_STOP (0 << AXP_PMC_NETASTOPCLOCK_OFFS)
+
+#define AXP_PMC_LCDSTOPCLOCK_OFFS 16
+#define AXP_PMC_LCDSTOPCLOCK_MASK (1 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+#define AXP_PMC_LCDSTOPCLOCK_EN (1 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+#define AXP_PMC_LCDSTOPCLOCK_STOP (0 << AXP_PMC_LCDSTOPCLOCK_OFFS)
+
+#define AXP_PMC_IDMASTOPCLOCK_OFFS 21
+#define AXP_PMC_IDMASTOPCLOCK_MASK (1 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+#define AXP_PMC_IDMASTOPCLOCK_EN (1 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+#define AXP_PMC_IDMASTOPCLOCK_STOP (0 << AXP_PMC_IDMASTOPCLOCK_OFFS)
+
+#define AXP_PMC_DDRSTOPCLOCK_OFFS 28
+#define AXP_PMC_DDRSTOPCLOCK_MASK (1 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+#define AXP_PMC_DDRSTOPCLOCK_EN (1 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+#define AXP_PMC_DDRSTOPCLOCK_STOP (0 << AXP_PMC_DDRSTOPCLOCK_OFFS)
+
/* dummy defenition, used for SGMII capable interfaces */
#define SGMII_SERDES_CFG_REG(port) (0)
@@ -158,6 +225,27 @@
#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
+/* Switch core registers */
+#define MV_PP_ADDCOMP_CNCTRL 0x00000140
+#define MV_PP_ADDCOMP_REG(n) (0x00000120 + 4*n)
+#define MV_PP_ADDCOMP_MODE_BIT 16
+#define MV_PP_ADDCOMP_MODE_MASK (1 << MV_PP_ADDCOMP_MODE_BIT)
+
+#define MV_PP_SMI_MISC_CONFIG_OFFSET 0x4
+#define MV_PP_SMI_INVERT_MDC_BIT 11
+#define MV_PP_SMI_INVERT_MDC_MASK (1 << MV_PP_SMI_INVERT_MDC_BIT)
+
+#define MV_PP_ETH_ADDCOMP_INDEX 1
+#define MV_PP_ETH_REG_BASE_NORNAL (SWITCH_REGS_VIRT_BASE | MV_PP_ETH_ADDCOMP_INDEX<<19)
+#define MV_PP_ETH_REG_BASE_LEGACY (SWITCH_REGS_VIRT_BASE | MV_PP_ETH_ADDCOMP_INDEX<<24)
+
+/* Sample at Reset - AXP only */
+#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
+
+/* Controller environment and SERDERS registers - AXP only */
+#define SERDES_LINE_MUX_REG_0_7 0x18270
+#define GEN_PURP_RES_2_REG 0x182F8
+
/* Dragonite Register */
#define DRAGONITE_CTRL_REG 0x1c
#define DRAGONITE_POE_CAUSE_IRQ_REG 0x64
@@ -178,6 +266,9 @@
#define MSAR_AC3_BOOT_MODE(sar1, sar2) (((sar1) >> 11) & 0x7) /* boot from */
#define MSAR_AC3_TM_CLK(sar1, sar2) (((sar2) >> 17) & 0x1) /* PLL 2 config */
+#define MSAR_BOBK_BOOT_MODE(sar1, sar2) (((sar1) >> 13) & 0x7) /* boot from */
+#define MSAR_BOBK_TM_CLK(sar1, sar2) (((sar2) >> 15) & 0x7) /* PLL 2 config */
+
#define SAR1_BOOT_FROM_NOR 0
#define SAR1_BOOT_FROM_NAND 1
#define SAR1_BOOT_FROM_UART 2
@@ -209,10 +300,23 @@
#define CORE_DIV_CLK_CTRL(num) (DFX_CORE_DIVCLK_CONTROL0_REG + ((num) * 0x4))
-
#define DFX_TEMPERATURE_SENSOR_LSB_CTRL_REG 0xF8070
#define DFX_TEMPERATURE_SENSOR_MSB_CTRL_REG 0xF8074
#define DFX_TEMPERATURE_SENSOR_STATUS_REG 0xF8078
+
+/* Core Divider Clock Control - AXP only */
+#define AXP_CORE_DIV_CLK_CTRL(num) (0x18740 + ((num) * 0x8))
+
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS 0
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_MASK (0xFF << AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS)
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_VAL (0x2 << AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS)
+
+#define AXP_NAND_ECC_DIVCLK_RATIO_OFFS 8
+#define AXP_NAND_ECC_DIVCLK_RATIO_MASK (0x3F << AXP_NAND_ECC_DIVCLK_RATIO_OFFS)
+
+#define AXP_CORE_DIVCLK_RELOAD_RATIO_OFFS 8
+#define AXP_CORE_DIVCLK_RELOAD_RATIO_MASK (1 << AXP_CORE_DIVCLK_RELOAD_RATIO_OFFS)
+
/* definition for caculate Temperature */
#define TEMPERATURE_OFFSET (596)
#define TEMPERATURE_FACTOR (2154)
@@ -255,6 +359,7 @@
#define ICDR_UINIT_ID_MASK 0x0F
#define ICDR_UNIT_ID_4_DFX 0x0f
+#define CPLD_RD_MTL_BC2_BOARD_REV_REG 2
#define CPLD_BOARD_REV_REG 1
#define CPLD_BOARD_REV_MASK 0x7
#define CPLD_REV_REG 2
@@ -263,27 +368,114 @@
#define DEV_ID_REG 0x1823C
#define DEVICE_ID_OFFS 0
#define DEVICE_ID_MASK 0xFFFF
-#define DEVICE_FLAVOR_MASK 0xFF
+
+/* for BobK devID, Cetus: 0xBE00 Caelum:0xBC00, the higher 6bits are the same.
+so update mask to 0x3FF, for BC2 flavor(0xF4XX), and AC3 flavor(0xFC00),
+the higher 6bits are also the same, so can work normally */
+#define DEVICE_FLAVOR_MASK 0x3FF
+
+#define BOBK_FLAVOR_MASK 0xFF /* only for Cetus & Caelum flavor */
#define DEV_REV_ID_REG 0xF8244
#define REVISON_ID_OFFS 28
#define REVISON_ID_MASK 0xF0000000
/* Extract CPU, L2, DDR clocks SAR value from
-** SAR bits 24-27
-*/
+ * SAR bits 24-27 - AXP only
+ */
+#define MSAR_CPU_CLK_IDX(sar0, sar1) ((((sar0) >> 21) & 0x7) + ((((sar1) >> 20) & 1) << 3))
+#define MSAR_CPU_CLK_TWSI(sar0, sar1) ((((sar0) >> 2) & 0x7) + (((sar1) & 1) << 3))
+#define MSAR_DDR_L2_CLK_RATIO_IDX(sar0, sar1) ((((sar0) >> 24) & 0xF) + ((((sar1) >> 19) & 1) << 4))
+#define MSAR_DDR_L2_CLK_RATIO_TWSI(sar0) (((sar0) >> 1) & 0xF)
+/* SAR TCLK bit - AXP only */
+#define MSAR_TCLK_OFFS 28
+#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
+
+/* PLL(CPU) input clock - AXP only */
+#define AXP_PLL_IN_CLK _2GHz
#ifndef MV_ASMLANGUAGE
+#define MV_CPU_CLK_TBL_AXP { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000,\
+ 600, 667, 800, 1600, 2133, 2200, 2400, 0 }
+/* cpu l2c hclk ddr */
+#define MV_DDR_L2_CLK_RATIO_TBL_AXP { \
+/*00*/ { 1, 1, 4, 2 },\
+/*01*/ { 1, 2, 2, 2 },\
+/*02*/ { 2, 2, 6, 3 },\
+/*03*/ { 2, 2, 3, 3 },\
+/*04*/ { 1, 2, 3, 3 },\
+/*05*/ { 1, 2, 4, 2 },\
+/*06*/ { 1, 1, 2, 2 },\
+/*07*/ { 2, 3, 6, 6 },\
+/*08*/ { 2, 3, 5, 5 },\
+/*09*/ { 1, 2, 6, 3 },\
+/*10*/ { 2, 4, 10, 5 },\
+/*11*/ { 1, 3, 6, 6 },\
+/*12*/ { 1, 2, 4, 4 },\
+/*13*/ { 1, 3, 6, 3 },\
+/*14*/ { 1, 2, 5, 5 },\
+/*15*/ { 2, 2, 5, 5 },\
+/*16*/ { 1, 1, 3, 3 },\
+/*17*/ { 2, 5, 10, 10 },\
+/*18*/ { 1, 3, 8, 4 },\
+/*19*/ { 1, 1, 2, 1 },\
+/*20*/ { 2, 3, 6, 3 },\
+/*21*/ { 1, 2, 8, 4 },\
+/*22*/ { 2, 5, 10, 5 } \
+}
+
+/* This structure refrect registers:
+ * Serdes 0-7 selectors 0x18270
+ * and Serdes 8-15 selectors 0x18274
+ * AXP only
+ */
+
+#define SERDES_CFG_AXP { \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 0 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 1 */ \
+ {0, 1, -1 , 2, -1, -1, -1, -1}, /* Lane 2 */ \
+ {0, 1, -1 , -1, 2, -1, -1, 3}, /* Lane 3 */ \
+ {0, 1, 2 , -1, -1, 3, -1, -1}, /* Lane 4 */ \
+ {0, 1, 2 , -1, 3, -1, -1, 4}, /* Lane 5 */ \
+ {0, 1, 2 , 4, -1, 3, -1, -1}, /* Lane 6 */ \
+ {0, 1, -1 , 2, -1, -1, 3, -1}, /* Lane 7 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 8 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 9 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 10 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 11 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 12 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 13 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 14 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1} /* Lane 15 */ \
+}
/* These macros help units to identify a target Mport Arbiter group */
#define MV_TARGET_IS_DRAM(target) \
((target >= SDRAM_CS0) && (target <= SDRAM_CS3))
#define MV_TARGET_IS_PEX0(target) \
((target >= PEX0_MEM) && (target <= PEX0_IO))
+#define MV_TARGET_IS_PEX1(target) \
+ ((target >= (MV_8)PEX1_MEM) && (target <= (MV_8)PEX1_IO))
+#define MV_TARGET_IS_PEX2(target) \
+ ((target >= (MV_8)PEX2_MEM) && (target <= (MV_8)PEX2_IO))
+#define MV_TARGET_IS_PEX3(target) \
+ ((target >= (MV_8)PEX3_MEM) && (target <= (MV_8)PEX3_IO))
+#define MV_TARGET_IS_PEX4(target) \
+ ((target >= (MV_8)PEX4_MEM) && (target <= (MV_8)PEX4_IO))
+#define MV_TARGET_IS_PEX5(target) \
+ ((target >= (MV_8)PEX5_MEM) && (target <= (MV_8)PEX5_IO))
+#define MV_TARGET_IS_PEX6(target) \
+ ((target >= (MV_8)PEX6_MEM) && (target <= (MV_8)PEX6_IO))
+#define MV_TARGET_IS_PEX7(target) \
+ ((target >= (MV_8)PEX7_MEM) && (target <= (MV_8)PEX7_IO))
+#define MV_TARGET_IS_PEX8(target) \
+ ((target >= (MV_8)PEX8_MEM) && (target <= (MV_8)PEX8_IO))
+#define MV_TARGET_IS_PEX9(target) \
+ ((target >= (MV_8)PEX9_MEM) && (target <= (MV_8)PEX9_IO))
-#define MV_TARGET_IS_PEX(target) MV_TARGET_IS_PEX0(target)
+#define MV_TARGET_IS_PEX(target) ((target >= PEX0_MEM) && (target <= (MV_8)PEX9_IO))
#define MV_TARGET_IS_DEVICE(target) ((target >= DEVICE_CS0) && (target <= DEVICE_CS3))
@@ -321,7 +513,16 @@
typedef enum {
PEX0_0x4 = 0,
- PEXIF_MAX = 1
+ PEX0_1x4 = 1,
+ PEX0_2x4 = 2,
+ PEX0_3x4 = 3,
+ PEX1_0x4 = 4,
+ PEX1_1x4 = 5,
+ PEX1_2x4 = 6,
+ PEX1_3x4 = 7,
+ PEX2_0x4 = 8,
+ PEX3_0x4 = 9,
+ PEXIF_MAX = 10
} MV_PEXIF_INDX;
typedef struct {
@@ -344,6 +545,24 @@
450 \
}
+#define MV_CORE_CLK_TBL_BOBK_CETUS { \
+ 365, 220, \
+ 250, 200, \
+ 167 \
+ }
+
+#define MV_CORE_CLK_TBL_BOBK_CAELUM { \
+ 365, 220, \
+ 250, 200, \
+ 167, 133 \
+ }
+
+#define MV_BYPASS_CORE_CLK_TBL_BOBK { \
+ 365, 220, \
+ 250, 200, \
+ 167 \
+ }
+
#define MV_CORE_CLK_TBL_AC3 { \
290, 250, \
222, 167, \
@@ -362,6 +581,26 @@
{1333, 666, 1600, MV_TRUE} \
}
+#define MV_CPU_DDR_CLK_TBL_BOBK_CETUS { \
+ { 400, 400, 400, MV_FALSE}, \
+ {1000, 667, 2000, MV_FALSE}, \
+ { 667, 667, 2000, MV_FALSE}, \
+ { 800, 800, 800, MV_FALSE}, \
+ {1200, 800, 2400, MV_FALSE}, \
+ { 800, 400, 800, MV_FALSE}, \
+ { 800, 800, 800, MV_TRUE} \
+}
+
+#define MV_CPU_DDR_CLK_TBL_BOBK_CAELUM { \
+ { 400, 400, 400, MV_FALSE}, \
+ {1000, 667, 2000, MV_TRUE}, \
+ { 667, 667, 2000, MV_FALSE}, \
+ { 800, 800, 800, MV_FALSE}, \
+ {1200, 800, 2400, MV_TRUE}, \
+ { 800, 400, 800, MV_FALSE}, \
+ { 800, 800, 800, MV_TRUE} \
+}
+
#define MV_CPU_DDR_CLK_TBL_AC3 { \
{ 533, 533, 533, MV_TRUE}, \
{ 667, 667, 2000, MV_FALSE}, \
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
index 21026e9..6854b95 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -70,19 +70,23 @@
#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#define MAX_TARGETS (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID ? \
+ MAX_TARGETS_AXP : MAX_TARGETS_MSYS)
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define MV_ARM_SOC
-#ifdef CONFIG_ALLEYCAT3
+#if defined CONFIG_ALLEYCAT3
#define SOC_NAME_PREFIX "Alleycat3"
-#else
+#elif defined CONFIG_BOBCAT2
#define SOC_NAME_PREFIX "Bobcat2"
+#else
+#define SOC_NAME_PREFIX "BobK"
#endif
/*
- * Bobcat2 Units Address decoding
+ * Bobcat2/AXP Units Address decoding
*/
#define MV_DRAM_REGS_OFFSET (0x0)
#define MV_AURORA_L2_REGS_OFFSET (0x8000)
@@ -92,9 +96,11 @@
#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100))
#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100))
+#define MV_RUNIT_PMU_REGS_OFFSET (0x1C000)
#define MV_MPP_REGS_OFFSET (0x18000)
#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x80))
+#define MV_GPP_REGS_OFFSET_AXP(unit) (0x18100 + ((unit) * 0x40))
#define MV_MISC_REGS_OFFSET (0x18200)
#define MV_CLK_CMPLX_REGS_OFFSET (0x18700)
@@ -108,16 +114,21 @@
#define MV_CPUIF_REGS_OFFSET(cpu) (0x21800 + (cpu) * 0x100)
#define MV_PMU_NFABRIC_UNIT_SERV_OFFSET (0x22000)
#define MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) (0x22100 + (cpu) * 0x100)
+#define MV_CPU_HW_SEM_OFFSET (0x20500)
#define MV_ETH_BASE_ADDR (0x70000)
-#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR + (port) * 0x4000)
+#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * 0x40000 + ((port) % 2) * 0x4000)
#define MV_PEX_IF_REGS_OFFSET(pexIf)\
(pexIf < 8 ? (0x40000 + ((pexIf) / 4) * 0x40000 + ((pexIf) % 4) * 0x4000)\
: (0X42000 + ((pexIf) % 8) * 0x40000))
#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000))
+#define MV_USB2_USB3_REGS_OFFSET(unitType, dev) (MV_USB_REGS_OFFSET(dev))
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
+#define MV_XOR_REGS_OFFSET_AXP(unit) (unit ? 0xF0900 : 0x60900)
#if defined(MV_INCLUDE_IDMA)
#define MV_IDMA_REGS_OFFSET (0x60800)
#endif
+#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000))
+#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000))
#define MV_SATA_REGS_OFFSET (0xA0000)
#define MV_COMM_UNIT_REGS_OFFSET (0xB0000)
#define MV_NFC_REGS_OFFSET (0xD0000)
@@ -126,8 +137,11 @@
#define MV_SDMMC_REGS_OFFSET (0xD4000)
#define MV_USB2_CAPLENGTH_OFFSET(index) (INTER_REGS_BASE + MV_USB_REGS_OFFSET(index) + 0x100)
-
#define MV_ETH_SMI_PORT 0
+
+#define MV_PP_SMI_BASE(n) (0x54000000 + 0x01000000*n)
+#define MV_PP_ETH_SMI_PORT 0
+
/*
* Miscellanuous Controller Configurations
*/
@@ -142,17 +156,19 @@
#define TWSI0_CPU_MAIN_INT_BIT(ch) ((ch) + 3)
#define TWSI_SPEED 100000
-#define MV_GPP_MAX_PINS 33
+#define MV_GPP_MAX_PINS 68
#define MV_GPP_MAX_GROUP 2 /* group == configuration register? */
+#define MV_GPP_MAX_GROUP_AXP 3
#define MV_CNTMR_MAX_COUNTER 8 /* 4 global + 1 global WD + 2 current private CPU + 1 private CPU WD*/
#define MV_UART_MAX_CHAN 2
-#define MV_XOR_MAX_UNIT 1 /* XOR unit == XOR engine */
-#define MV_XOR_MAX_CHAN 2 /* total channels for all units together*/
+#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_MPP_MAX_GROUP 5
+#define MV_MPP_MAX_GROUP_AXP 9
#define MV_DRAM_MAX_CS 4
#define MV_SPI_MAX_CS 8
@@ -168,8 +184,8 @@
#endif
/* This define describes the maximum number of supported PEX Interfaces */
-#define MV_PEX_MAX_IF 1
-#define MV_PEX_MAX_UNIT 1
+#define MV_PEX_MAX_IF 10 /* 1 for MSYS */
+#define MV_PEX_MAX_UNIT 4 /* 1 for MSYS */
#ifdef MV_INCLUDE_PEX
#define MV_INCLUDE_PEX0
#define MV_DISABLE_PEX_DEVICE_BAR
@@ -186,15 +202,27 @@
/* This define describes the maximum number of supported PCI Interfaces */
#define MV_DEVICE_MAX_CS 4
+/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */
+#define MV_CESA_VERSION 3
+#define MV_CESA_SRAM_SIZE (2 * 1024)
+
+#ifdef MV_USB
+#define MV_USB_MAX_PORTS 1
+#else
+#define MV_USB_MAX_PORTS 0
+#endif
+#define MV_USB3_MAX_HOST_PORTS 0
/* This define describes the maximum number of supported Ethernet ports */
/* TODO - verify all these numbers */
#define MV_ETH_VERSION 4 /* for Legacy mode */
#define MV_NETA_VERSION 1 /* for NETA mode */
-#define MV_ETH_MAX_PORTS 2
+#define MV_ETH_MAX_PORTS 4
#define MV_ETH_MAX_RXQ 8
#define MV_ETH_MAX_TXQ 8
#define MV_ETH_TX_CSUM_MAX_SIZE 9800
+#define MV_ETH_TX_CSUM_MIN_SIZE 2048
+#define MV_PNC_TCAM_LINES 1024 /* TCAM num of entries */
#define BOARD_ETH_SWITCH_PORT_NUM 2
/* New GMAC module is used */
@@ -235,6 +263,17 @@
I2C_UNIT_ID,
USB_UNIT_ID,
USB3_UNIT_ID,
+ NAND_UNIT_ID,
+ DEVBUS_UNIT_ID,
+ IDMA_UNIT_ID,
+ SATA_UNIT_ID,
+ TDM_UNIT_ID,
+ CESA_UNIT_ID,
+ AUDIO_UNIT_ID,
+ TS_UNIT_ID,
+ XPON_UNIT_ID,
+ BM_UNIT_ID,
+ PNC_UNIT_ID,
MAX_UNITS_ID
} MV_UNIT_ID;
@@ -288,9 +327,57 @@
DEV_BOOCS, /* 23 DEV_BOOCS */
USB_REGS, /* 24 USB Internal registers */
DRAGONITE, /* 25 Dragonite co-processor */
- MAX_TARGETS
+ MAX_TARGETS_MSYS
} MV_TARGET;
+enum _mvTarget_axp {
+ SDRAM_CS0_AXP, /*0 SDRAM chip select 0 */
+ SDRAM_CS1_AXP, /*1 SDRAM chip select 1 */
+ SDRAM_CS2_AXP, /*2 SDRAM chip select 2 */
+ SDRAM_CS3_AXP, /*3 SDRAM chip select 3 */
+ DEVICE_CS0_AXP, /*4 Device chip select 0 */
+ DEVICE_CS1_AXP, /*5 Device chip select 1 */
+ DEVICE_CS2_AXP, /*6 Device chip select 2 */
+ DEVICE_CS3_AXP, /*7 Device chip select 3 */
+ PEX0_MEM_AXP, /*8 PCI Express 0 Memory */
+ PEX0_IO_AXP, /*9 PCI Express 0 IO */
+ PEX1_MEM, /*10 PCI Express 1 Memory */
+ PEX1_IO, /*11 PCI Express 1 IO */
+ PEX2_MEM, /*12 PCI Express 2 Memory */
+ PEX2_IO, /*13 PCI Express 2 IO */
+ PEX3_MEM, /*14 PCI Express 3 Memory */
+ PEX3_IO, /*15 PCI Express 3 IO */
+ PEX4_MEM, /*16 PCI Express 4 Memory */
+ PEX4_IO, /*17 PCI Express 4 IO */
+ PEX5_MEM, /*18 PCI Express 5 Memory */
+ PEX5_IO, /*19 PCI Express 5 IO */
+ PEX6_MEM, /*20 PCI Express 6 Memory */
+ PEX6_IO, /*21 PCI Express 6 IO */
+ PEX7_MEM, /*22 PCI Express 7 Memory */
+ PEX7_IO, /*23 PCI Express 7 IO */
+ PEX8_MEM, /*24 PCI Express 8 Memory */
+ PEX8_IO, /*25 PCI Express 8 IO */
+ PEX9_MEM, /*26 PCI Express 9 Memory */
+ PEX9_IO, /*27 PCI Express 9 IO */
+ INTER_REGS_AXP, /*28 Internal registers */
+ DMA_UART_AXP, /*29 DMA based UART request */
+ SPI_CS0_AXP, /*30 SPI_CS0 */
+ SPI_CS1_AXP, /*31 SPI_CS1 */
+ SPI_CS2_AXP, /*32 SPI_CS2 */
+ SPI_CS3_AXP, /*33 SPI_CS3 */
+ SPI_CS4_AXP, /*34 SPI_CS4 */
+ SPI_CS5_AXP, /*35 SPI_CS5 */
+ SPI_CS6_AXP, /*36 SPI_CS6 */
+ SPI_CS7_AXP, /*37 SPI_CS7 */
+ BOOT_ROM_CS_AXP, /*38 BOOT_ROM_CS */
+ DEV_BOOCS_AXP, /*39 DEV_BOOCS */
+ PMU_SCRATCHPAD, /*40 PMU Scratchpad */
+ CRYPT0_ENG, /* 41 Crypto0 Engine */
+ CRYPT1_ENG, /* 42 Crypto1 Engine */
+ PNC_BM, /* 43 PNC + BM */
+ MAX_TARGETS_AXP
+};
+
#ifdef AURORA_IO_CACHE_COHERENCY
#define DRAM_CS0_ATTR 0x1E
#define DRAM_CS1_ATTR 0x1D
@@ -364,6 +451,100 @@
+#define TARGETS_DEF_ARRAY_AXP { \
+ {DRAM_CS0_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
+ {DRAM_CS1_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
+ {DRAM_CS2_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
+ {DRAM_CS3_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
+ {0x3E, DEV_TARGET_ID }, /* DEVICE_CS0 */ \
+ {0x3D, DEV_TARGET_ID }, /* DEVICE_CS1 */ \
+ {0x3B, DEV_TARGET_ID }, /* DEVICE_CS2 */ \
+ {0x37, DEV_TARGET_ID }, /* DEVICE_CS3 */ \
+ {0xE8, PEX0_TARGET_ID }, /* PEX0_LANE0_MEM */ \
+ {0xE0, PEX0_TARGET_ID }, /* PEX0_LANE0_IO */ \
+ {0xD8, PEX0_TARGET_ID }, /* PEX0_LANE1_MEM */ \
+ {0xD0, PEX0_TARGET_ID }, /* PEX0_LANE1_IO */ \
+ {0xB8, PEX0_TARGET_ID }, /* PEX0_LANE2_MEM */ \
+ {0xB0, PEX0_TARGET_ID }, /* PEX0_LANE2_IO */ \
+ {0x78, PEX0_TARGET_ID }, /* PEX0_LANE3_MEM */ \
+ {0x70, PEX0_TARGET_ID }, /* PEX0_LANE3_IO */ \
+ {0xE8, DFX_TARGET_ID }, /* PEX1_LANE0_MEM */ \
+ {0xE0, DFX_TARGET_ID }, /* PEX1_LANE0_IO */ \
+ {0xD8, DFX_TARGET_ID }, /* PEX1_LANE1_MEM */ \
+ {0xD0, DFX_TARGET_ID }, /* PEX1_LANE1_IO */ \
+ {0xB8, DFX_TARGET_ID }, /* PEX1_LANE2_MEM */ \
+ {0xB0, DFX_TARGET_ID }, /* PEX1_LANE2_IO */ \
+ {0x78, DFX_TARGET_ID }, /* PEX1_LANE3_MEM */ \
+ {0x70, DFX_TARGET_ID }, /* PEX1_LANE3_IO */ \
+ {0xF8, PEX0_TARGET_ID }, /* PEX2_LANE0_MEM */ \
+ {0xF0, PEX0_TARGET_ID }, /* PEX2_LANE0_IO */ \
+ {0xF8, DFX_TARGET_ID }, /* PEX3_LANE0_MEM */ \
+ {0xF0, DFX_TARGET_ID }, /* PEX3_LANE0_IO */ \
+ {0xFF, 0xFF }, /* INTER_REGS */ \
+ {0x01, DEV_TARGET_ID }, /* DMA_UART */ \
+ {0x1E, DEV_TARGET_ID }, /* SPI_CS0 */ \
+ {0x5E, DEV_TARGET_ID }, /* SPI_CS1 */ \
+ {0x9E, DEV_TARGET_ID }, /* SPI_CS2 */ \
+ {0xDE, DEV_TARGET_ID }, /* SPI_CS3 */ \
+ {0x1F, DEV_TARGET_ID }, /* SPI_CS4 */ \
+ {0x5F, DEV_TARGET_ID }, /* SPI_CS5 */ \
+ {0x9F, DEV_TARGET_ID }, /* SPI_CS6 */ \
+ {0xDF, DEV_TARGET_ID }, /* SPI_CS7 */ \
+ {0x1D, DEV_TARGET_ID }, /* Main Boot device */ \
+ {0x2F, DEV_TARGET_ID }, /* Secondary Boot device, */ \
+ {0x2D, DEV_TARGET_ID }, /* PMU_SCRATCHPAD */ \
+ {0x09, CRYPT_TARGET_ID }, /* CRYPT_ENG0 */ \
+ {0x05, CRYPT_TARGET_ID }, /* CRYPT_ENG1 */ \
+ {0x00, PNC_BM_TARGET_ID }, /* PNC_BM */ \
+}
+
+#define TARGETS_NAME_ARRAY_AXP { \
+ "SDRAM_CS0", /* SDRAM_CS0 */ \
+ "SDRAM_CS1", /* SDRAM_CS1 */ \
+ "SDRAM_CS2", /* SDRAM_CS1 */ \
+ "SDRAM_CS3", /* SDRAM_CS1 */ \
+ "DEVICE_CS0", /* DEVICE_CS0 */ \
+ "DEVICE_CS1", /* DEVICE_CS1 */ \
+ "DEVICE_CS2", /* DEVICE_CS2 */ \
+ "DEVICE_CS3", /* DEVICE_CS3 */ \
+ "PEX0_MEM", /* PEX0_MEM */ \
+ "PEX0_IO", /* PEX0_IO */ \
+ "PEX1_MEM", /* PEX1_MEM */ \
+ "PEX1_IO", /* PEX1_IO */ \
+ "PEX2_MEM", /* PEX2_MEM */ \
+ "PEX2_IO", /* PEX2_IO */ \
+ "PEX3_MEM", /* PEX3_MEM */ \
+ "PEX3_IO", /* PEX3_IO */ \
+ "PEX4_MEM", /* PEX4_MEM */ \
+ "PEX4_IO", /* PEX4_IO */ \
+ "PEX5_MEM", /* PEX5_MEM */ \
+ "PEX5_IO", /* PEX5_IO */ \
+ "PEX6_MEM", /* PEX6_MEM */ \
+ "PEX6_IO", /* PEX6_IO */ \
+ "PEX7_MEM", /* PEX7_MEM */ \
+ "PEX7_IO", /* PEX7_IO */ \
+ "PEX8_MEM", /* PEX8_MEM */ \
+ "PEX8_IO", /* PEX8_IO */ \
+ "PEX9_MEM", /* PEX9_MEM */ \
+ "PEX9_IO", /* PEX9_IO */ \
+ "INTER_REGS", /* INTER_REGS */ \
+ "DMA_UART", /* DMA_UART */ \
+ "SPI_CS0", /* SPI_CS0 */ \
+ "SPI_CS1", /* SPI_CS1 */ \
+ "SPI_CS2", /* SPI_CS2 */ \
+ "SPI_CS3", /* SPI_CS3 */ \
+ "SPI_CS4", /* SPI_CS4 */ \
+ "SPI_CS5", /* SPI_CS5 */ \
+ "SPI_CS6", /* SPI_CS6 */ \
+ "SPI_CS7", /* SPI_CS7 */ \
+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \
+ "DEV_BOOTCS", /* DEV_BOOCS */ \
+ "PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */ \
+ "CRYPT1_ENG", /* CRYPT1_ENG */ \
+ "CRYPT2_ENG", /* CRYPT2_ENG */ \
+ "PNC_BM" /* PNC_BM */ \
+}
+
#endif /* MV_ASMLANGUAGE */
#ifdef __cplusplus
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.c
index d71df4e..de6c496 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.c
@@ -42,12 +42,12 @@
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.h
index 8b8994c..9ac8134 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvSemaphore.h
@@ -42,12 +42,12 @@
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
index e4608ab..0229d22 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvAhbToMbus.c
@@ -255,7 +255,10 @@
if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) {
pAddrDecWin->addrWin.size = INTER_REGS_SIZE;
- pAddrDecWin->target = INTER_REGS;
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ pAddrDecWin->target = (MV_U8)INTER_REGS_AXP;
+ else
+ pAddrDecWin->target = INTER_REGS;
pAddrDecWin->enable = MV_TRUE;
return MV_OK;
@@ -301,7 +304,7 @@
return 0xffffffff;
}
- if (INTER_REGS == target)
+ if (INTER_REGS == target || (MV_U8)INTER_REGS_AXP == target)
return MV_AHB_TO_MBUS_INTREG_WIN;
for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) {
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
index 58db349..b5d2632 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIf.c
@@ -156,7 +156,7 @@
/* Set IO Bypass base address and size according to the cpuAddrWinMap */
for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) {
if ((MV_TARGET_IS_DRAM(target)) || (DIS == cpuAddrWinMap[target].enable) ||
- (target == INTER_REGS))
+ (target == INTER_REGS) || (target == (MV_U8)INTER_REGS_AXP))
continue;
if (cpuAddrWinMap[target].addrWin.baseLow == 0)
continue;
@@ -190,7 +190,8 @@
/* First disable all CPU target windows */
for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) {
- if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS))
+ if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS) ||
+ (target == (MV_U8)INTER_REGS_AXP))
continue;
#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA)
@@ -720,9 +721,23 @@
MV_U32 winNum;
/* Check parameters */
- if (!MV_TARGET_IS_PEX0(pexTarget)) {
- mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget);
- return 0xffffffff;
+ if (mvCtrlPexMaxIfGet() > 1) {
+ if ((!MV_TARGET_IS_PEX0(pexTarget)) &&
+ (!MV_TARGET_IS_PEX1(pexTarget)) &&
+ (!MV_TARGET_IS_PEX2(pexTarget)) &&
+ (!MV_TARGET_IS_PEX3(pexTarget)) &&
+ (!MV_TARGET_IS_PEX4(pexTarget)) &&
+ (!MV_TARGET_IS_PEX5(pexTarget)) &&
+ (!MV_TARGET_IS_PEX6(pexTarget)) &&
+ (!MV_TARGET_IS_PEX7(pexTarget)) &&
+ (!MV_TARGET_IS_PEX8(pexTarget)) &&
+ (!MV_TARGET_IS_PEX9(pexTarget))) {
+ mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget);
+ return 0xffffffff;
+ }
+ } else if (!MV_TARGET_IS_PEX0(pexTarget)) {
+ mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget);
+ return 0xffffffff;
}
/* get the Window number associated with this target */
@@ -940,3 +955,32 @@
return MV_OK;
}
+
+/*******************************************************************************
+* mvCpuIfMbusWindowSet
+*
+* DESCRIPTION:
+* Set Mbus Bridge Window register
+*
+* INPUT:
+* Windows Base Address
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvCpuIfMbusWindowSet(MV_U32 base, MV_U32 size)
+{
+ MV_U32 reg;
+
+ MV_REG_WRITE(MBUS_BRIDGE_WIN_BASE_REG, base);
+ /* Align window size to 64KB */
+ size = ((size / _64K) - 1) << BRIDGWCR_SIZE_OFFS;
+ reg = MV_REG_READ(MBUS_BRIDGE_WIN_CTRL_REG);
+ reg &= ~BRIDGWCR_SIZE_MASK;
+ reg |= (size & BRIDGWCR_SIZE_MASK);
+ MV_REG_WRITE(MBUS_BRIDGE_WIN_CTRL_REG, reg);
+}
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIfRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIfRegs.h
index 0c6c14f..f795ecf 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIfRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/sys/mvCpuIfRegs.h
@@ -348,6 +348,17 @@
#define CPU_ARM_TO_HOST_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x70)
#define CPU_ARM_TO_HOST_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x74)
+/*******************************************/
+/* CLOCK Complex Registers Map - AXP only */
+/*******************************************/
+
+#define CPU_DIV_CLK_CTRL0_REG (MV_CLK_CMPLX_REGS_OFFSET)
+#define CPU_DIV_CLK_CTRL0_RESET_MASK_OFFS 8
+#define CPU_DIV_CLK_CTRL2_RATIO_FULL0_REG (MV_CLK_CMPLX_REGS_OFFSET + 0x8)
+#define CPU_DIV_CLK_CTRL2_NB_RATIO_OFFS 16
+#define CPU_DIV_CLK_CTRL3_RATIO_FULL1_REG (MV_CLK_CMPLX_REGS_OFFSET + 0xC)
+#define CPU_DIV_CLK_CTRL3_CPU_RATIO_OFFS 8
+
/* CPU control register map */
/* Set bits means value is about to change according to new value */
#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK)
diff --git a/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h b/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
index 413abd8..69bd8aa 100644
--- a/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
+++ b/board/mv_ebu/msys/msys_family/device/mvDeviceRegs.h
@@ -76,6 +76,8 @@
switch (num) {
case (DEV_BOOCS):
return MV_DEV_BUS_REGS_OFFSET + 0x00;
+ case (DEV_BOOCS_AXP):
+ return MV_DEV_BUS_REGS_OFFSET + 0x00;
case (DEVICE_CS0):
return MV_DEV_BUS_REGS_OFFSET + 0x08;
case (DEVICE_CS1):
diff --git a/board/mv_ebu/msys/mvSysHwConfig.h b/board/mv_ebu/msys/mvSysHwConfig.h
index e7d490e..aaf184e 100644
--- a/board/mv_ebu/msys/mvSysHwConfig.h
+++ b/board/mv_ebu/msys/mvSysHwConfig.h
@@ -135,6 +135,7 @@
#define SWITCH_REGS_BASE 0xA8000000
#define SWITCH_REGS_SIZE _64M
#define SWITCH_REGS_VIRT_BASE SWITCH_REGS_BASE
+#define SWITCH_WIN_ID 5
/************************************************************/
/* Device: CS0 - NOR or NAND, CS1 - SPI, CS2 - Boot ROM, CS3 - Boot device */
/* NOR and NAND are configure to CS0 but it is posible to load
@@ -252,7 +253,7 @@
{ { PEX0_IO_BASE, 0, PEX0_IO_SIZE }, TBL_UNUSED, DIS }, /* 9 PEX0_IO */ \
{ { INTER_REGS_BASE, 0, INTER_REGS_SIZE }, MV_AHB_TO_MBUS_INTREG_WIN, EN }, /* 10 INTER_REGS */ \
{ { DFX_REGS_BASE, 0, DFX_REGS_SIZE }, 1, EN }, /* 11 DFX_REGS */ \
- { { SWITCH_REGS_BASE, 0, SWITCH_REGS_SIZE }, 5, EN }, /* 12 SWITCH */ \
+ { { SWITCH_REGS_BASE, 0, SWITCH_REGS_SIZE }, SWITCH_WIN_ID, EN }, /* 12 SWITCH */ \
{ { TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS }, /* 13 DMA_UART */ \
{ { SPI_CS_BASE, 0, SPI_CS_SIZE }, 8, EN }, /* 14 SPI_CS0 */ \
{ { TBL_UNUSED, 0, TBL_UNUSED }, TBL_UNUSED, DIS }, /* 15 SPI_CS1 */ \
diff --git a/boards.cfg b/boards.cfg
index f497b89..4a01430 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -54,6 +54,7 @@
armada_38x arm armv7 a38x mv_ebu mvca9 armada_38x:ARMADA_38X
armada_38x_customer0 arm armv7 a38x mv_ebu mvca9 armada_38x:CUSTOMER_BOARD_0,ARMADA_38X
armada_38x_customer1 arm armv7 a38x mv_ebu mvca9 armada_38x:CUSTOMER_BOARD_1,ARMADA_38X
+armada_38x_clearfog arm armv7 a38x mv_ebu mvca9 armada_38x:CLEARFOG_BOARD,ARMADA_38X
armada_38x_gfch100 arm armv7 a38x mv_ebu mvca9 armada_38x:GFCH100,ARMADA_38X
armada_39x arm armv7 a38x mv_ebu mvca9 armada_38x:ARMADA_39X
armada_39x_customer0 arm armv7 a38x mv_ebu mvca9 armada_38x:CUSTOMER_BOARD_0,ARMADA_39X
diff --git a/build.pl b/build.pl
index 17b9968..d786ee1 100755
--- a/build.pl
+++ b/build.pl
@@ -13,14 +13,14 @@
print "Options:\n";
print "\t-f\tBoot device. Accepts spi, nor, nand, mmc\n";
print "\t-b\tBoard type. Accepts:\tavanta_lp , avanta_lp_customer0 , avanta_lp_customer1\n";
- print "\t\t\t\t\tarmada_38x, armada_38x_customer0, armada_38x_customer1\n";
+ print "\t\t\t\t\tarmada_38x, armada_38x_clearfog, armada_38x_customer0, armada_38x_customer1\n";
print "\t\t\t\t\tarmada_39x, armada_39x_customer0, armada_39x_customer1\n";
print "\t\t\t\t\tarmada_375, armada_375_customer0, armada_375_customer1\n";
print "\t\t\t\t\tbobcat2_db, bobcat2_rd, bobcat2_customer0, bobcat2_customer1\n";
print "\t\t\t\t\tac3_db, ac3_rd, ac3_customer0, ac3_customer1\n";
print "\t-o\tOutput dir/file. The image will be copied into this dir/file\n";
print "\t-e\tBig Endian. If not specified Little endian is used\n";
- print "\t-m\tDDR type(default: DDR3). Accepts: 3 for DDR3, 4 for DDR4\n";
+ print "\t-m\tDDR type(default: DDR4 for A39x, DDR3 for the rest). Accepts: 3 for DDR3, 4 for DDR4\n";
print "\t-i\tSupported interfaces, seperated by \":\" - Accepts [spi:nor:nand]\n";
print "\t-v\tSW version (in file name: u-boot-alp-X.X.X-spi.bin, else using date by default)\n";
print "\t\tinterfaces. Supports spi, nor, nand. the boot \n";
@@ -94,6 +94,7 @@
($opt_b eq "armada_375_customer0") or
($opt_b eq "armada_375_customer1") or
($opt_b eq "armada_38x") or
+ ($opt_b eq "armada_38x_clearfog") or
($opt_b eq "armada_38x_customer0") or
($opt_b eq "armada_38x_customer1") or
($opt_b eq "armada_38x_gfch100") or
@@ -111,19 +112,24 @@
($opt_b eq "ac3_customer1") )
{
$board = $opt_b;
+ $ddr3LibBuild="yes";
if( (substr $board,7 , 3) eq "370" ) {
$boardID="a370";
$targetBoard = substr $board, 11;
+ $ddr3LibBuild="no";
}
elsif ( (substr $board,7 , 2) eq "xp" ) {
$boardID="axp";
$targetBoard = substr $board, 10;
+ $ddr3LibBuild="no";
}
elsif ( (substr $board,7 , 2) eq "lp" ) {
$boardID="alp";
+ $ddr3LibBuild="no";
}
elsif ( (substr $board,7 , 3) eq "375" ) {
$boardID="a375";
+ $ddr3LibBuild="no";
}
elsif ( (substr $board,7 , 3) eq "38x" ) {
$boardID="a38x";
@@ -139,10 +145,12 @@
$boardID="msys-ac3";
$targetBoard = substr $board, 8;
}
- # if board string contains "customer", use customer define for binary_header
- if (index($board, "customer") != -1 || index($board, "gfch100") != -1){
- system("echo \"#define CONFIG_CUSTOMER_BOARD_SUPPORT 1\" >> include/config.h");
+ # if board string contains "customer" (Or A38x-SolidRun Clear fog board), use customer define for binary_header
+ if ((index($board, "customer") != -1) or (index($board, "clearfog") != -1)
+ or (index($board, "gfch100") != -1)) {
+ system("echo \"#define CONFIG_CUSTOMER_BOARD_SUPPORT 1\" >> include/config.h");
}
+
}
else
{
@@ -344,6 +352,19 @@
print "\n";
}
+if($opt_d eq 4)
+{
+ system("echo \"DDR4SUBLIB = yes\" >> include/config.mk");
+ print "** Rebuild DDR4 sublib **\n";
+ $opt_d = 2;
+}
+
+#by default -d 2 will be enabled for new TIP SoCs
+if(($ddr3LibBuild eq "yes") && !((substr $board,7 , 3) eq "39x"))
+{
+ $opt_d = 2;
+}
+
if(defined $opt_d)
{
system("echo \"DDR3LIB = $opt_d\" >> include/config.mk");
@@ -439,6 +460,7 @@
print "\n**** [Creating Image]\t*****\n\n";
$failUart = system("./tools/marvell/doimage -T uart -D 0 -E 0 -G ./tools/marvell/bin_hdr/bin_hdr.uart.bin u-boot.bin u-boot-$boardID-$opt_v-$flash_name$targetBoard-uart.bin");
+$failDebug = system("./tools/marvell/doimage -T uart -D 0 -E 0 -H 3 -G ./tools/marvell/bin_hdr/bin_hdr.debug.bin u-boot.bin u-boot-$boardID-$opt_v-$flash_name$targetBoard-debug.bin");
$fail = system("./tools/marvell/doimage -T $img_type -D 0x0 -E 0x0 $img_opts $rsa_opts $id_opts $extra_opt -G ./tools/marvell/bin_hdr/$bin_hdr_n u-boot.bin u-boot-$boardID-$opt_v-$flash_name$targetBoard.bin");
if($fail){
@@ -449,6 +471,10 @@
print "\n *** Error: Doimage for uart image failed\n\n";
exit 1;
}
+if($failDebug){
+ print "\n *** Error: Doimage for debug image failed\n\n";
+ exit 1;
+}
if(defined $opt_o)
{
diff --git a/common/cmd_disk.c b/common/cmd_disk.c
index ee4e215..8c4d0bd 100644
--- a/common/cmd_disk.c
+++ b/common/cmd_disk.c
@@ -67,7 +67,8 @@
"Name: %.32s Type: %.32s\n", intf, dev, part, info.name,
info.type);
- debug("First Block: %ld, # of blocks: %ld, Block Size: %ld\n",
+ debug("First Block: " LBAFU ", # of blocks: " LBAFU
+ ", Block Size: %ld\n",
info.start, info.size, info.blksz);
if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) {
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 4380794..6b55ca8 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1576,6 +1576,8 @@
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char i2c_help_text[] =
+ "address.[.0, .2] = Address length [byte, 2byte]"
+ "xx.[.b, .w, .l] = Returned Data length [byte, 2byte, 4byte]"
#if defined(CONFIG_I2C_MUX)
"bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
#endif /* CONFIG_I2C_MUX */
@@ -1588,9 +1590,9 @@
#endif /* CONFIG_I2C_EDID */
"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
- "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
- "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
- "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
+ "i2c mm[.b, .w, .l] chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
+ "i2c nm[.b, .w, .l] chip address[.0, .1, .2] - write to I2C device (constant address)\n"
+ "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill constant value)\n"
"i2c probe [address] - test for and show device(s) on the I2C bus\n"
"i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
"i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 642ed4b..1826e1e 100755
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c
@@ -866,6 +866,19 @@
/* verify if we have a valid device specified */
if ((id = id_find_by_mtd_id(mtd_id, mtd_id_len - 1)) == NULL) {
printf("invalid mtd device '%.*s'\n", mtd_id_len - 1, mtd_id);
+ /* let 'p' point to the start of the next device in order
+ * to try to parse it in the next iteration
+ * example: mtdparts=spi_flash:4m(boot),-(spi-rootfs);armada-nand:8m...
+ * when failing to recognize 'spi_flash', let 'p' point to the start
+ * of 'armada-nand'
+ * */
+ p = strchr(p, ';');
+ if (ret) {
+ if (p)
+ *ret = ++p;
+ else
+ *ret = NULL;
+ }
return 1;
}
@@ -928,7 +941,12 @@
if (*p == ';') {
if (ret)
*ret = ++p;
- } else if (*p == '\0') {
+ } else if (*p == '\0' || (*p == '\'' && *(p+1) == '\0')) {
+ /* ignore ' if it is the last character, in case 'mtdparts' is wrapped
+ * with quotation marks.
+ * example: mtdparts='mtdparts=spi_flash:4m(boot),-(spi-rootfs);armada-nand:8m...'
+ * ignore the last character (quotation mark '), and don't print error message on it
+ * */
if (ret)
*ret = p;
} else {
@@ -1551,6 +1569,14 @@
/* re-read 'mtdparts' variable, mtd_devices_init may be updating env */
p = getenv("mtdparts");
+ /* ignore ' if it is the first character, in case 'mtdparts' is wrapped
+ * with quotation marks.
+ * example: mtdparts='mtdparts=spi_flash:4m(boot),-(spi-rootfs);armada-nand:8m...'
+ * ignore the first character (quotation mark '), and don't print error
+ * */
+ if (*p == '\'')
+ p++;
+
if (strncmp(p, "mtdparts=", 9) != 0) {
printf("mtdparts variable doesn't start with 'mtdparts='\n");
return err;
@@ -1559,8 +1585,12 @@
while (p && (*p != '\0')) {
err = 1;
- if ((device_parse(p, &p, &dev) != 0) || (!dev))
- break;
+ if ((device_parse(p, &p, &dev) != 0) || (!dev)) {
+ /* try to parse next device if the current device fails
+ * 'p' will point to the next device */
+ err = 0;
+ continue;
+ }
debug("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
dev->id->num, dev->id->mtd_id);
@@ -1619,8 +1649,17 @@
ret = 1;
/* parse 'nor'|'nand'|'onenand'<dev-num> */
- if (mtd_id_parse(p, &p, &type, &num) != 0)
- break;
+ if (mtd_id_parse(p, &p, &type, &num) != 0) {
+ /* let 'p' point to the next <idmap>, when the current <idmap> parsing fails.
+ * example: mtdids=spi0=spi_flash,nand0=armada-nand
+ * when failing to parse spi0, let 'p' point to the start of nand0=armada-nand
+ */
+ p = strchr(p, ',');
+ if (p)
+ p++;
+ ret = 0;
+ continue;
+ }
if (*p != '=') {
printf("mtdids: incorrect <dev-num>\n");
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index 62f2042..977bde9 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -112,6 +112,14 @@
lbaint_t capacity;
unsigned long blksz;
ccb* pccb=(ccb *)&tempccb;
+ static int scsi_detected = 0;
+
+ if (scsi_detected) {
+ printf("** scsi detection can run only once - please");
+ printf(" reset board before running detection again **\n");
+ return;
+ }
+ scsi_detected = 1;
if(mode==1) {
printf("scanning bus for devices...\n");
@@ -517,7 +525,7 @@
__func__, start, smallblks, buf_addr);
if (scsi_exec(pccb) != TRUE) {
scsi_print_error(pccb);
- blkcnt -= blks;
+ blkcnt -= (blks + smallblks);
break;
}
buf_addr += pccb->datalen;
diff --git a/disk/part_efi.c b/disk/part_efi.c
old mode 100755
new mode 100644
index 112b438..6fb5d46
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -206,8 +206,8 @@
uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid);
#endif
- debug("%s: start 0x%lX, size 0x%lX, name %s", __func__,
- info->start, info->size, info->name);
+ debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__,
+ info->start, info->size, info->name);
/* Remember to free pte */
free(gpt_pte);
@@ -442,7 +442,7 @@
gpt_e[i].partition_name[k] =
(efi_char16_t)(partitions[i].name[k]);
- debug("%s: name: %s offset[%d]: 0x%x size[%d]: 0x%lx\n",
+ debug("%s: name: %s offset[%d]: 0x%x size[%d]: 0x" LBAF "\n",
__func__, partitions[i].name, i,
offset, i, partitions[i].size);
}
diff --git a/disk/part_iso.c b/disk/part_iso.c
index baeced7..49bff15 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -261,8 +261,8 @@
printf("Part Start Sect x Size Type\n");
i=0;
do {
- printf (" %2d %8ld %8ld %6ld %.32s\n",
- i, info.start, info.size, info.blksz, info.type);
+ printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n",
+ i, info.start, info.size, info.blksz, info.type);
i++;
} while (get_partition_info_iso_verb(dev_desc,i,&info,0)!=-1);
}
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index d9767b3..04c1729 100755
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -503,6 +503,20 @@
pp->cmd_slot->tbl_addr_hi = 0;
}
+static int wait_spinup(volatile u8 *port_mmio)
+{
+ ulong start;
+ u32 tf_data;
+
+ start = get_timer(0);
+ do {
+ tf_data = readl(port_mmio + PORT_TFDATA);
+ if (!(tf_data & ATA_BUSY))
+ return 0;
+ } while (get_timer(start) < WAIT_MS_SPINUP);
+
+ return -ETIMEDOUT;
+}
#ifdef CONFIG_AHCI_SETFEATURES_XFER
static void ahci_set_feature(struct ahci_probe_ent *probe_ent, u8 port)
@@ -595,7 +609,11 @@
debug("Exit start port %d\n", port);
- return 0;
+ /*
+ * Make sure interface is not busy based on error and status
+ * information from task file data register before proceeding
+ */
+ return wait_spinup(port_mmio);
}
@@ -1065,6 +1083,14 @@
fis[1] = 1 << 7; /* Command FIS. */
fis[2] = ATA_CMD_FLUSH_EXT;
+ /* Clear IRQ status register
+ * before issuing the flush command to the controller, make
+ * sure IRQ status register is flushed (in case a previous
+ * transaction ended, without clearing it). ** Flush command
+ * will not start/complete unless clearing IRQ **
+ * */
+ writel_with_flush(0xffffffff, port_mmio + PORT_IRQ_STAT);
+
memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
ahci_fill_cmd_slot(pp, cmd_fis_len);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 3bab739..7227bfd 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -149,8 +149,8 @@
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
unsigned int time = 0, start_addr = 0;
- unsigned int retry = 10000;
int mmc_dev = mmc->block_dev.dev;
+ unsigned start = get_timer(0);
/* Timeout unit - ms */
static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
@@ -236,6 +236,7 @@
flush_cache(start_addr, trans_bytes);
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
+ start = get_timer(0);
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR)
@@ -247,11 +248,10 @@
cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
udelay(5);
#endif
- if (--retry == 0)
- break;
- } while ((stat & mask) != mask);
+ } while (((stat & mask) != mask) &&
+ (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT));
- if (retry == 0) {
+ if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) {
if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
return 0;
else {
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index d79bc1c..ed40ab6 100755
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -121,7 +121,7 @@
board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
#endif
}
-#if defined(CONFIG_ENV_IS_IN_NAND)
+
int nand_get_env_offs(void)
{
size_t offset = 0;
@@ -145,7 +145,7 @@
offset = (i + 1) * blocksize;
}
i++;
- if (sum >= CONFIG_ENV_RANGE)
+ if (sum >= CONFIG_ENV_RANGE_NAND)
break;
}
@@ -166,11 +166,10 @@
size_t env_size = 0;
size_t blocksize = nand_info[0].erasesize;
- if (blocksize < CONFIG_ENV_SIZE) {
- env_size = ((CONFIG_ENV_SIZE + (blocksize - 1)) & (~(blocksize-1)));
+ if (blocksize < CONFIG_ENV_SIZE_NAND) {
+ env_size = ((CONFIG_ENV_SIZE_NAND + (blocksize - 1)) & (~(blocksize-1)));
return env_size;
} else
return blocksize;
}
-#endif
diff --git a/drivers/net/sk98lin/h/skaddr.h b/drivers/net/sk98lin/h/skaddr.h
index bc4fcdb..e2163dd 100644
--- a/drivers/net/sk98lin/h/skaddr.h
+++ b/drivers/net/sk98lin/h/skaddr.h
@@ -156,6 +156,7 @@
typedef struct s_MacAddr {
SK_U8 a[SK_MAC_ADDR_LEN];
+ SK_U16 DummyAlignWord; /* Dummy entry for 32bit alignment only. */
} SK_MAC_ADDR;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 5981200..c55300d 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -119,7 +119,7 @@
},
};
-static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
+static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_HOST_COUNT];
/**
* Waits for as per specified amount of time
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index 464a67d..dcbb17f 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -41,7 +41,7 @@
#include <ext4fs.h>
#include <ext_common.h>
-unsigned long part_offset;
+lbaint_t part_offset;
static block_dev_desc_t *ext4fs_block_dev_desc;
static disk_partition_t *part_info;
@@ -55,7 +55,7 @@
get_fs()->dev_desc = rbdd;
}
-int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf)
+int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf)
{
ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE);
unsigned block_len;
@@ -64,7 +64,7 @@
if ((sector < 0)
|| ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
part_info->size)) {
- printf("%s read outside partition %d\n", __func__, sector);
+ printf("%s read outside partition " LBAFU "\n", __func__, sector);
return 0;
}
@@ -72,7 +72,7 @@
sector += byte_offset >> SECTOR_BITS;
byte_offset &= SECTOR_SIZE - 1;
- debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
+ debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
if (ext4fs_block_dev_desc == NULL) {
printf("** Invalid Block Device Descriptor (NULL)\n");
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index bcc9dc8..c6185ca 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -84,7 +84,7 @@
if ((startblock + (size / SECTOR_SIZE)) >
(part_offset + fs->total_sect)) {
- printf("part_offset is %lu\n", part_offset);
+ printf("part_offset is " LBAFU "\n", part_offset);
printf("total_sector is %llu\n", fs->total_sect);
printf("error: overflow occurs\n");
return;
@@ -405,7 +405,7 @@
previous_blknr = root_blknr;
}
- status = ext4fs_devread(first_block_no_of_root
+ status = ext4fs_devread((lbaint_t)first_block_no_of_root
* fs->sect_perblk,
0, fs->blksz, root_first_block_buffer);
if (status == 0)
@@ -457,9 +457,9 @@
goto fail;
}
put_ext4(((uint64_t)
- (g_parent_inode->b.
+ ((uint64_t)g_parent_inode->b.
blocks.dir_blocks[direct_blk_idx] *
- fs->blksz)), zero_buffer, fs->blksz);
+ (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
g_parent_inode->size =
g_parent_inode->size + fs->blksz;
g_parent_inode->blockcnt =
@@ -545,7 +545,7 @@
if (!block_buffer)
goto fail;
- status = ext4fs_devread(blknr * fs->sect_perblk,
+ status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
0, fs->blksz, (char *)block_buffer);
if (status == 0)
goto fail;
@@ -783,7 +783,7 @@
if (!root_first_block_buffer)
return -ENOMEM;
root_first_block_addr = root_first_block_buffer;
- status = ext4fs_devread(first_block_no_of_root *
+ status = ext4fs_devread((lbaint_t)first_block_no_of_root *
fs->sect_perblk, 0,
fs->blksz, root_first_block_buffer);
if (status == 0)
@@ -876,8 +876,8 @@
for (i = 0; i < fs->no_blkgrp; i++) {
if (bgd[i].free_blocks) {
if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
- put_ext4(((uint64_t) (bgd[i].block_id *
- fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id *
+ (uint64_t)fs->blksz)),
zero_buffer, fs->blksz);
bgd[i].bg_flags =
bgd[i].
@@ -895,7 +895,8 @@
fs->first_pass_bbmap++;
bgd[i].free_blocks--;
fs->sb->free_blocks--;
- status = ext4fs_devread(bgd[i].block_id *
+ status = ext4fs_devread((lbaint_t)
+ bgd[i].block_id *
fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
@@ -940,8 +941,8 @@
if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (bgd[bg_idx].block_id *
- fs->blksz)), zero_buffer, fs->blksz);
+ put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id *
+ (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
~EXT4_BG_BLOCK_UNINIT;
@@ -957,7 +958,7 @@
/* journal backup */
if (prev_bg_bitmap_index != bg_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[bg_idx].block_id
+ status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id
* fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
@@ -1007,8 +1008,8 @@
bgd[i].free_inodes;
if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
put_ext4(((uint64_t)
- (bgd[i].inode_id *
- fs->blksz)),
+ ((uint64_t)bgd[i].inode_id *
+ (uint64_t)fs->blksz)),
zero_buffer, fs->blksz);
bgd[i].bg_flags = bgd[i].bg_flags &
~EXT4_BG_INODE_UNINIT;
@@ -1026,7 +1027,8 @@
bgd[i].free_inodes--;
bgd[i].bg_itable_unused--;
fs->sb->free_inodes--;
- status = ext4fs_devread(bgd[i].inode_id *
+ status = ext4fs_devread((lbaint_t)
+ bgd[i].inode_id *
fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
@@ -1047,8 +1049,8 @@
ibmap_idx = fs->curr_inode_no / inodes_per_grp;
if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id *
- fs->blksz)), zero_buffer,
+ put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id *
+ (uint64_t)fs->blksz)), zero_buffer,
fs->blksz);
bgd[ibmap_idx].bg_flags =
bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
@@ -1067,7 +1069,8 @@
/* journal backup */
if (prev_inode_bitmap_index != ibmap_idx) {
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[ibmap_idx].inode_id
+ status = ext4fs_devread((lbaint_t)
+ bgd[ibmap_idx].inode_id
* fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
@@ -1129,7 +1132,7 @@
(*no_blks_reqd)++;
debug("SIPB %ld: %u\n", si_blockno, *total_remaining_blocks);
- status = ext4fs_devread(si_blockno * fs->sect_perblk,
+ status = ext4fs_devread((lbaint_t)si_blockno * fs->sect_perblk,
0, fs->blksz, (char *)si_buffer);
memset(si_buffer, '\0', fs->blksz);
if (status == 0)
@@ -1152,7 +1155,7 @@
}
/* write the block to disk */
- put_ext4(((uint64_t) (si_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)),
si_start_addr, fs->blksz);
file_inode->b.blocks.indir_block = si_blockno;
}
@@ -1193,7 +1196,7 @@
debug("DIPB %ld: %u\n", di_blockno_parent,
*total_remaining_blocks);
- status = ext4fs_devread(di_blockno_parent *
+ status = ext4fs_devread((lbaint_t)di_blockno_parent *
fs->sect_perblk, 0,
fs->blksz, (char *)di_parent_buffer);
@@ -1224,7 +1227,7 @@
debug("DICB %ld: %u\n", di_blockno_child,
*total_remaining_blocks);
- status = ext4fs_devread(di_blockno_child *
+ status = ext4fs_devread((lbaint_t)di_blockno_child *
fs->sect_perblk, 0,
fs->blksz,
(char *)di_child_buff);
@@ -1251,7 +1254,7 @@
break;
}
/* write the block table */
- put_ext4(((uint64_t) (di_blockno_child * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)di_blockno_child * (uint64_t)fs->blksz)),
di_child_buff_start, fs->blksz);
free(di_child_buff_start);
di_child_buff_start = NULL;
@@ -1259,7 +1262,7 @@
if (*total_remaining_blocks == 0)
break;
}
- put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)),
di_block_start_addr, fs->blksz);
file_inode->b.blocks.double_indir_block = di_blockno_parent;
}
@@ -1357,8 +1360,8 @@
break;
}
/* write the child block */
- put_ext4(((uint64_t) (ti_child_blockno *
- fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_child_blockno *
+ (uint64_t)fs->blksz)),
ti_cbuff_start_addr, fs->blksz);
free(ti_cbuff_start_addr);
@@ -1366,7 +1369,7 @@
break;
}
/* write the parent block */
- put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_parent_blockno * (uint64_t)fs->blksz)),
ti_pbuff_start_addr, fs->blksz);
free(ti_pbuff_start_addr);
@@ -1374,7 +1377,7 @@
break;
}
/* write the grand parent block */
- put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)),
+ put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
}
@@ -1447,7 +1450,8 @@
block = le32_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
- if (ext4fs_devread(block << log2_blksz, 0, fs->blksz, buf))
+ if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, fs->blksz,
+ buf))
ext_block = (struct ext4_extent_header *)buf;
else
return 0;
@@ -1469,7 +1473,7 @@
debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
group, blkno, blkoff);
- return ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data),
+ return ext4fs_devread((lbaint_t)blkno << LOG2_EXT2_BLOCK_SIZE(data),
blkoff, sizeof(struct ext2_block_group),
(char *)blkgrp);
}
@@ -1495,7 +1499,7 @@
(ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (ino % inodes_per_block) * fs->inodesz;
/* Read the inode. */
- status = ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data), blkoff,
+ status = ext4fs_devread((lbaint_t)blkno << LOG2_EXT2_BLOCK_SIZE(data), blkoff,
sizeof(struct ext2_inode), (char *)inode);
if (status == 0)
return 0;
@@ -1592,7 +1596,7 @@
if ((__le32_to_cpu(inode->b.blocks.indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status =
- ext4fs_devread(__le32_to_cpu
+ ext4fs_devread((lbaint_t)__le32_to_cpu
(inode->b.blocks.
indir_block) << log2_blksz, 0,
blksz, (char *)ext4fs_indir1_block);
@@ -1641,7 +1645,7 @@
if ((__le32_to_cpu(inode->b.blocks.double_indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status =
- ext4fs_devread(__le32_to_cpu
+ ext4fs_devread((lbaint_t)__le32_to_cpu
(inode->b.blocks.
double_indir_block) << log2_blksz,
0, blksz,
@@ -1681,7 +1685,7 @@
}
if ((__le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) <<
log2_blksz) != ext4fs_indir2_blkno) {
- status = ext4fs_devread(__le32_to_cpu
+ status = ext4fs_devread((lbaint_t)__le32_to_cpu
(ext4fs_indir1_block
[rblock /
perblock]) << log2_blksz, 0,
@@ -1733,7 +1737,8 @@
if ((__le32_to_cpu(inode->b.blocks.triple_indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status = ext4fs_devread
- (__le32_to_cpu(inode->b.blocks.triple_indir_block)
+ ((lbaint_t)
+ __le32_to_cpu(inode->b.blocks.triple_indir_block)
<< log2_blksz, 0, blksz,
(char *)ext4fs_indir1_block);
if (status == 0) {
@@ -1773,7 +1778,7 @@
perblock_parent]) <<
log2_blksz)
!= ext4fs_indir2_blkno) {
- status = ext4fs_devread(__le32_to_cpu
+ status = ext4fs_devread((lbaint_t)__le32_to_cpu
(ext4fs_indir1_block
[rblock /
perblock_parent]) <<
@@ -1818,7 +1823,7 @@
perblock_child]) <<
log2_blksz) != ext4fs_indir3_blkno) {
status =
- ext4fs_devread(__le32_to_cpu
+ ext4fs_devread((lbaint_t)__le32_to_cpu
(ext4fs_indir2_block
[(rblock / perblock_child)
% (blksz / 4)]) << log2_blksz, 0,
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 9f01708..bafd793 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -360,7 +360,8 @@
(struct ext2_inode *)&inode_journal);
blknr = read_allocated_block((struct ext2_inode *)
&inode_journal, i);
- ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
p_jdb = (char *)temp_buff;
jdb = (struct journal_header_t *) temp_buff;
ofs = sizeof(struct journal_header_t);
@@ -384,9 +385,9 @@
continue;
}
blknr = read_allocated_block(&inode_journal, i);
- ext4fs_devread(blknr * fs->sect_perblk, 0,
+ ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
fs->blksz, metadata_buff);
- put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz),
+ put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz),
metadata_buff, (uint32_t) fs->blksz);
} while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
fail:
@@ -431,7 +432,8 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK);
- ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
if (fs->sb->feature_incompat & EXT3_FEATURE_INCOMPAT_RECOVER) {
@@ -455,7 +457,7 @@
while (1) {
blknr = read_allocated_block(&inode_journal, i);
memset(temp_buff1, '\0', fs->blksz);
- ext4fs_devread(blknr * fs->sect_perblk,
+ ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
0, fs->blksz, temp_buff1);
jdb = (struct journal_header_t *) temp_buff1;
@@ -547,7 +549,7 @@
blknr = read_allocated_block(&inode_journal,
EXT2_JOURNAL_SUPERBLOCK);
- put_ext4((uint64_t) (blknr * fs->blksz),
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
(struct journal_superblock_t *)temp_buff,
(uint32_t) fs->blksz);
ext4fs_free_revoke_blks();
@@ -576,7 +578,8 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
jsb_blknr = read_allocated_block(&inode_journal,
EXT2_JOURNAL_SUPERBLOCK);
- ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_DESCRIPTOR_BLOCK);
@@ -605,7 +608,7 @@
tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG);
memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag,
sizeof(struct ext3_journal_block_tag));
- put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
free(temp_buff);
free(buf);
@@ -623,10 +626,12 @@
if (!temp_buff)
return;
- ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+ &inode_journal);
jsb_blknr = read_allocated_block(&inode_journal,
EXT2_JOURNAL_SUPERBLOCK);
- ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_COMMIT_BLOCK);
@@ -638,7 +643,7 @@
return;
}
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