)]}' { "commit": "0920d472195935af640dfbb569c66dbfeb049ed1", "tree": "c02d98115ead6f219893783d05ee533b24279f89", "parents": [ "46a5534d942dcf8e6845c00c42c76cd60f5477c8" ], "author": { "name": "Margarita Granov", "email": "margra@marvell.com", "time": "Wed Sep 09 09:23:12 2015 +0300" }, "committer": { "name": "Greg Poist", "email": "poist@google.com", "time": "Thu Mar 24 11:59:54 2016 -0700" }, "message": "ddr3libv2: bobk: Add DQ to PAD mapping for Interface 0.\n\n\tSet DQ mapping values provided by design\n\tto run DDR WL supplementary on 933MHz\n\nChange-Id: I7b2e282350aacc26967c607866159b3276083f6c\nSigned-off-by: Margarita Granov \u003cmargra@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/23499\nTested-by: Star_Automation \u003cstar@marvell.com\u003e\nReviewed-by: Omri Itach \u003comrii@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24162\n", "tree_diff": [ { "type": "modify", "old_id": "2e035f3aaee520b278d6bbf4c20adb4c3c101b66", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c", "new_id": "34ecbb7296399dcccb19a7987536afe5a8888bb8", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c" } ] }