commit 0920d472195935af640dfbb569c66dbfeb049ed1
author Margarita Granov <margra@marvell.com> Wed Sep 09 09:23:12 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree c02d98115ead6f219893783d05ee533b24279f89
parent 46a5534d942dcf8e6845c00c42c76cd60f5477c8

ddr3libv2: bobk: Add DQ to PAD mapping for Interface 0.

	Set DQ mapping values provided by design
	to run DDR WL supplementary on 933MHz

Change-Id: I7b2e282350aacc26967c607866159b3276083f6c
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23499
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24162

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index 2e035f3..34ecbb7 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -264,12 +264,12 @@
 /* Bit mapping (for PBS) */
 GT_U32 bobKDQbitMap2Phypin[] =
 {
-/*#warning "DQ mapping is updated for Interface4 only!" !!!*/
+/*#warning "DQ mapping is updated for Interface 0 and 4 only!" !!!*/
 	    /* Interface 0 */
-	    0,0,0,0,0,0,0,0 , /* dq[0:7]   */
-	    0,0,0,0,0,0,0,0 , /* dq[8:15]  */
-	    0,0,0,0,0,0,0,0 , /* dq[16:23] */
-	    0,0,0,0,0,0,0,0 , /* dq[24:31] */
+        2,0,3,9,7,8,6,1 , /* dq[0:7]   */
+        3,2,1,6,0,9,7,8 , /* dq[8:15]  */
+        9,6,3,2,1,7,0,8 , /* dq[16:23] */
+        3,1,7,2,0,8,9,6 , /* dq[24:31] */
         0,0,0,0,0,0,0,0 , /* dq[ECC]   */
 
 	    /* Interface 1 */