/* Generated automatically by the program `genconstants'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CONSTANTS_H
#define GCC_INSN_CONSTANTS_H

#define UNSPEC_ARC_SIMD_VMOVAW 1080
#define UNSPEC_ARC_SIMD_VMR7W 1041
#define UNSPEC_ARC_SIMD_VASRRPWBi 1069
#define UNSPEC_ARC_SIMD_VMR3AW 1032
#define UNSPEC_ARC_SIMD_VVC1FT 1047
#define UNSPEC_ARC_SIMD_VMULFAW 1011
#define VUNSPEC_LR 25
#define UNSPEC_ARC_SIMD_VMAXW 1007
#define UNSPEC_DIRECT 17
#define UNSPEC_ARC_SIMD_VMRB 1042
#define UNSPEC_ARC_SIMD_VBSUBW 1057
#define UNSPEC_TLS_LD 22
#define UNSPEC_FFS 40
#define UNSPEC_TLS_GD 21
#define UNSPEC_ARC_SIMD_VH264F 1043
#define UNSPEC_ARC_SIMD_VMR3W 1033
#define UNSPEC_ARC_SIMD_VH264FW 1045
#define UNSPEC_ARC_SIMD_VMINAW 1008
#define ILINK1_REGNUM 29
#define UNSPEC_ARC_SIMD_VSR8i 1071
#define UNSPEC_ARC_SIMD_VH264FT 1044
#define UNSPEC_ARC_SIMD_VBMAXW 1051
#define UNSPEC_ARC_SIMD_VBADDW 1050
#define R10_REG 10
#define UNSPEC_ARC_SIMD_VMULAW 1010
#define UNSPEC_ARC_SIMD_VASRSRWi 1066
#define VUNSPEC_CORE_WRITE 24
#define UNSPEC_ARC_SIMD_VMOVW 1081
#define UNSPEC_ARC_SIMD_VMAXAW 1006
#define UNSPEC_ARC_SIMD_VNEW 1027
#define UNSPEC_ARC_SIMD_VASRRWi 1065
#define UNSPEC_ARC_SIMD_VDIFW 1005
#define UNSPEC_ARC_SIMD_VMR4W 1035
#define LP_COUNT 60
#define UNSPEC_ARC_SIMD_VENDREC 1108
#define UNSPEC_ARC_SIMD_VVC1F 1046
#define UNSPEC_ARC_SIMD_VEXCH1 1089
#define UNSPEC_ARC_SIMD_VEXCH2 1090
#define UNSPEC_ARC_SIMD_VEXCH4 1091
#define UNSPEC_ARC_SIMD_VMINW 1009
#define UNSPEC_ARC_SIMD_VMR7AW 1040
#define SP_REG 28
#define UNSPEC_ARC_SIMD_VMOVZW 1082
#define UNSPEC_ARC_SIMD_VASRPWBi 1068
#define ARCV2_ACC 58
#define UNSPEC_ARC_SIMD_VASRW 1060
#define UNSPEC_ARC_SIMD_VSUMMW 1016
#define VUNSPEC_CLRI 30
#define UNSPEC_ARC_SIMD_VBMULFW 1054
#define UNSPEC_TLS_IE 23
#define UNSPEC_ARC_SIMD_VMVAW 1075
#define UNSPEC_ARC_SIMD_VDIRUN 1100
#define LP_END 145
#define UNSPEC_ARC_SIMD_VMR5W 1037
#define UNSPEC_ARC_SIMD_VMR1AW 1028
#define UNSPEC_ARC_SIMD_VBMINW 1052
#define R1_REG 1
#define R12_REG 12
#define VUNSPEC_CORE_READ 23
#define UNSPEC_ARC_SIMD_VEQW 1024
#define UNSPEC_ARC_SIMD_VDOWR 1103
#define UNSPEC_TLS_OFF 24
#define VUNSPEC_SWI 22
#define VUNSPEC_SETI 31
#define UNSPEC_ARC_SIMD_VREC 1105
#define UNSPEC_ARC_SIMD_VABSAW 1085
#define UNSPEC_ARC_SIMD_VDIWR 1102
#define UNSPEC_ARC_SIMD_VLD32WH 1110
#define UNSPEC_ARC_SIMD_VLD32WL 1111
#define UNSPEC_ARC_SIMD_VOR 1021
#define UNSPEC_ARC_SIMD_VMR6AW 1038
#define UNSPEC_ARC_SIMD_VCAST 1200
#define UNSPEC_ARC_SIMD_VMR6W 1039
#define UNSPEC_ARC_SIMD_VD6TAPF 1078
#define UNSPEC_ARC_SIMD_VMVZW 1077
#define UNSPEC_ARC_SIMD_VSR8AWi 1070
#define UNSPEC_ARC_SIMD_VSUBAW 1014
#define UNSPEC_ARC_SIMD_VABSW 1086
#define UNSPEC_LP 19
#define UNSPEC_ARC_SIMD_VLTW 1026
#define VUNSPEC_SYNC 18
#define UNSPEC_ARC_SIMD_VUPBAW 1092
#define UNSPEC_ARC_SIMD_VUPBW 1093
#define UNSPEC_ARC_SIMD_VLEW 1025
#define UNSPEC_ARC_SIMD_VBICAW 1020
#define UNSPEC_ARC_SIMD_VINTI 1201
#define UNSPEC_MULU64 15
#define UNSPEC_MUL64 14
#define UNSPEC_ARC_SIMD_VUPSBW 1095
#define UNSPEC_PROF 18
#define VUNSPEC_UNIMP_S 28
#define UNSPEC_ARC_SIMD_VMVW 1076
#define UNSPEC_ARC_SIMD_VRECRUN 1107
#define R3_REG 3
#define UNSPEC_ARC_SIMD_VMR5AW 1036
#define UNSPEC_ARC_SIMD_VXORAW 1023
#define CC_REG 61
#define UNSPEC_ARC_SIMD_VBMULAW 1053
#define UNSPEC_ARC_SIMD_VASRWi 1067
#define VUNSPEC_TRAP_S 27
#define UNSPEC_ARC_SIMD_VADDW 1001
#define UNSPEC_ARC_SIMD_VDORUN 1101
#define UNSPEC_ARC_SIMD_VAND 1017
#define UNSPEC_ARC_SIMD_VXOR 1022
#define UNSPEC_SWAP 13
#define UNSPEC_ARC_SIMD_VUPSBAW 1094
#define RETURN_ADDR_REGNUM 31
#define UNSPEC_ARC_SIMD_VAVRB 1003
#define UNSPEC_ARC_SIMD_VAVB 1002
#define R0_REG 0
#define VUNSPEC_RTIE 17
#define VUNSPEC_FLAG 20
#define VUNSPEC_KFLAG 29
#define MUL64_OUT_REG 58
#define ILINK2_REGNUM 30
#define UNSPEC_ARC_SIMD_VMR4AW 1034
#define UNSPEC_ARC_SIMD_VANDAW 1018
#define UNSPEC_ARC_SIMD_VADDSUW 1087
#define UNSPEC_ARC_SIMD_VBRSUBW 1056
#define UNSPEC_ARC_SIMD_VMR1W 1029
#define UNSPEC_ARC_SIMD_VMR2AW 1030
#define VUNSPEC_BRK 19
#define UNSPEC_ARC_SIMD_VMULW 1013
#define UNSPEC_ARC_SIMD_VBIC 1019
#define UNSPEC_CASESI 20
#define UNSPEC_ARC_SIMD_VSUBW 1015
#define UNSPEC_ARC_SIMD_VSR8AW 1062
#define UNSPEC_FLS 41
#define UNSPEC_NORMW 12
#define UNSPEC_ARC_SIMD_VDIFAW 1004
#define UNSPEC_ARC_SIMD_VADDAW 1000
#define UNSPEC_NORM 11
#define UNSPEC_ARC_SIMD_VBMULW 1055
#define UNSPEC_ARC_SIMD_VSR8 1061
#define VUNSPEC_SLEEP 21
#define VUNSPEC_SR 26
#define LP_START 144
#define UNSPEC_ARC_SIMD_VRUN 1106
#define UNSPEC_ARC_SIMD_VMR2W 1031
#define UNSPEC_DIVAW 16
#define UNSPEC_ARC_SIMD_VSIGNW 1088
#define UNSPEC_ARC_SIMD_VMULFW 1012
#define R2_REG 2

enum unspec {
  DUMMY0 = 0,
  DUMMY1 = 1,
  DYMMY2 = 2,
  ARC_UNSPEC_PLT = 3,
  ARC_UNSPEC_GOT = 4,
  ARC_UNSPEC_GOTOFF = 5,
  ARC_UNSPEC_GOTOFFPC = 6,
  UNSPEC_ARC_NORM = 7,
  UNSPEC_ARC_NORMW = 8,
  UNSPEC_ARC_SWAP = 9,
  UNSPEC_ARC_DIVAW = 10,
  UNSPEC_ARC_DIRECT = 11,
  UNSPEC_ARC_LP = 12,
  UNSPEC_ARC_CASESI = 13,
  UNSPEC_ARC_FFS = 14,
  UNSPEC_ARC_FLS = 15,
  UNSPEC_ARC_MEMBAR = 16,
  UNSPEC_ARC_DMACH = 17,
  UNSPEC_ARC_DMACHU = 18,
  UNSPEC_ARC_DMACWH = 19,
  UNSPEC_ARC_DMACWHU = 20,
  UNSPEC_ARC_QMACH = 21,
  UNSPEC_ARC_QMACHU = 22,
  UNSPEC_ARC_QMPYH = 23,
  UNSPEC_ARC_QMPYHU = 24,
  UNSPEC_ARC_VMAC2H = 25,
  UNSPEC_ARC_VMAC2HU = 26,
  UNSPEC_ARC_VMPY2H = 27,
  UNSPEC_ARC_VMPY2HU = 28,
  VUNSPEC_ARC_RTIE = 29,
  VUNSPEC_ARC_SYNC = 30,
  VUNSPEC_ARC_BRK = 31,
  VUNSPEC_ARC_FLAG = 32,
  VUNSPEC_ARC_SLEEP = 33,
  VUNSPEC_ARC_SWI = 34,
  VUNSPEC_ARC_CORE_READ = 35,
  VUNSPEC_ARC_CORE_WRITE = 36,
  VUNSPEC_ARC_LR = 37,
  VUNSPEC_ARC_SR = 38,
  VUNSPEC_ARC_TRAP_S = 39,
  VUNSPEC_ARC_UNIMP_S = 40,
  VUNSPEC_ARC_KFLAG = 41,
  VUNSPEC_ARC_CLRI = 42,
  VUNSPEC_ARC_SETI = 43,
  VUNSPEC_ARC_NOP = 44,
  VUNSPEC_ARC_STACK_IRQ = 45,
  VUNSPEC_ARC_DEXCL = 46,
  VUNSPEC_ARC_DEXCL_NORES = 47,
  VUNSPEC_ARC_LR_HIGH = 48,
  VUNSPEC_ARC_EX = 49,
  VUNSPEC_ARC_CAS = 50,
  VUNSPEC_ARC_SC = 51,
  VUNSPEC_ARC_LL = 52
};
#define NUM_UNSPEC_VALUES 53
extern const char *const unspec_strings[];

#endif /* GCC_INSN_CONSTANTS_H */