diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index cea67db..66301b2 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -27,6 +27,9 @@
 static void (*ath79_ip2_handler)(void);
 static void (*ath79_ip3_handler)(void);
 
+static struct irq_chip ip2_chip;
+static struct irq_chip ip3_chip;
+
 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 	void __iomem *base = ath79_reset_base;
@@ -157,35 +160,83 @@
 
 static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 {
+        u32 status;
+
+        disable_irq_nosync(irq);
+
+        status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
+        status &= QCA953X_PCIE_WMAC_INT_PCIE_ALL | QCA953X_PCIE_WMAC_INT_WMAC_ALL;
+
+        if (status == 0) {
+                spurious_interrupt();
+                goto enable;
+        }
+
+        if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
+                /* TODO: flush DDR? */
+                generic_handle_irq(ATH79_IP2_IRQ(0));
+        }
+
+        if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
+                /* TODO: flsuh DDR? */
+                generic_handle_irq(ATH79_IP2_IRQ(1));
+        }
+
+enable:
+        enable_irq(irq);
+}
+
+static void qca953x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+{
 	u32 status;
 
 	disable_irq_nosync(irq);
 
 	status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
+	status &= QCA953X_PCIE_WMAC_INT_PCIE_RCX_ALL|
+			QCA953X_PCIE_WMAC_USB1|
+			QCA953X_PCIE_WMAC_USB2;
 
-	if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-		ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
-		generic_handle_irq(ATH79_IP2_IRQ(0));
-	} else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-		ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
-		generic_handle_irq(ATH79_IP2_IRQ(1));
-	} else {
+	if (status == 0) {
 		spurious_interrupt();
+		goto enable;
 	}
 
+	if (status & QCA953X_PCIE_WMAC_USB1) {
+		/* TODO: flush DDR? */
+		generic_handle_irq(ATH79_IP3_IRQ(0));
+	}
+
+	if (status & QCA953X_PCIE_WMAC_USB2) {
+		/* TODO: flsuh DDR? */
+		generic_handle_irq(ATH79_IP3_IRQ(1));
+	}
+
+	if (status & QCA953X_PCIE_WMAC_INT_PCIE_RCX_ALL) {
+		/* TODO: flush DDR? */
+		generic_handle_irq(ATH79_IP3_IRQ(2));
+	}
+
+enable:
 	enable_irq(irq);
 }
 
+
 static void qca953x_irq_init(void)
 {
 	int i;
 
 	for (i = ATH79_IP2_IRQ_BASE;
-	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-		irq_set_chip_and_handler(i, &dummy_irq_chip,
-					 handle_level_irq);
+		i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+		irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
 
 	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca953x_ip2_irq_dispatch);
+
+	for (i = ATH79_IP3_IRQ_BASE;
+		i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
+		irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
+
+	irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca953x_ip3_irq_dispatch);
 }
 
 static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
@@ -469,8 +520,35 @@
 	do_IRQ(ATH79_CPU_IRQ_USB);
 }
 
+static void ath79_ip2_disable(struct irq_data *data)
+{
+	disable_irq(ATH79_CPU_IRQ(2));
+}
+
+static void ath79_ip2_enable(struct irq_data *data)
+{
+	enable_irq(ATH79_CPU_IRQ(2));
+}
+
+static void ath79_ip3_disable(struct irq_data *data)
+{
+	disable_irq(ATH79_CPU_IRQ(3));
+}
+
+static void ath79_ip3_enable(struct irq_data *data)
+{
+	enable_irq(ATH79_CPU_IRQ(3));
+}
+
 void __init arch_init_irq(void)
 {
+	ip2_chip = dummy_irq_chip;
+	ip3_chip = dummy_irq_chip;
+	ip2_chip.irq_disable = ath79_ip2_disable;
+	ip2_chip.irq_enable = ath79_ip2_enable;
+	ip3_chip.irq_disable = ath79_ip3_disable;
+	ip3_chip.irq_enable = ath79_ip3_enable;
+
 	if (soc_is_ar71xx()) {
 		ath79_ip2_handler = ar71xx_ip2_handler;
 		ath79_ip3_handler = ar71xx_ip3_handler;
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index b7d5b83..bb20226 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -688,6 +688,14 @@
 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX		BIT(12)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT0	BIT(13)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT1	BIT(14)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT2	BIT(15)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT3	BIT(16)
+#define QCA953X_PCIE_WMAC_USB1			BIT(24)
+#define QCA953X_PCIE_WMAC_USB2			BIT(28)
+
 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
 	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
 	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
@@ -696,7 +704,14 @@
 	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
 	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
 	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
- 
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_RCX_ALL	\
+	(QCA953X_PCIE_WMAC_INT_PCIE_RCX |	\
+	 QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT0 |  \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT1 |  \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT2 |  \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RCX_INT3)
+
 #define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
 #define QCA955X_EXT_INT_WMAC_TX			BIT(1)
 #define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index be87b54..2e7b026 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -13,6 +13,8 @@
 #define MIPS_CPU_IRQ_BASE	0
 #define NR_IRQS			83
 
+#define ATH79_CPU_IRQ(_x)	(MIPS_CPU_IRQ_BASE + (_x))
+
 #define ATH79_MISC_IRQ_BASE	8
 #define ATH79_MISC_IRQ_COUNT	32
 #define ATH79_MISC_IRQ(_x)	(ATH79_MISC_IRQ_BASE + (_x))