/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Generated by pegen
 * Version 1.1
 * Virage Logic (c) 2009
 * This is a generated file. All manual edits will be lost.
 */

#ifndef _ENET_APP_H
#define _ENET_APP_H 1

#ifdef __cplusplus
extern "C" {
#endif

/*
Register offset definitions for ENET on bus memIntf
*/
#define ENET_CONTROL_offset  0x0000 /* read-write, width=32 */
#define ENET_STATUS_offset   0x0004 /* read-only, width=32 */
#define ENET_TX_SIZE_offset  0x0008 /* read-write, width=32 */
#define ENET_TX_BUFFER_offset 0x000c /* read-write, width=32 */
#define ENET_RX_SIZE_offset  0x0010 /* read-write, width=32 */
#define ENET_RX_BUFFER_offset 0x0014 /* read-write, width=32 */
#define ENET_INTERRUPT_CONFIGURATION_offset 0x0018 /* read-write, width=32 */

/*-------------------------------------------------------------------------*/
/* Bit definitions for control field of the ethernet device */

/* Write this bit to request initialization */
#define EMWSIM_CONTROL_INITIALIZE    (0x0001)

/*
** Write this bit to enable (1) or disable(0) the device interrupts
** The device interrupts on a read or write completion.
** The interrupt is automatically cleared
*/
#define EMWSIM_CONTROL_INT_ENABLE    (0x0002)

/* Write this bit to deinstall the device */
#define EMWSIM_CONTROL_SHUTDOWN      (0x0004)

/* Write this bit to tell the device to transmit */
#define EMWSIM_CONTROL_TRANSMIT      (0x0008)

/* Write this bit to reset the RX Available bit in the status register */
#define EMWSIM_CONTROL_RECEIVED      (0x0010)

/* Write this bit when read to read a packet */
#define EMWSIM_CONTROL_READY_TO_RX   (0x0020)


/*-------------------------------------------------------------------------*/
/* Bit definitions for status field of the ethernet device */

/* The device is initialized */
#define EMWSIM_STATUS_INITIALIZED   (0x0001)

/* The device is able to transmit */
#define EMWSIM_STATUS_TX_AVAILABLE  (0x0002)

/* The device has received a packet */
#define EMWSIM_STATUS_RX_RECEIVED   (0x0004)


/*
Register structure definitions for peripheral ENET on bus memIntf
*/

/*
** EMWSIM STRUCT
** This structure defines what the registers of the simulator ethernet
** device look like.
*/
typedef struct emwsim_struct {

   /* The control register */
   unsigned int CONTROL;

   /* The status register */
   unsigned int STATUS;

   /*
   ** If STATUS & TX_AVAILABLE, and you write CONTROL_TRANSMIT to the
   ** CONTROL register, the device will transmit the packed pointed to
   ** by TX_BUFFER for TX_SIZE.  During transmission, TX_AVAILABLE is
   ** is NOT set in STATUS; at completion of transmission, it is set,
   ** indicating we can transmit again.
   ** Upon completion of transmission, if CONTROL & INTERRUPT_ENABLE,
   ** an interrupt is attempted.
   */
   unsigned int TX_SIZE;
   unsigned char * TX_BUFFER;

   /*
   ** If CONTROL & RX_READY, the device is allowed to receive
   ** an ethernet packet.  It writes the packet to the address in RX_BUFFER
   ** puts its length in RX_SIZE, and sets RX_AVAILABLE in the STATUS
   ** register.  If CONTROL & INTERRUPT_ENABLE, an interrupt
   ** is attempted.
   ** If RX_BUFFER is null, the packet is discarded, and no other changes
   ** are made.
   */
   unsigned int RX_SIZE;
   unsigned char * RX_BUFFER;

   /*
   ** This is the interrupt configuration of the device.
   ** The upper 16 bits is the level (1 or 2)
   ** and the lower 16 bits is the vector.
   ** The default for the device is level 2, vector 6.
   ** This is set up when the device is configured and does not change.
   ** The device driver can read this register to determine how to
   ** catch the interrupt.
   */
   unsigned int INTERRUPT_CONFIGURATION;

};


/*
 Register CONTROL
 Description: Control Register
 */
struct ENET_CONTROL_struct {
    unsigned INITIALIZE : 1; /* bit 0, read-write */
        /* Write this bit to request initialization */
    unsigned INT_ENABLE : 1; /* bit 1, read-write */
        /* Write 1 to enable interrupts and 0 to disable. */
    unsigned SHUTDOWN : 1; /* bit 2, read-write */
        /* Write this bit to de-install the device */
    unsigned TRANSMIT : 1; /* bit 3, read-write */
        /* Write this bit to tell the device to transmit */
    unsigned RECEIVED : 1; /* bit 4, read-write */
        /* Write this bit to reset the RX Available bit in the status register */
    unsigned READY_TO_RX : 1; /* bit 5, read-write */
        /* Write this bit when ready to read a packet */
    unsigned reserved6 : 26; /* bits 6..31, read-only */
        /* reserved */
};

/*
 Register STATUS
 Description: Status Register
 */
struct ENET_STATUS_struct {
    unsigned INITIALIZED : 1; /* bit 0, read-only */
        /* The device is initialized */
    unsigned TX_AVAILABLE : 1; /* bit 1, read-only */
        /* The device is able to transmit */
    unsigned RX_RECEIVED : 1; /* bit 2, read-only */
        /* The device has received a packet */
    unsigned reserved3 : 29; /* bits 3..31, read-only */
        /* reserved */
};

/*
 Register TX_SIZE
 Description: TX Size Register
 */
struct ENET_TX_SIZE_struct {
    unsigned TX_SIZE : 32; /* bits 0..31, read-write */
        /* Total size of packet to transmit (bytes) */
};

/*
 Register TX_BUFFER
 Description: TX Buffer Register
 */
struct ENET_TX_BUFFER_struct {
    unsigned TX_BUFFER : 32; /* bits 0..31, read-write */
        /* Pointer to the packet fragment to transmit */
};

/*
 Register RX_SIZE
 Description: RX Size Register
 */
struct ENET_RX_SIZE_struct {
    unsigned RX_SIZE : 32; /* bits 0..31, read-write */
        /* Largest size a received packet can be (bytes) */
};

/*
 Register RX_BUFFER
 Description: RX Buffer Register
 */
struct ENET_RX_BUFFER_struct {
    unsigned RX_BUFFER : 32; /* bits 0..31, read-write */
        /* Pointer to the place to put the packet when received */
};

/*
 Register INTERRUPT_CONFIGURATION
 Description: Interrupt Configuration Register
 */
struct ENET_INTERRUPT_CONFIGURATION_struct {
    unsigned VECTOR : 16; /* bits 0..15, read-write */
        /* Interrupt Vector (default 6) */
    unsigned LEVEL : 16; /* bits 16..31, read-write */
        /* Interrupt Level (1 or 2) (default 2) */
};


/*
Register accessor functions for peripheral ENET on bus memIntf
*/

/*
 Register CONTROL
 Description: Control Register
 */

static __inline__ unsigned int
READ_ENET_CONTROL_INITIALIZE(unsigned int base)
{
    volatile unsigned int *p = (volatile unsigned int *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 0) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_INITIALIZE(unsigned int base, unsigned int val)
{
    volatile unsigned int *p = (volatile unsigned int *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000001;
    v |= ((val << 0) & 0x00000001);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_INT_ENABLE(unsigned int base)
{
    volatile unsigned int *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 1) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_INT_ENABLE(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000002;
    v |= ((val << 1) & 0x00000002);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_SHUTDOWN(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 2) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_SHUTDOWN(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000004;
    v |= ((val << 2) & 0x00000004);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_TRANSMIT(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 3) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_TRANSMIT(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000008;
    v |= ((val << 3) & 0x00000008);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_RECEIVED(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 4) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_RECEIVED(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000010;
    v |= ((val << 4) & 0x00000010);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_READY_TO_RX(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 5) & 0x00000001);
}

static __inline__ void
WRITE_ENET_CONTROL_READY_TO_RX(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x00000020;
    v |= ((val << 5) & 0x00000020);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_CONTROL_reserved6(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 6) & 0x03ffffff);
}

static __inline__ unsigned int
READ_ENET_CONTROL(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_CONTROL(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_CONTROL_offset);
    *p = val; /* i/o write */
}


/*
 Register STATUS
 Description: Status Register
 */

static __inline__ unsigned int
READ_ENET_STATUS_INITIALIZED(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_STATUS_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 0) & 0x00000001);
}

static __inline__ unsigned int
READ_ENET_STATUS_TX_AVAILABLE(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_STATUS_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 1) & 0x00000001);
}

static __inline__ unsigned int
READ_ENET_STATUS_RX_RECEIVED(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_STATUS_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 2) & 0x00000001);
}

static __inline__ unsigned int
READ_ENET_STATUS_reserved3(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_STATUS_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 3) & 0x1fffffff);
}

static __inline__ unsigned int
READ_ENET_STATUS(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_STATUS_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}


/*
 Register TX_SIZE
 Description: TX Size Register
 */

static __inline__ unsigned int
READ_ENET_TX_SIZE_TX_SIZE(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_SIZE_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_TX_SIZE_TX_SIZE(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_SIZE_offset);
    *p = val; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_TX_SIZE(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_SIZE_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_TX_SIZE(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_SIZE_offset);
    *p = val; /* i/o write */
}


/*
 Register TX_BUFFER
 Description: TX Buffer Register
 */

static __inline__ unsigned int
READ_ENET_TX_BUFFER_TX_BUFFER(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_BUFFER_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_TX_BUFFER_TX_BUFFER(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_BUFFER_offset);
    *p = val; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_TX_BUFFER(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_BUFFER_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_TX_BUFFER(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_TX_BUFFER_offset);
    *p = val; /* i/o write */
}


/*
 Register RX_SIZE
 Description: RX Size Register
 */

static __inline__ unsigned int
READ_ENET_RX_SIZE_RX_SIZE(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_SIZE_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_RX_SIZE_RX_SIZE(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_SIZE_offset);
    *p = val; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_RX_SIZE(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_SIZE_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_RX_SIZE(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_SIZE_offset);
    *p = val; /* i/o write */
}


/*
 Register RX_BUFFER
 Description: RX Buffer Register
 */

static __inline__ unsigned int
READ_ENET_RX_BUFFER_RX_BUFFER(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_BUFFER_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_RX_BUFFER_RX_BUFFER(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_BUFFER_offset);
    *p = val; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_RX_BUFFER(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_BUFFER_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_RX_BUFFER(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_RX_BUFFER_offset);
    *p = val; /* i/o write */
}


/*
 Register INTERRUPT_CONFIGURATION
 Description: Interrupt Configuration Register
 */

static __inline__ unsigned int
READ_ENET_INTERRUPT_CONFIGURATION_VECTOR(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 0) & 0x0000ffff);
}

static __inline__ void
WRITE_ENET_INTERRUPT_CONFIGURATION_VECTOR(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0x0000ffff;
    v |= ((val << 0) & 0x0000ffff);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_INTERRUPT_CONFIGURATION_LEVEL(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    unsigned int val = *p; /* i/o read */
    return (unsigned int)((val >> 16) & 0x0000ffff);
}

static __inline__ void
WRITE_ENET_INTERRUPT_CONFIGURATION_LEVEL(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    unsigned int v = *p; /* i/o read */
    v &= ~0xffff0000;
    v |= ((val << 16) & 0xffff0000);
    *p = v; /* i/o write */
}

static __inline__ unsigned int
READ_ENET_INTERRUPT_CONFIGURATION(unsigned int base)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    unsigned int val = *p; /* i/o read */
    return val;
}

static __inline__ void
WRITE_ENET_INTERRUPT_CONFIGURATION(unsigned int base, unsigned int val)
{
    volatile unsigned int  *p = (volatile unsigned int  *)(base + ENET_INTERRUPT_CONFIGURATION_offset);
    *p = val; /* i/o write */
}


#ifdef __cplusplus
}
#endif

#endif /* _ENET_APP_H */