/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Device tree for AXC003 CPU card: HS38x UP configuration
 */

/include/ "skeleton_hs.dtsi"

/ {
	compatible = "snps,arc";
	clock-frequency = <90000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0xf0000000 0x10000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <90000000>;
		};

		core_intc: archs-intc@cpu {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		/*
		 * this GPIO block ORs all interrupts on CPU card (creg,..)
		 * to uplink only 1 IRQ to ARC core intc
		 */
		dw-apb-gpio@0x2000 {
			compatible = "snps,dw-apb-gpio";
			reg = < 0x2000 0x80 >;
			#address-cells = <1>;
			#size-cells = <0>;

			ictl_intc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&core_intc>;
				interrupts = <25>;
			};
		};

		debug_uart: dw-apb-uart@0x5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33333000>;
			interrupt-parent = <&ictl_intc>;
			interrupts = <2 4>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupt-parent = <&core_intc>;
			interrupts = <20>;
		};
	};

	/*
	 * The DW APB ICTL intc on MB is connected to CPU intc via a
	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
	 *
	 * So here we mimic a direct connection betwen them, ignoring the
	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
	 *
	 * This intc actually resides on MB, but we move it here to
	 * avoid duplicating the MB dtsi file given that IRQ from
	 * this intc to cpu intc are different for axs101 and axs103
	 */
	mb_intc: dw-apb-ictl@0xe0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0xe0012000 0x200 >;
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		interrupts = < 24 >;
	};

	memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x80000000 0x40000000>;
		device_type = "memory";
		reg = <0x80000000 0x20000000>;	/* 512MiB */
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		/*
		 * Move frame buffer out of IOC aperture (0x8z-0xAz).
		 */
		frame_buffer: frame_buffer@be000000 {
			compatible = "shared-dma-pool";
			reg = <0xbe000000 0x2000000>;
			no-map;
		};
	};
};