| /* |
| * Copyright (c) 2014 MediaTek Inc. |
| * Author: Eddie Huang <eddie.huang@mediatek.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/mt8173-clk.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/memory/mt8173-larb-port.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/power/mt8173-power.h> |
| #include <dt-bindings/reset/mt8173-resets.h> |
| #include "mt8173-pinfunc.h" |
| |
| / { |
| compatible = "mediatek,mt8173"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu2>; |
| }; |
| core1 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x000>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x001>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| }; |
| |
| cpu2: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a57"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| }; |
| |
| cpu3: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a57"; |
| reg = <0x101>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| entry-latency-us = <639>; |
| exit-latency-us = <680>; |
| min-residency-us = <1088>; |
| arm,psci-suspend-param = <0x0010000>; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; |
| method = "smc"; |
| cpu_suspend = <0x84000001>; |
| cpu_off = <0x84000002>; |
| cpu_on = <0x84000003>; |
| }; |
| |
| clk26m: oscillator@0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| clk32k: oscillator@1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32000>; |
| clock-output-names = "clk32k"; |
| }; |
| |
| cpum_ck: oscillator@2 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| clock-output-names = "cpum_ck"; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu_thermal { |
| polling-delay-passive = <1000>; /* milliseconds */ |
| polling-delay = <1000>; /* milliseconds */ |
| |
| thermal-sensors = <&thermal>; |
| sustainable-power = <1500>; /* milliwatts */ |
| |
| trips { |
| threshold: trip-point@0 { |
| temperature = <68000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| target: trip-point@1 { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit: cpu_crit@0 { |
| temperature = <115000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map@0 { |
| trip = <&target>; |
| cooling-device = <&cpu0 0 0>; |
| contribution = <1024>; |
| }; |
| map@1 { |
| trip = <&target>; |
| cooling-device = <&cpu2 0 0>; |
| contribution = <2048>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| topckgen: clock-controller@10000000 { |
| compatible = "mediatek,mt8173-topckgen"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: power-controller@10001000 { |
| compatible = "mediatek,mt8173-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pericfg: power-controller@10003000 { |
| compatible = "mediatek,mt8173-pericfg", "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| syscfg_pctl_a: syscfg_pctl_a@10005000 { |
| compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; |
| reg = <0 0x10005000 0 0x1000>; |
| }; |
| |
| pio: pinctrl@0x10005000 { |
| compatible = "mediatek,mt8173-pinctrl"; |
| reg = <0 0x1000b000 0 0x1000>; |
| mediatek,pctl-regmap = <&syscfg_pctl_a>; |
| pins-are-numbered; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
| |
| i2c0_pins_a: i2c0 { |
| pins1 { |
| pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, |
| <MT8173_PIN_46_SCL0__FUNC_SCL0>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_pins_a: i2c1 { |
| pins1 { |
| pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, |
| <MT8173_PIN_126_SCL1__FUNC_SCL1>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins_a: i2c2 { |
| pins1 { |
| pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, |
| <MT8173_PIN_44_SCL2__FUNC_SCL2>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c3_pins_a: i2c3 { |
| pins1 { |
| pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, |
| <MT8173_PIN_107_SCL3__FUNC_SCL3>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c4_pins_a: i2c4 { |
| pins1 { |
| pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, |
| <MT8173_PIN_134_SCL4__FUNC_SCL4>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c6_pins_a: i2c6 { |
| pins1 { |
| pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, |
| <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| scpsys: scpsys@10006000 { |
| compatible = "mediatek,mt8173-scpsys"; |
| #power-domain-cells = <1>; |
| reg = <0 0x10006000 0 0x1000>; |
| clocks = <&clk26m>, |
| <&topckgen CLK_TOP_MM_SEL>, |
| <&topckgen CLK_TOP_VENC_SEL>, |
| <&topckgen CLK_TOP_VENC_LT_SEL>; |
| clock-names = "mfg", "mm", "venc", "venc_lt"; |
| infracfg = <&infracfg>; |
| }; |
| |
| watchdog: watchdog@10007000 { |
| compatible = "mediatek,mt8173-wdt", |
| "mediatek,mt6589-wdt"; |
| reg = <0 0x10007000 0 0x100>; |
| }; |
| |
| timer: timer@10008000 { |
| compatible = "mediatek,mt8173-timer", |
| "mediatek,mt6577-timer"; |
| reg = <0 0x10008000 0 0x1000>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_CLK_13M>, |
| <&topckgen CLK_TOP_RTC_SEL>; |
| }; |
| |
| pwrap: pwrap@1000d000 { |
| compatible = "mediatek,mt8173-pwrap"; |
| reg = <0 0x1000d000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; |
| reset-names = "pwrap"; |
| clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; |
| clock-names = "spi", "wrap"; |
| }; |
| |
| sysirq: intpol-controller@10200620 { |
| compatible = "mediatek,mt8173-sysirq", |
| "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10200620 0 0x20>; |
| }; |
| |
| iommu: iommu@10205000 { |
| compatible = "mediatek,mt8173-m4u"; |
| reg = <0 0x10205000 0 0x1000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_M4U>; |
| clock-names = "bclk"; |
| mediatek,larbs = <&larb0 &larb1 &larb2 |
| &larb3 &larb4 &larb5>; |
| #iommu-cells = <1>; |
| }; |
| |
| efuse: efuse@10206000 { |
| compatible = "mediatek,mt8173-efuse"; |
| reg = <0 0x10206000 0 0x1000>; |
| }; |
| |
| apmixedsys: clock-controller@10209000 { |
| compatible = "mediatek,mt8173-apmixedsys"; |
| reg = <0 0x10209000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| gic: interrupt-controller@10220000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x10221000 0 0x1000>, |
| <0 0x10222000 0 0x2000>, |
| <0 0x10224000 0 0x2000>, |
| <0 0x10226000 0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| auxadc: auxadc@11001000 { |
| compatible = "mediatek,mt8173-auxadc"; |
| reg = <0 0x11001000 0 0x1000>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt8173-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x400>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt8173-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x400>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt8173-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x400>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@11005000 { |
| compatible = "mediatek,mt8173-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11005000 0 0x400>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11007000 0 0x70>, |
| <0 0x11000100 0 0x80>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C0>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11008000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11008000 0 0x70>, |
| <0 0x11000180 0 0x80>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C1>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11009000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11009000 0 0x70>, |
| <0 0x11000200 0 0x80>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C2>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi: spi@1100a000 { |
| compatible = "mediatek,mt8173-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100a000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&pericfg CLK_PERI_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| thermal: thermal@1100b000 { |
| #thermal-sensor-cells = <0>; |
| compatible = "mediatek,mt8173-thermal"; |
| reg = <0 0x1100b000 0 0x1000>; |
| interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; |
| clock-names = "therm", "auxadc"; |
| resets = <&pericfg MT8173_PERI_THERM_SW_RST>; |
| mediatek,auxadc = <&auxadc>; |
| mediatek,apmixedsys = <&apmixedsys>; |
| }; |
| |
| nor_flash: spi@1100d000 { |
| compatible = "mediatek,mt8173-nor"; |
| reg = <0 0x1100d000 0 0xe0>; |
| clocks = <&pericfg CLK_PERI_SPI>, |
| <&topckgen CLK_TOP_SPINFI_IFR_SEL>; |
| clock-names = "spi", "sf"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@11010000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11010000 0 0x70>, |
| <0 0x11000280 0 0x80>; |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C3>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c3_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@11011000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11011000 0 0x70>, |
| <0 0x11000300 0 0x80>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C4>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c4_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@11013000 { |
| compatible = "mediatek,mt8173-i2c"; |
| reg = <0 0x11013000 0 0x70>, |
| <0 0x11000080 0 0x80>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C6>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c6_pins_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| afe: audio-controller@11220000 { |
| compatible = "mediatek,mt8173-afe-pcm"; |
| reg = <0 0x11220000 0 0x1000>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; |
| clocks = <&infracfg CLK_INFRA_AUDIO>, |
| <&topckgen CLK_TOP_AUDIO_SEL>, |
| <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| <&topckgen CLK_TOP_APLL1_DIV0>, |
| <&topckgen CLK_TOP_APLL2_DIV0>, |
| <&topckgen CLK_TOP_I2S0_M_SEL>, |
| <&topckgen CLK_TOP_I2S1_M_SEL>, |
| <&topckgen CLK_TOP_I2S2_M_SEL>, |
| <&topckgen CLK_TOP_I2S3_M_SEL>, |
| <&topckgen CLK_TOP_I2S3_B_SEL>; |
| clock-names = "infra_sys_audio_clk", |
| "top_pdn_audio", |
| "top_pdn_aud_intbus", |
| "bck0", |
| "bck1", |
| "i2s0_m", |
| "i2s1_m", |
| "i2s2_m", |
| "i2s3_m", |
| "i2s3_b"; |
| assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, |
| <&topckgen CLK_TOP_AUD_2_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, |
| <&topckgen CLK_TOP_APLL2>; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt8173-mmc", |
| "mediatek,mt8135-mmc"; |
| reg = <0 0x11230000 0 0x1000>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_0>, |
| <&topckgen CLK_TOP_MSDC50_0_H_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11240000 { |
| compatible = "mediatek,mt8173-mmc", |
| "mediatek,mt8135-mmc"; |
| reg = <0 0x11240000 0 0x1000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_1>, |
| <&topckgen CLK_TOP_AXI_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc2: mmc@11250000 { |
| compatible = "mediatek,mt8173-mmc", |
| "mediatek,mt8135-mmc"; |
| reg = <0 0x11250000 0 0x1000>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_2>, |
| <&topckgen CLK_TOP_AXI_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc3: mmc@11260000 { |
| compatible = "mediatek,mt8173-mmc", |
| "mediatek,mt8135-mmc"; |
| reg = <0 0x11260000 0 0x1000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_3>, |
| <&topckgen CLK_TOP_MSDC50_2_H_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| usb30: usb@11270000 { |
| compatible = "mediatek,mt8173-xhci"; |
| reg = <0 0x11270000 0 0x1000>, |
| <0 0x11280700 0 0x0100>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; |
| clocks = <&topckgen CLK_TOP_USB30_SEL>, |
| <&pericfg CLK_PERI_USB0>, |
| <&pericfg CLK_PERI_USB1>; |
| clock-names = "sys_ck", |
| "wakeup_deb_p0", |
| "wakeup_deb_p1"; |
| phys = <&phy_port0 PHY_TYPE_USB3>, |
| <&phy_port1 PHY_TYPE_USB2>; |
| mediatek,syscon-wakeup = <&pericfg>; |
| status = "okay"; |
| }; |
| |
| u3phy: usb-phy@11290000 { |
| compatible = "mediatek,mt8173-u3phy"; |
| reg = <0 0x11290000 0 0x800>; |
| clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; |
| clock-names = "u3phya_ref"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "okay"; |
| |
| phy_port0: port@11290800 { |
| reg = <0 0x11290800 0 0x800>; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| |
| phy_port1: port@11291000 { |
| reg = <0 0x11291000 0 0x800>; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| mmsys: clock-controller@14000000 { |
| compatible = "mediatek,mt8173-mmsys", "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pwm0: pwm@1401e000 { |
| compatible = "mediatek,mt8173-disp-pwm", |
| "mediatek,mt6595-disp-pwm"; |
| reg = <0 0x1401e000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&mmsys CLK_MM_DISP_PWM026M>, |
| <&mmsys CLK_MM_DISP_PWM0MM>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@1401f000 { |
| compatible = "mediatek,mt8173-disp-pwm", |
| "mediatek,mt6595-disp-pwm"; |
| reg = <0 0x1401f000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&mmsys CLK_MM_DISP_PWM126M>, |
| <&mmsys CLK_MM_DISP_PWM1MM>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| larb0: larb@14021000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x14021000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_SMI_LARB0>, |
| <&mmsys CLK_MM_SMI_LARB0>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| smi_common: smi@14022000 { |
| compatible = "mediatek,mt8173-smi-common"; |
| reg = <0 0x14022000 0 0x1000>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_SMI_COMMON>, |
| <&mmsys CLK_MM_SMI_COMMON>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| larb4: larb@14027000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x14027000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_SMI_LARB4>, |
| <&mmsys CLK_MM_SMI_LARB4>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| imgsys: clock-controller@15000000 { |
| compatible = "mediatek,mt8173-imgsys", "syscon"; |
| reg = <0 0x15000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb2: larb@15001000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x15001000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; |
| clocks = <&imgsys CLK_IMG_LARB2_SMI>, |
| <&imgsys CLK_IMG_LARB2_SMI>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| vdecsys: clock-controller@16000000 { |
| compatible = "mediatek,mt8173-vdecsys", "syscon"; |
| reg = <0 0x16000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb1: larb@16010000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x16010000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; |
| clocks = <&vdecsys CLK_VDEC_CKEN>, |
| <&vdecsys CLK_VDEC_LARB_CKEN>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| vencsys: clock-controller@18000000 { |
| compatible = "mediatek,mt8173-vencsys", "syscon"; |
| reg = <0 0x18000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb3: larb@18001000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x18001000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; |
| clocks = <&vencsys CLK_VENC_CKE1>, |
| <&vencsys CLK_VENC_CKE0>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| vencltsys: clock-controller@19000000 { |
| compatible = "mediatek,mt8173-vencltsys", "syscon"; |
| reg = <0 0x19000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb5: larb@19001000 { |
| compatible = "mediatek,mt8173-smi-larb"; |
| reg = <0 0x19001000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; |
| clocks = <&vencltsys CLK_VENCLT_CKE1>, |
| <&vencltsys CLK_VENCLT_CKE0>; |
| clock-names = "apb", "smi"; |
| }; |
| }; |
| }; |
| |
