| commit | 18abd16376ad88ed3995c63ddae47be78bd56abe | [log] [tgz] |
|---|---|---|
| author | Andrew Bresticker <abrestic@chromium.org> | Thu Nov 06 14:47:55 2014 -0800 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Mon Feb 02 15:46:14 2015 +0200 |
| tree | 149e4b0e10e149d65d4cef3f0f9a0c6f76a17394 | |
| parent | e36f014edff70fc02b3d3d79cead1d58f289332e [diff] |
clk: tegra: SDMMC controllers are on APB Since the SDMMC controller registers are accessed via the APB, the APB must be flushed before gating the SDMMC clocks to prevent register accesses to the SDMMC controllers after their clocks are gated. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>