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*******************************************************************************/
#ifndef __INC_MV_TSU_REGS_H__
#define __INC_MV_TSU_REGS_H__

#define TSU_MAX_DECODE_WIN		4

#define MV_TSU_MODES_REG		(MV_TSU_GLOBAL_REGS_BASE + 0x00)


#define MV_TSU_CONFIG_REG(port)			(MV_TSU_REGS_BASE(port) + 0x00)
#define MV_TSU_DMA_PARAMS_REG(port)		(MV_TSU_REGS_BASE(port) + 0x04)
#define MV_TSU_DONE_QUEUE_BASE_REG(port)	(MV_TSU_REGS_BASE(port) + 0x08)
#define MV_TSU_DESC_QUEUE_BASE_REG(port)	(MV_TSU_REGS_BASE(port) + 0x0C)
#define MV_TSU_DONE_QUEUE_WRITE_PTR_REG(port)	(MV_TSU_REGS_BASE(port) + 0x10)
#define MV_TSU_DONE_QUEUE_READ_PTR_REG(port)	(MV_TSU_REGS_BASE(port) + 0x14)
#define MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port)	(MV_TSU_REGS_BASE(port) + 0x18)
#define MV_TSU_DESC_QUEUE_READ_PTR_REG(port)	(MV_TSU_REGS_BASE(port) + 0x1C)
#define MV_TSU_ENABLE_ACCESS_REG(port)		(MV_TSU_REGS_BASE(port) + 0x2C)
#define MV_TSU_TIMESTAMP_REG(port)		(MV_TSU_REGS_BASE(port) + 0x30)
#define MV_TSU_STATUS_REG(port)			(MV_TSU_REGS_BASE(port) + 0x34)
#define MV_TSU_TIMESTAMP_CTRL_REG(port)		(MV_TSU_REGS_BASE(port) + 0x38)
#define MV_TSU_TEST_REG(port)			(MV_TSU_REGS_BASE(port) + 0x3C)
#define MV_TSU_INTERRUPT_SRC_REG(port)		(MV_TSU_REGS_BASE(port) + 0x40)
#define MV_TSU_INTERRUPT_MASK_REG(port)		(MV_TSU_REGS_BASE(port) + 0x44)
#define MV_TSU_IRQ_PARAM_REG(port)		(MV_TSU_REGS_BASE(port) + 0x48)
#define MV_TSU_DEBUG_REG(port)			(MV_TSU_REGS_BASE(port) + 0x4C)
#define MV_TSU_NEXT_DESC_1_REG(port)		(MV_TSU_REGS_BASE(port) + 0x50)
#define MV_TSU_NEXT_DESC_2_REG(port)		(MV_TSU_REGS_BASE(port) + 0x54)
#define MV_TSU_SYNCBYTE_DETECT_REG(port)	(MV_TSU_REGS_BASE(port) + 0x58)
#define MV_TSU_AGGREGATION_CTRL_REG(port)	(MV_TSU_REGS_BASE(port) + 0x60)
#define MV_TSU_TIMESTAMP_INTERVAL_REG(port)	(MV_TSU_REGS_BASE(port) + 0x64)
#define MV_TSU_CONFIG_2_REG(port)		(MV_TSU_REGS_BASE(port) + 0x68)


/* TSU Modes register.				*/
#define TSU_MODES_PAR_MODE_OFFS		14
#define TSU_MODES_PAR_MODE_MASK		(0x1 << TSU_MODES_PAR_MODE_OFFS)
#define TSU_MODES_PAR_MODE_SER		(0x0 << TSU_MODES_PAR_MODE_OFFS)
#define TSU_MODES_PAR_MODE_PAR		(0x1 << TSU_MODES_PAR_MODE_OFFS)
#define TSU_MODES_TSCK_OFF		15
#define TSU_MODES_TSCK_MASK		(0x3 << TSU_MODES_TSCK_OFF)


/* TSU config register.				*/
#define TSU_CFG_RESET_OFFS		0
#define TSU_CFG_RESET_MASK		(0x3 << TSU_CFG_RESET_OFFS)
#define TSU_CFG_RESET_SET		(0x1 << TSU_CFG_RESET_OFFS)
#define TSU_CFG_RESET_CLEAR		(0x2 << TSU_CFG_RESET_OFFS)
#define TSU_CFG_OPER_OFFS		2
#define TSU_CFG_OPER_MASK		(0x3 << TSU_CFG_OPER_OFFS)
#define TSU_CFG_OPER_DISABLE		(0x1 << TSU_CFG_OPER_OFFS)
#define TSU_CFG_OPER_ENABLE		(0x2 << TSU_CFG_OPER_OFFS)
#define TSU_CFG_DATA_DIR_OFFS		8
#define TSU_CFG_DATA_DIR_MASK		(0x1 << TSU_CFG_DATA_DIR_OFFS)
#define TSU_CFG_DATA_DIR_IN		(0x0 << TSU_CFG_DATA_DIR_OFFS)
#define TSU_CFG_DATA_DIR_OUT		(0x1 << TSU_CFG_DATA_DIR_OFFS)
#define TSU_CFG_DATA_MODE_OFFS		9
#define TSU_CFG_DATA_MODE_MASK		(0x1 << TSU_CFG_DATA_MODE_OFFS)
#define TSU_CFG_DATA_MODE_SER		(0x0 << TSU_CFG_DATA_MODE_OFFS)
#define TSU_CFG_DATA_MODE_PAR		(0x1 << TSU_CFG_DATA_MODE_OFFS)
#define TSU_CFG_OUT_CLOCK_OFFS		10
#define TSU_CFG_OUT_CLOCK_MASK		(0x3 << TSU_CFG_OUT_CLOCK_OFFS)
#define TSU_CFG_OUT_CLOCK_4_32		(0x0 << TSU_CFG_OUT_CLOCK_OFFS)
#define TSU_CFG_OUT_CLOCK_2_16		(0x1 << TSU_CFG_OUT_CLOCK_OFFS)
#define TSU_CFG_OUT_CLOCK_1_8		(0x2 << TSU_CFG_OUT_CLOCK_OFFS)
#define TSU_CFG_OUT_CLOCK_EXT		(0x3 << TSU_CFG_OUT_CLOCK_OFFS)
#define TSU_CFG_CLK_MODE_OFFS		12
#define TSU_CFG_CLK_MODE_MASK		(0x1 << TSU_CFG_CLK_MODE_OFFS)
#define TSU_CFG_CLK_MODE_CONT		(0x0 << TSU_CFG_CLK_MODE_OFFS)
#define TSU_CFG_CLK_MODE_GAPPED		(0x1 << TSU_CFG_CLK_MODE_OFFS)
#define TSU_CFG_TS_SYNC_OFFS		13
#define TSU_CFG_TS_SYNC_MASK		(0x1 << TSU_CFG_TS_SYNC_OFFS)
#define TSU_CFG_TS_SYNC_8BIT		(0x0 << TSU_CFG_TS_SYNC_OFFS)
#define TSU_CFG_TS_SYNC_1BIT		(0x1 << TSU_CFG_TS_SYNC_OFFS)
#define TSU_CFG_DATA_ORD_OFFS		14
#define TSU_CFG_DATA_ORD_MASK		(0x1 << TSU_CFG_DATA_ORD_OFFS)
#define TSU_CFG_DATA_ORD_MSB		(0x0 << TSU_CFG_DATA_ORD_OFFS)
#define TSU_CFG_DATA_ORD_LSB		(0x1 << TSU_CFG_DATA_ORD_OFFS)
#define TSU_CFG_TX_EDGE_OFFS		15
#define TSU_CFG_TX_EDGE_MASK		(0x1 << TSU_CFG_TX_EDGE_OFFS)
#define TSU_CFG_FREQ_MODE_OFFS		16
#define TSU_CFG_FREQ_MODE_MASK		(0x1 << TSU_CFG_FREQ_MODE_OFFS)
#define TSU_CFG_ERR_POL_OFFS		18
#define TSU_CFG_ERR_POL_MASK		(0x1 << TSU_CFG_ERR_POL_OFFS)
#define TSU_CFG_ERR_USED_OFFS		19
#define TSU_CFG_ERR_USED_MASK		(0x1 << TSU_CFG_ERR_USED_OFFS)
#define TSU_CFG_VAL_POL_OFFS		20
#define TSU_CFG_VAL_POL_MASK		(0x1 << TSU_CFG_VAL_POL_OFFS)
#define TSU_CFG_VAL_USED_OFFS		21
#define TSU_CFG_VAL_USED_MASK		(0x1 << TSU_CFG_VAL_USED_OFFS)
#define TSU_CFG_SYNC_POL_OFFS		22
#define TSU_CFG_SYNC_POL_MASK		(0x1 << TSU_CFG_SYNC_POL_OFFS)
#define TSU_CFG_SYNC_USED_OFFS		23
#define TSU_CFG_SYNC_USED_MASK		(0x1 << TSU_CFG_SYNC_USED_OFFS)
#define TSU_CFG_RESET_SET		(0x1 << TSU_CFG_RESET_OFFS)
#define TSU_CFG_PKT_SIZE_OFFS		24
#define TSU_CFG_PKT_SIZE_MASK		(0xFF << TSU_CFG_PKT_SIZE_OFFS)

/* TSU DMA parameters register.			*/
#define TSU_DMAP_DMA_LEN_OFFS		0
#define TSU_DMAP_DMA_LEN_MASK		(0xFFFF << TSU_DMAP_DMA_LEN_OFFS)
#define TSU_DMAP_DATA_WTRMK_OFFS	16
#define TSU_DMAP_DATA_WTRMK_MASK	(0xFF << TSU_DMAP_DATA_WTRMK_OFFS)
#define TSU_DMAP_DATA_WTRMK_MAX		0xFF
#define TSU_DMAP_DESC_Q_SIZE_OFFS	24
#define TSU_DMAP_DESC_Q_SIZE_MASK	(0xF << TSU_DMAP_DESC_Q_SIZE_OFFS)
#define TSU_DMAP_DONE_Q_SIZE_OFFS	28
#define TSU_DMAP_DONE_Q_SIZE_MASK	(0xF << TSU_DMAP_DONE_Q_SIZE_OFFS)

/* TSU Done queue base register.		*/
#define TSU_DONE_PTR_BASE_OFFS		2
#define TSU_DONE_PTR_BASE_MASK		(0x3FFFFFFF << TSU_DONE_PTR_BASE_OFFS)

/* TSU Desc queue base register.		*/
#define TSU_DESC_PTR_BASE_OFFS		2
#define TSU_DESC_PTR_BASE_MASK		(0x3FFFFFFF << TSU_DESC_PTR_BASE_OFFS)

/* TSU Done queue write pointer register.	*/
#define TSU_DONE_WRITE_PTR_OFFS		0
#define TSU_DONE_WRITE_PTR_MASK		(0xFFF << TSU_DONE_WRITE_PTR_OFFS)

/* TSU Done queue read pointer register.	*/
#define TSU_DONE_READ_PTR_OFFS		0
#define TSU_DONE_READ_PTR_MASK		(0xFFF << TSU_DONE_READ_PTR_OFFS)

/* TSU Desc queue write pointer register.	*/
#define TSU_DESC_WRITE_PTR_OFFS		0
#define TSU_DESC_WRITE_PTR_MASK		(0xFFF << TSU_DESC_WRITE_PTR_OFFS)

/* TSU Desc queue read pointer register.	*/
#define TSU_DESC_READ_PTR_OFFS		0
#define TSU_DESC_READ_PTR_MASK		(0xFFF << TSU_DESC_READ_PTR_OFFS)

/* TSU access enable reg.			*/
#define TSU_ENACC_TS_READ_OFFS		0
#define TSU_ENACC_TS_WRITE_OFFS		8
#define TSU_ENACC_DESC_WRITE_OFFS	16
#define TSU_ENACC_DESC_READ_OFFS	24

/* TSU Timestamp register.			*/
#define TSU_TMSTMP_TIMESTAMP_OFFS	0
#define TSU_TMSTMP_TIMESTAMP_MASK	(0xFFFFFFF << TSU_TMSTMP_TIMESTAMP_OFFS)

/* TSU status register.				*/
#define TSU_STATUS_OFFS			0
#define TSU_STATUS_MASK			(0x7FF << TSU_STATUS_OFFS)
#define TSU_STATUS_IF_ERR		(0x100 << TSU_STATUS_OFFS)
#define TSU_STATUS_FIFO_OVFL_ERR	(0x200 << TSU_STATUS_OFFS)
#define TSU_STATUS_CONN_ERR		(0x400 << TSU_STATUS_OFFS)

/* TSU interrupt source register.		*/
#define TSU_INT_TS_IF_ERROR		(1 << 3)
#define TSU_INT_FIFO_OVFL_ERROR		(1 << 4)
#define TSU_INT_TS_CONN_ERROR		(1 << 5)
#define TSU_INT_CLOCK_SYNC_EXP		(1 << 6)

/* TSU SyncByte detect register.		*/
#define TSU_SYNC_DETECT_CNT_OFFS	0
#define TSU_SYNC_DETECT_CNT_MASK	(0xF << TSU_SYNC_DETECT_CNT_OFFS)
#define TSU_SYNC_LOSS_CNT_OFFS		4
#define TSU_SYNC_LOSS_CNT_MASK		(0xF << TSU_SYNC_LOSS_CNT_OFFS)

/* TSU Aggregation control register.		*/
#define TSU_AGGR_PCKT_NUM_OFFS		0
#define TSU_AGGR_PCKT_NUM_MASK		(0xFF << TSU_AGGR_PCKT_NUM_OFFS)
#define TSU_AGGR_TMSTMP_OFF_OFFS	8
#define TSU_AGGR_TMSTMP_OFF_MASK	(0xF << TSU_AGGR_TMSTMP_OFF_OFFS)
#define TSU_AGGR_FLUSH_ERR_OFFS		26
#define TSU_AGGR_FLUSH_ERR_MASK		(0x3 << TSU_AGGR_FLUSH_ERR_OFFS)
#define TSU_AGGR_FLUSH_ERR_DISABLE	(0x1 << TSU_AGGR_FLUSH_ERR_OFFS)
#define TSU_AGGR_FLUSH_ERR_ENABLE	(0x2 << TSU_AGGR_FLUSH_ERR_OFFS)
#define TSU_AGGR_TMSTMP_MODE_OFFS	28
#define TSU_AGGR_TMSTMP_MODE_MASK	(0x3 << TSU_AGGR_TMSTMP_MODE_OFFS)
#define TSU_AGGR_TMSTMP_TO_DONE_Q	(0x1 << TSU_AGGR_TMSTMP_MODE_OFFS)
#define TSU_AGGR_TMSTMP_TO_PCKT		(0x2 << TSU_AGGR_TMSTMP_MODE_OFFS)
#define TSU_AGGR_ENABLE_OFFS		30
#define TSU_AGGR_ENABLE_MASK		(0x3 << TSU_AGGR_ENABLE_OFFS)
#define TSU_AGGR_DISABLE		(0x1 << TSU_AGGR_ENABLE_OFFS)
#define TSU_AGGR_ENABLE			(0x2 << TSU_AGGR_ENABLE_OFFS)


/* TSU timestamp interval register.		*/
#define TSU_TMSTP_INTRVL_OFFS		0
#define TSU_TMSTP_INTRVL_MASK		(0xFFFFFFF << TSU_TMSTP_INTRVL_OFFS)

/* TSU timestamp control register.		*/
#define TSU_TMS_CTRL_TIMER_OFFS		0
#define TSU_TMS_CTRL_TIMER_MASK		(0x3 << TSU_TMS_CTRL_TIMER_OFFS)
#define TSU_TMS_CTRL_TIMER_DIS		(0x1 << TSU_TMS_CTRL_TIMER_OFFS)
#define TSU_TMS_CTRL_TIMER_EN		(0x2 << TSU_TMS_CTRL_TIMER_OFFS)
#define TSU_TMS_CTRL_AUTO_ADJ_OFFS	2
#define TSU_TMS_CTRL_AUTO_ADJ_MASK	(0x3 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
#define TSU_TMS_CTRL_AUTO_ADJ_OFF	(0x1 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
#define TSU_TMS_CTRL_AUTO_ADJ_ON	(0x2 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
#define TSU_TMS_CTRL_READ_TIMER_OFFS	4
#define TSU_TMS_CTRL_READ_TIMER_MASK	(0x1 << TSU_TMS_CTRL_READ_TIMER_OFFS)


/*******************************************/
/* TSU Windows Registers                   */
/*******************************************/
#define TSU_MAX_DECODE_WIN		4

#define MV_TSU_WIN_CTRL_REG(win)	(MV_TSU_GLOBAL_REGS_BASE + 0x30 + 0x10 * win)
#define MV_TSU_WIN_BASE_REG(win)	(MV_TSU_GLOBAL_REGS_BASE + 0x34 + 0x10 * win)

/* TSU windows control register.		*/
#define TSU_WIN_CTRL_EN_MASK		(0x1 << 0)
#define TSU_WIN_CTRL_TARGET_OFFS	4
#define TSU_WIN_CTRL_TARGET_MASK	(0xF << TSU_WIN_CTRL_TARGET_OFFS)
#define TSU_WIN_CTRL_ATTR_OFFS		8
#define TSU_WIN_CTRL_ATTR_MASK		(0xFF << TSU_WIN_CTRL_ATTR_OFFS)
#define TSU_WIN_CTRL_SIZE_OFFS		16
#define TSU_WIN_CTRL_SIZE_MASK		(0xFFFF << TSU_WIN_CTRL_SIZE_OFFS)
#define TSU_WIN_SIZE_ALIGN		_64K

/* TSU windows base register.			*/
#define TSU_WIN_BASE_OFFS		16
#define TSU_WIN_BASE_MASK		(0xFFFF << TSU_WIN_BASE_OFFS)


#endif /* __INC_MV_TSU_REGS_H__ */