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| ******************************************************************************/ | |
| /****************************************************************************** | |
| ** FILE : gponOnuIsr.h ** | |
| ** ** | |
| ** DESCRIPTION : This file contains ONU GPON Interrupt implementation ** | |
| ******************************************************************************* | |
| * * | |
| * MODIFICATION HISTORY: * | |
| * * | |
| * 29Oct06 Oren Ben Hayun created * | |
| * =========================================================================== * | |
| ******************************************************************************/ | |
| #ifndef _ONU_GPON_ISR_H | |
| #define _ONU_GPON_ISR_H | |
| /* Include Files | |
| ------------------------------------------------------------------------------*/ | |
| /* Definitions | |
| ------------------------------------------------------------------------------*/ | |
| #define ONU_GPON_LOS_ALARM_MASK (0x0001) | |
| #define ONU_GPON_LOF_ALARM_MASK (0x0002) | |
| #define ONU_GPON_LCDG_ALARM_MASK (0x0004) | |
| #define ONU_GPON_DS_PLOAM_MASK (0x0008) | |
| #define ONU_GPON_CDR_LOL_MASK (0x0010) | |
| #define ONU_GPON_BIP_INERVAL_MASK (0x0020) | |
| #define ONU_GPON_RAM_TEST_GRX_PARITY_ERR_MASK (0x0040) | |
| #define ONU_GPON_RAM_TEST_GEM_PARITY_ERR_MASK (0x0080) | |
| #define ONU_GPON_RAM_TEST_GTX_PARITY_ERR_MASK (0x0100) | |
| #define ONU_GPON_RAM_TEST_UTM_PARITY_ERR_MASK (0x0200) | |
| #define ONU_GPON_PHY_READY_STATUS_MASK (0x0400) | |
| #define ONU_GPON_PHY_SIGNAL_DETECT_STATUS_MASK (0x0800) | |
| #define ONU_GPON_XVR_SIGNAL_DETECT_STATUS_MASK (0x1000) | |
| #define ONU_GPON_LOS_ALARM_SHIFT (0) | |
| #define ONU_GPON_LOF_ALARM_SHIFT (1) | |
| #define ONU_GPON_LCDG_ALARM_SHIFT (2) | |
| #define ONU_GPON_DS_PLOAM_SHIFT (3) | |
| #define ONU_GPON_CDR_LOL_SHIFT (4) | |
| #define ONU_GPON_BIP_INERVAL_SHIFT (5) | |
| #define ONU_GPON_RAM_TEST_GRX_PARITY_ERR_SHIFT (6) | |
| #define ONU_GPON_RAM_TEST_GEM_PARITY_ERR_SHIFT (7) | |
| #define ONU_GPON_RAM_TEST_GTX_PARITY_ERR_SHIFT (8) | |
| #define ONU_GPON_RAM_TEST_UTM_PARITY_ERR_SHIFT (9) | |
| #define ONU_GPON_PHY_READY_STATUS_SHIFT (10) | |
| #define ONU_GPON_PHY_SIGNAL_DETECT_STATUS_SHIFT (11) | |
| #define ONU_GPON_XVR_SIGNAL_DETECT_STATUS_SHIFT (12) | |
| #define ONU_GPON_EVENT_SHIFT (16) | |
| #define ON_GPON_MAX_ALARMS (3) | |
| #define ONU_GPON_INT_ALARMS (ONU_GPON_LOF_ALARM_MASK |\ | |
| ONU_GPON_LCDG_ALARM_MASK) | |
| #define ONU_GPON_PARITY_ERROR (ONU_GPON_RAM_TEST_GRX_PARITY_ERR_MASK |\ | |
| ONU_GPON_RAM_TEST_GEM_PARITY_ERR_MASK |\ | |
| ONU_GPON_RAM_TEST_GTX_PARITY_ERR_MASKK |\ | |
| ONU_GPON_RAM_TEST_UTM_PARITY_ERR_MASK) | |
| #define ONU_GPON_READY_STATUS (ONU_GPON_PHY_READY_STATUS_SHIFT |\ | |
| ONU_GPON_PHY_SIGNAL_DETECT_STATUS_SHIFT |\ | |
| ONU_GPON_XVR_SIGNAL_DETECT_STATUS_SHIFT) | |
| #if 1 | |
| #define ONU_GPON_INTERRUPTS (ONU_GPON_INT_ALARMS |\ | |
| ONU_GPON_DS_PLOAM_MASK |\ | |
| ONU_GPON_BIP_INERVAL_MASK |\ | |
| ONU_GPON_XVR_SIGNAL_DETECT_STATUS_MASK) | |
| #else | |
| #define ONU_GPON_INTERRUPTS (ONU_GPON_INT_ALARMS |\ | |
| ONU_GPON_PARITY_ERROR |\ | |
| ONU_GPON_READY_STATUS |\ | |
| ONU_GPON_DS_PLOAM_MASK |\ | |
| ONU_GPON_BIP_INERVAL_MASK)*/ | |
| #endif | |
| #define ONU_GPON_INTERRUPT_INTERVAL (10) | |
| /* Enums | |
| ------------------------------------------------------------------------------*/ | |
| typedef enum | |
| { | |
| ONU_GPON_ISR_ALARM, | |
| ONU_GPON_ISR_PLOAM, | |
| ONU_GPON_ISR_BIP, | |
| ONU_GPON_ISR_TYPE_MAX | |
| }E_OnuGponIsrTypes; | |
| /* Typedefs | |
| ------------------------------------------------------------------------------*/ | |
| typedef struct | |
| { | |
| MV_U32 interruptReadError; | |
| MV_U32 sendMessageError[ONU_GPON_ISR_TYPE_MAX]; | |
| MV_U32 setEventError[ONU_GPON_ISR_TYPE_MAX]; | |
| MV_U32 interruptSameStatus[ON_GPON_MAX_ALARMS]; | |
| MV_U32 ploamStatusNoInterrupt; | |
| }S_OnuGponIsrCounters; | |
| /* Global variables | |
| ------------------------------------------------------------------------------*/ | |
| /* Global functions | |
| ------------------------------------------------------------------------------*/ | |
| MV_STATUS onuGponIsrInit(void); | |
| void onuGponIsrLowRoutine(MV_U32 *interruptEvent, MV_U32 *interruptStatus); | |
| void onuGponIsrRoutine(MV_U32 interruptEvent, MV_U32 interruptStatus); | |
| #ifndef PON_FPGA | |
| void onuGponDgIsrRoutine(void); | |
| void onuGponIsrXvrResetTimerHndl(unsigned long data); | |
| MV_STATUS onuGponIsrXvrResetStateSet(MV_BOOL mode); | |
| #endif /* PON_FPGA */ | |
| void onuGponPonMngDebugModeSet(MV_BOOL mode); | |
| MV_BOOL onuGponPonMngDebugModeGet(void); | |
| /* Macros | |
| ------------------------------------------------------------------------------*/ | |
| #endif /* _ONU_GPON_ISR_H */ | |