Update to SDK_2.6.25-RC70
cp -prf * ../prism/
cd ../prism
git add -Af .
git commit
Change-Id: I5b34d94e309432c90ab4a7d6c63def4683ac6737
diff --git a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvHwf.c b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvHwf.c
index e57702c..69b6a4c 100755
--- a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvHwf.c
+++ b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvHwf.c
@@ -235,6 +235,19 @@
return MV_OK;
}
+MV_STATUS mvNetaHwfTxqNextIndexGet(int port, int tx_port, int txp, int txq, int *val)
+{
+ MV_U32 regVal;
+
+ regVal = NETA_HWF_TX_PORT_MASK(tx_port + txp) | NETA_HWF_TXQ_MASK(txq) | NETA_HWF_REG_MASK(3);
+ MV_REG_WRITE(NETA_HWF_TX_PTR_REG(port), regVal);
+
+ regVal = MV_REG_READ(NETA_HWF_MEMORY_REG(port));
+ if (val)
+ *val = (int)((regVal >> 16) & 0x3fff);
+
+ return MV_OK;
+}
/*******************************************************************************
* mvNetaHwfTxqEnable - Enable / Disable HWF from the rx_port to tx_port/txp/txq
diff --git a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNeta.h b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNeta.h
index ad3679c..5a9ac64 100755
--- a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNeta.h
+++ b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNeta.h
@@ -474,6 +474,30 @@
return sent_desc;
}
+/* Invalidate TXQ descriptor - buffer will not be sent, buffer will not be returned */
+static INLINE void mvNetaTxqDescInv(NETA_TX_DESC *pTxDesc)
+{
+ pTxDesc->command |= NETA_TX_HWF_MASK;
+ pTxDesc->command &= ~NETA_TX_BM_ENABLE_MASK;
+ pTxDesc->hw_cmd |= NETA_TX_ES_MASK;
+}
+
+/* Return: 1 - TX descriptor is valid, 0 - TX descriptor is invalid */
+static INLINE int mvNetaTxqDescIsValid(NETA_TX_DESC *pTxDesc)
+{
+ return ((pTxDesc->hw_cmd & NETA_TX_ES_MASK) == 0);
+}
+
+/* Get index of descripotor to be processed next in the specific TXQ */
+static INLINE int mvNetaTxqNextIndexGet(int port, int txp, int txq)
+{
+ MV_U32 regVal;
+
+ regVal = MV_REG_READ(NETA_TXQ_INDEX_REG(port, txp, txq));
+
+ return (regVal & NETA_TXQ_NEXT_DESC_INDEX_MASK) >> NETA_TXQ_NEXT_DESC_INDEX_OFFS;
+}
+
/* Get number of TX descriptors didn't send by HW yet and waiting for TX */
static INLINE int mvNetaTxqPendDescNumGet(int port, int txp, int txq)
{
@@ -755,6 +779,8 @@
MV_STATUS mvNetaHwfTxqDropSet(int port, int p, int txp, int txq, int thresh, int bits);
MV_STATUS mvNetaHwfMhSrcSet(int port, MV_NETA_HWF_MH_SRC src);
MV_STATUS mvNetaHwfMhSelSet(int port, MV_U8 mhSel);
+MV_STATUS mvNetaHwfTxqNextIndexGet(int port, int tx_port, int txp, int txq, int *val);
+
void mvNetaHwfRxpRegs(int port);
void mvNetaHwfTxpRegs(int port, int p, int txp);
diff --git a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaDebug.c b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaDebug.c
index 2a487d0..4db75e3 100755
--- a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaDebug.c
+++ b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaDebug.c
@@ -599,16 +599,20 @@
mvEthMibPrint(port, mib, ETH_MIB_BAD_CRC_EVENT, "BAD_CRC_EVENT");
mvEthRegPrint0(ETH_RX_DISCARD_PKTS_CNTR_REG(port), "RX_DISCARD_PKTS_CNTR_REG");
mvEthRegPrint0(ETH_RX_OVERRUN_PKTS_CNTR_REG(port), "RX_OVERRUN_PKTS_CNTR_REG");
+
mvOsPrintf("\n[Tx]\n");
mvEthMibPrint(port, mib, ETH_MIB_GOOD_FRAMES_SENT, "GOOD_FRAMES_SENT");
mvEthMibPrint(port, mib, ETH_MIB_BROADCAST_FRAMES_SENT, "BROADCAST_FRAMES_SENT");
mvEthMibPrint(port, mib, ETH_MIB_MULTICAST_FRAMES_SENT, "MULTICAST_FRAMES_SENT");
mvEthMibPrint(port, mib, ETH_MIB_GOOD_OCTETS_SENT_LOW, "GOOD_OCTETS_SENT");
+
mvOsPrintf("\n[Tx Errors]\n");
mvEthMibPrint(port, mib, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR, "INTERNAL_MAC_TRANSMIT_ERR");
mvEthMibPrint(port, mib, ETH_MIB_EXCESSIVE_COLLISION, "EXCESSIVE_COLLISION");
mvEthMibPrint(port, mib, ETH_MIB_COLLISION, "COLLISION");
mvEthMibPrint(port, mib, ETH_MIB_LATE_COLLISION, "LATE_COLLISION");
+ mvEthRegPrint0(NETA_TX_BAD_FCS_CNTR_REG(port, mib), "NETA_TX_BAD_FCS_CNTR_REG");
+ mvEthRegPrint0(NETA_TX_DROP_CNTR_REG(port, mib), "NETA_TX_DROP_CNTR_REG");
mvOsPrintf("\n[FC control]\n");
mvEthMibPrint(port, mib, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED, "UNREC_MAC_CONTROL_RECEIVED");
diff --git a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaRegs.h b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaRegs.h
index 7b0d73b..435ce51 100755
--- a/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaRegs.h
+++ b/arch/arm/plat-feroceon/mv_hal/neta/gbe/mvNetaRegs.h
@@ -313,6 +313,10 @@
#define NETA_HWF_TXQ_OFFS 8
#define NETA_HWF_TXQ_ALL_MASK (0x7 << NETA_HWF_TXQ_OFFS)
#define NETA_HWF_TXQ_MASK(txq) ((txq) << NETA_HWF_TXQ_OFFS)
+
+#define NETA_HWF_REG_OFFS 0
+#define NETA_HWF_REG_ALL_MASK (0x7 << NETA_HWF_REG_OFFS)
+#define NETA_HWF_REG_MASK(reg) ((reg) << NETA_HWF_REG_OFFS)
/*-----------------------------------------------------------------------------------*/
#define NETA_HWF_DROP_TH_REG(p) (NETA_REG_BASE(p) + 0x1d40)
