diff --git a/arch/arm/mach-comcerto/board-optimus.c b/arch/arm/mach-comcerto/board-optimus.c
index 2c6e981..bfe855a 100644
--- a/arch/arm/mach-comcerto/board-optimus.c
+++ b/arch/arm/mach-comcerto/board-optimus.c
@@ -71,6 +71,8 @@
 
 static void __init board_gpio_init(void)
 {
+	uint32_t mask = 0xFFFFFFFC;
+	uint32_t value = 0x0;
 #ifdef CONFIG_COMCERTO_PFE_UART_SUPPORT
 	writel((readl(COMCERTO_GPIO_PIN_SELECT_REG) & ~PFE_UART_GPIO) | PFE_UART_BUS, COMCERTO_GPIO_PIN_SELECT_REG);
 	c2k_gpio_pin_stat.c2k_gpio_pins_0_31 |= PFE_UART_GPIO_PIN; /* GPIOs 12 & 13 are used for PFE_UART */
@@ -107,10 +109,19 @@
 	c2k_gpio_pin_stat.c2k_gpio_pins_0_31 |= NOR_GPIO_PIN;
 #endif
 
-#ifdef MOCA_RESET_GPIO_PIN
-	__raw_writel(__raw_readl(COMCERTO_GPIO_OUTPUT_REG) | MOCA_RESET_GPIO_PIN, COMCERTO_GPIO_OUTPUT_REG);
+#ifdef TUNER_RESET_GPIO_PIN
+	value |= TUNER_RESET_GPIO_PIN;
 #endif
 
+#ifdef USB_BRG_RESET_GPIO_PIN
+	value |= USB_BRG_RESET_GPIO_PIN;
+#endif
+
+#ifdef MOCA_RESET_GPIO_PIN
+	value |= MOCA_RESET_GPIO_PIN;
+#endif
+	__raw_writel(__raw_readl(COMCERTO_GPIO_OUTPUT_REG) | (value), COMCERTO_GPIO_OUTPUT_REG);
+
 #ifdef PCIE_ADDITIONAL_RESET_PIN
 	printk(KERN_WARNING "Pulsing GPIO_62 to reset PCIe");
 	writel((0x2 << 4) | (readl(COMCERTO_GPIO_MISC_PIN_SELECT) & ~(0x3 << 4)),
@@ -125,9 +136,14 @@
 			COMCERTO_GPIO_63_32_PIN_OUTPUT);
 	udelay(1000);
 #endif
-
+#if defined(CONFIG_GOOGLE_SPACECAST)
+	// enable TPM interrupt as level triggered, falling edge.
+	value = COMCERTO_GPIO_INTR_FALLING_EDGE;
+#else
 	// enable GPIO0 interrupt (for MoCA) as level triggered, active high.
-	__raw_writel(__raw_readl(COMCERTO_GPIO_INT_CFG_REG) | (0x3),
+	value = COMCERTO_GPIO_INTR_ACTIVE_HIGH;
+#endif
+	__raw_writel((__raw_readl(COMCERTO_GPIO_INT_CFG_REG) & (mask)) | value,
 			COMCERTO_GPIO_INT_CFG_REG);
 }
 
@@ -707,7 +723,11 @@
 	platform_add_devices(comcerto_devices, ARRAY_SIZE(comcerto_devices));
 }
 
+#if defined(CONFIG_GOOGLE_SPACECAST)
+MACHINE_START(COMCERTO, "Google Fiber Spacecast")
+#else
 MACHINE_START(COMCERTO, "Google Fiber Optimus")
+#endif
 	.atag_offset    = COMCERTO_AXI_DDR_BASE + 0x100,
 	.reserve	= platform_reserve,
 	.map_io		= platform_map_io,
diff --git a/arch/arm/mach-comcerto/include/mach/board-optimus.h b/arch/arm/mach-comcerto/include/mach/board-optimus.h
index bf2d6cf..b29badf 100644
--- a/arch/arm/mach-comcerto/include/mach/board-optimus.h
+++ b/arch/arm/mach-comcerto/include/mach/board-optimus.h
@@ -50,4 +50,15 @@
 	 ***********************************/
 	#define COMCERTO_SLIC_GPIO_IRQ		IRQ_G2
 
+	/*****************************************
+	 * Spacecast board specific configuration
+	 *****************************************/
+	#if defined(CONFIG_GOOGLE_SPACECAST)
+		#undef COMCERTO_OUTPUT_GPIO
+		#undef MOCA_RESET_GPIO_PIN
+		#define TUNER_RESET_GPIO_PIN	GPIO_PIN_11
+		#define USB_BRG_RESET_GPIO_PIN	GPIO_PIN_9
+		#define COMCERTO_OUTPUT_GPIO	(USB_BRG_RESET_GPIO_PIN|TUNER_RESET_GPIO_PIN)
+	#endif
+
 #endif
diff --git a/arch/arm/mach-comcerto/include/mach/comcerto-2000/gpio.h b/arch/arm/mach-comcerto/include/mach/comcerto-2000/gpio.h
index 764b176..dfc24d8 100644
--- a/arch/arm/mach-comcerto/include/mach/comcerto-2000/gpio.h
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-2000/gpio.h
@@ -85,6 +85,10 @@
 #define COMCERTO_GPIO_MEM_EMA_CONF5		APB_VADDR(COMCERTO_APB_GPIO_BASE + 0x1B4)
 #define COMCERTO_GPIO_MEM_EMA_CONF6		APB_VADDR(COMCERTO_APB_GPIO_BASE + 0x1B8)
 
+#define COMCERTO_GPIO_INTR_FALLING_EDGE		0x01
+#define COMCERTO_GPIO_INTR_RISING_EDGE		0x02
+#define COMCERTO_GPIO_INTR_ACTIVE_HIGH		0x03
+
 #define GPIO_0		0x00000003
 #define GPIO_1		0x0000000C
 #define GPIO_2		0x00000030