Designware SPI: Round up clock divisor
Previously, the clock divisor was rounded down which caused the clock
signal to oscillate at a higher frequency than what we specified. This
is risky if the frequency we specified is already the maximum for a
certain component. Let's play it safe and round up the divisor i.e.
round down the frequency.
Unfortunately, the DesignWare SPI controller requires the divisor to be
even which can cause a further frequency decrease.
Change-Id: I649a5b08a426b7cbba9367cb84cf007fb7c7f64b
1 file changed
