| /* |
| * Kernel-based Virtual Machine driver for Linux |
| * |
| * This module enables machines with Intel VT-x extensions to run virtual |
| * machines without emulation or binary translation. |
| * |
| * Copyright (C) 2006 Qumranet, Inc. |
| * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
| * |
| * Authors: |
| * Avi Kivity <avi@qumranet.com> |
| * Yaniv Kamay <yaniv@qumranet.com> |
| * |
| * This work is licensed under the terms of the GNU GPL, version 2. See |
| * the COPYING file in the top-level directory. |
| * |
| */ |
| |
| #include "irq.h" |
| #include "mmu.h" |
| |
| #include <linux/kvm_host.h> |
| #include <linux/module.h> |
| #include <linux/kernel.h> |
| #include <linux/mm.h> |
| #include <linux/highmem.h> |
| #include <linux/sched.h> |
| #include <linux/moduleparam.h> |
| #include <linux/ftrace_event.h> |
| #include <linux/slab.h> |
| #include <linux/tboot.h> |
| #include "kvm_cache_regs.h" |
| #include "x86.h" |
| |
| #include <asm/io.h> |
| #include <asm/desc.h> |
| #include <asm/vmx.h> |
| #include <asm/virtext.h> |
| #include <asm/mce.h> |
| #include <asm/i387.h> |
| #include <asm/xcr.h> |
| #include <asm/perf_event.h> |
| |
| #include "trace.h" |
| |
| #define __ex(x) __kvm_handle_fault_on_reboot(x) |
| #define __ex_clear(x, reg) \ |
| ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) |
| |
| MODULE_AUTHOR("Qumranet"); |
| MODULE_LICENSE("GPL"); |
| |
| static int __read_mostly enable_vpid = 1; |
| module_param_named(vpid, enable_vpid, bool, 0444); |
| |
| static int __read_mostly flexpriority_enabled = 1; |
| module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
| |
| static int __read_mostly enable_ept = 1; |
| module_param_named(ept, enable_ept, bool, S_IRUGO); |
| |
| static int __read_mostly enable_unrestricted_guest = 1; |
| module_param_named(unrestricted_guest, |
| enable_unrestricted_guest, bool, S_IRUGO); |
| |
| static int __read_mostly emulate_invalid_guest_state = 0; |
| module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
| |
| static int __read_mostly vmm_exclusive = 1; |
| module_param(vmm_exclusive, bool, S_IRUGO); |
| |
| static int __read_mostly yield_on_hlt = 1; |
| module_param(yield_on_hlt, bool, S_IRUGO); |
| |
| static int __read_mostly fasteoi = 1; |
| module_param(fasteoi, bool, S_IRUGO); |
| |
| /* |
| * If nested=1, nested virtualization is supported, i.e., guests may use |
| * VMX and be a hypervisor for its own guests. If nested=0, guests may not |
| * use VMX instructions. |
| */ |
| static int __read_mostly nested = 0; |
| module_param(nested, bool, S_IRUGO); |
| |
| #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
| (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) |
| #define KVM_GUEST_CR0_MASK \ |
| (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) |
| #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ |
| (X86_CR0_WP | X86_CR0_NE) |
| #define KVM_VM_CR0_ALWAYS_ON \ |
| (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) |
| #define KVM_CR4_GUEST_OWNED_BITS \ |
| (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ |
| | X86_CR4_OSXMMEXCPT) |
| |
| #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
| #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) |
| |
| #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
| |
| /* |
| * These 2 parameters are used to config the controls for Pause-Loop Exiting: |
| * ple_gap: upper bound on the amount of time between two successive |
| * executions of PAUSE in a loop. Also indicate if ple enabled. |
| * According to test, this time is usually smaller than 128 cycles. |
| * ple_window: upper bound on the amount of time a guest is allowed to execute |
| * in a PAUSE loop. Tests indicate that most spinlocks are held for |
| * less than 2^12 cycles |
| * Time is measured based on a counter that runs at the same rate as the TSC, |
| * refer SDM volume 3b section 21.6.13 & 22.1.3. |
| */ |
| #define KVM_VMX_DEFAULT_PLE_GAP 128 |
| #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 |
| static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
| module_param(ple_gap, int, S_IRUGO); |
| |
| static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; |
| module_param(ple_window, int, S_IRUGO); |
| |
| #define NR_AUTOLOAD_MSRS 8 |
| #define VMCS02_POOL_SIZE 1 |
| |
| struct vmcs { |
| u32 revision_id; |
| u32 abort; |
| char data[0]; |
| }; |
| |
| /* |
| * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also |
| * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs |
| * loaded on this CPU (so we can clear them if the CPU goes down). |
| */ |
| struct loaded_vmcs { |
| struct vmcs *vmcs; |
| int cpu; |
| int launched; |
| struct list_head loaded_vmcss_on_cpu_link; |
| }; |
| |
| struct shared_msr_entry { |
| unsigned index; |
| u64 data; |
| u64 mask; |
| }; |
| |
| /* |
| * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a |
| * single nested guest (L2), hence the name vmcs12. Any VMX implementation has |
| * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is |
| * stored in guest memory specified by VMPTRLD, but is opaque to the guest, |
| * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. |
| * More than one of these structures may exist, if L1 runs multiple L2 guests. |
| * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the |
| * underlying hardware which will be used to run L2. |
| * This structure is packed to ensure that its layout is identical across |
| * machines (necessary for live migration). |
| * If there are changes in this struct, VMCS12_REVISION must be changed. |
| */ |
| typedef u64 natural_width; |
| struct __packed vmcs12 { |
| /* According to the Intel spec, a VMCS region must start with the |
| * following two fields. Then follow implementation-specific data. |
| */ |
| u32 revision_id; |
| u32 abort; |
| |
| u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
| u32 padding[7]; /* room for future expansion */ |
| |
| u64 io_bitmap_a; |
| u64 io_bitmap_b; |
| u64 msr_bitmap; |
| u64 vm_exit_msr_store_addr; |
| u64 vm_exit_msr_load_addr; |
| u64 vm_entry_msr_load_addr; |
| u64 tsc_offset; |
| u64 virtual_apic_page_addr; |
| u64 apic_access_addr; |
| u64 ept_pointer; |
| u64 guest_physical_address; |
| u64 vmcs_link_pointer; |
| u64 guest_ia32_debugctl; |
| u64 guest_ia32_pat; |
| u64 guest_ia32_efer; |
| u64 guest_ia32_perf_global_ctrl; |
| u64 guest_pdptr0; |
| u64 guest_pdptr1; |
| u64 guest_pdptr2; |
| u64 guest_pdptr3; |
| u64 host_ia32_pat; |
| u64 host_ia32_efer; |
| u64 host_ia32_perf_global_ctrl; |
| u64 padding64[8]; /* room for future expansion */ |
| /* |
| * To allow migration of L1 (complete with its L2 guests) between |
| * machines of different natural widths (32 or 64 bit), we cannot have |
| * unsigned long fields with no explict size. We use u64 (aliased |
| * natural_width) instead. Luckily, x86 is little-endian. |
| */ |
| natural_width cr0_guest_host_mask; |
| natural_width cr4_guest_host_mask; |
| natural_width cr0_read_shadow; |
| natural_width cr4_read_shadow; |
| natural_width cr3_target_value0; |
| natural_width cr3_target_value1; |
| natural_width cr3_target_value2; |
| natural_width cr3_target_value3; |
| natural_width exit_qualification; |
| natural_width guest_linear_address; |
| natural_width guest_cr0; |
| natural_width guest_cr3; |
| natural_width guest_cr4; |
| natural_width guest_es_base; |
| natural_width guest_cs_base; |
| natural_width guest_ss_base; |
| natural_width guest_ds_base; |
| natural_width guest_fs_base; |
| natural_width guest_gs_base; |
| natural_width guest_ldtr_base; |
| natural_width guest_tr_base; |
| natural_width guest_gdtr_base; |
| natural_width guest_idtr_base; |
| natural_width guest_dr7; |
| natural_width guest_rsp; |
| natural_width guest_rip; |
| natural_width guest_rflags; |
| natural_width guest_pending_dbg_exceptions; |
| natural_width guest_sysenter_esp; |
| natural_width guest_sysenter_eip; |
| natural_width host_cr0; |
| natural_width host_cr3; |
| natural_width host_cr4; |
| natural_width host_fs_base; |
| natural_width host_gs_base; |
| natural_width host_tr_base; |
| natural_width host_gdtr_base; |
| natural_width host_idtr_base; |
| natural_width host_ia32_sysenter_esp; |
| natural_width host_ia32_sysenter_eip; |
| natural_width host_rsp; |
| natural_width host_rip; |
| natural_width paddingl[8]; /* room for future expansion */ |
| u32 pin_based_vm_exec_control; |
| u32 cpu_based_vm_exec_control; |
| u32 exception_bitmap; |
| u32 page_fault_error_code_mask; |
| u32 page_fault_error_code_match; |
| u32 cr3_target_count; |
| u32 vm_exit_controls; |
| u32 vm_exit_msr_store_count; |
| u32 vm_exit_msr_load_count; |
| u32 vm_entry_controls; |
| u32 vm_entry_msr_load_count; |
| u32 vm_entry_intr_info_field; |
| u32 vm_entry_exception_error_code; |
| u32 vm_entry_instruction_len; |
| u32 tpr_threshold; |
| u32 secondary_vm_exec_control; |
| u32 vm_instruction_error; |
| u32 vm_exit_reason; |
| u32 vm_exit_intr_info; |
| u32 vm_exit_intr_error_code; |
| u32 idt_vectoring_info_field; |
| u32 idt_vectoring_error_code; |
| u32 vm_exit_instruction_len; |
| u32 vmx_instruction_info; |
| u32 guest_es_limit; |
| u32 guest_cs_limit; |
| u32 guest_ss_limit; |
| u32 guest_ds_limit; |
| u32 guest_fs_limit; |
| u32 guest_gs_limit; |
| u32 guest_ldtr_limit; |
| u32 guest_tr_limit; |
| u32 guest_gdtr_limit; |
| u32 guest_idtr_limit; |
| u32 guest_es_ar_bytes; |
| u32 guest_cs_ar_bytes; |
| u32 guest_ss_ar_bytes; |
| u32 guest_ds_ar_bytes; |
| u32 guest_fs_ar_bytes; |
| u32 guest_gs_ar_bytes; |
| u32 guest_ldtr_ar_bytes; |
| u32 guest_tr_ar_bytes; |
| u32 guest_interruptibility_info; |
| u32 guest_activity_state; |
| u32 guest_sysenter_cs; |
| u32 host_ia32_sysenter_cs; |
| u32 padding32[8]; /* room for future expansion */ |
| u16 virtual_processor_id; |
| u16 guest_es_selector; |
| u16 guest_cs_selector; |
| u16 guest_ss_selector; |
| u16 guest_ds_selector; |
| u16 guest_fs_selector; |
| u16 guest_gs_selector; |
| u16 guest_ldtr_selector; |
| u16 guest_tr_selector; |
| u16 host_es_selector; |
| u16 host_cs_selector; |
| u16 host_ss_selector; |
| u16 host_ds_selector; |
| u16 host_fs_selector; |
| u16 host_gs_selector; |
| u16 host_tr_selector; |
| }; |
| |
| /* |
| * VMCS12_REVISION is an arbitrary id that should be changed if the content or |
| * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and |
| * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. |
| */ |
| #define VMCS12_REVISION 0x11e57ed0 |
| |
| /* |
| * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region |
| * and any VMCS region. Although only sizeof(struct vmcs12) are used by the |
| * current implementation, 4K are reserved to avoid future complications. |
| */ |
| #define VMCS12_SIZE 0x1000 |
| |
| /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
| struct vmcs02_list { |
| struct list_head list; |
| gpa_t vmptr; |
| struct loaded_vmcs vmcs02; |
| }; |
| |
| /* |
| * The nested_vmx structure is part of vcpu_vmx, and holds information we need |
| * for correct emulation of VMX (i.e., nested VMX) on this vcpu. |
| */ |
| struct nested_vmx { |
| /* Has the level1 guest done vmxon? */ |
| bool vmxon; |
| |
| /* The guest-physical address of the current VMCS L1 keeps for L2 */ |
| gpa_t current_vmptr; |
| /* The host-usable pointer to the above */ |
| struct page *current_vmcs12_page; |
| struct vmcs12 *current_vmcs12; |
| |
| /* vmcs02_list cache of VMCSs recently used to run L2 guests */ |
| struct list_head vmcs02_pool; |
| int vmcs02_num; |
| u64 vmcs01_tsc_offset; |
| /* L2 must run next, and mustn't decide to exit to L1. */ |
| bool nested_run_pending; |
| /* |
| * Guest pages referred to in vmcs02 with host-physical pointers, so |
| * we must keep them pinned while L2 runs. |
| */ |
| struct page *apic_access_page; |
| }; |
| |
| struct vcpu_vmx { |
| struct kvm_vcpu vcpu; |
| unsigned long host_rsp; |
| u8 fail; |
| u8 cpl; |
| bool nmi_known_unmasked; |
| u32 exit_intr_info; |
| u32 idt_vectoring_info; |
| ulong rflags; |
| struct shared_msr_entry *guest_msrs; |
| int nmsrs; |
| int save_nmsrs; |
| #ifdef CONFIG_X86_64 |
| u64 msr_host_kernel_gs_base; |
| u64 msr_guest_kernel_gs_base; |
| #endif |
| /* |
| * loaded_vmcs points to the VMCS currently used in this vcpu. For a |
| * non-nested (L1) guest, it always points to vmcs01. For a nested |
| * guest (L2), it points to a different VMCS. |
| */ |
| struct loaded_vmcs vmcs01; |
| struct loaded_vmcs *loaded_vmcs; |
| bool __launched; /* temporary, used in vmx_vcpu_run */ |
| struct msr_autoload { |
| unsigned nr; |
| struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; |
| struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; |
| } msr_autoload; |
| struct { |
| int loaded; |
| u16 fs_sel, gs_sel, ldt_sel; |
| int gs_ldt_reload_needed; |
| int fs_reload_needed; |
| } host_state; |
| struct { |
| int vm86_active; |
| ulong save_rflags; |
| struct kvm_save_segment { |
| u16 selector; |
| unsigned long base; |
| u32 limit; |
| u32 ar; |
| } tr, es, ds, fs, gs; |
| } rmode; |
| struct { |
| u32 bitmask; /* 4 bits per segment (1 bit per field) */ |
| struct kvm_save_segment seg[8]; |
| } segment_cache; |
| int vpid; |
| bool emulation_required; |
| |
| /* Support for vnmi-less CPUs */ |
| int soft_vnmi_blocked; |
| ktime_t entry_time; |
| s64 vnmi_blocked_time; |
| u32 exit_reason; |
| |
| bool rdtscp_enabled; |
| |
| /* Support for a guest hypervisor (nested VMX) */ |
| struct nested_vmx nested; |
| }; |
| |
| enum segment_cache_field { |
| SEG_FIELD_SEL = 0, |
| SEG_FIELD_BASE = 1, |
| SEG_FIELD_LIMIT = 2, |
| SEG_FIELD_AR = 3, |
| |
| SEG_FIELD_NR = 4 |
| }; |
| |
| static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
| { |
| return container_of(vcpu, struct vcpu_vmx, vcpu); |
| } |
| |
| #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
| #define FIELD(number, name) [number] = VMCS12_OFFSET(name) |
| #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ |
| [number##_HIGH] = VMCS12_OFFSET(name)+4 |
| |
| static unsigned short vmcs_field_to_offset_table[] = { |
| FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
| FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
| FIELD(GUEST_CS_SELECTOR, guest_cs_selector), |
| FIELD(GUEST_SS_SELECTOR, guest_ss_selector), |
| FIELD(GUEST_DS_SELECTOR, guest_ds_selector), |
| FIELD(GUEST_FS_SELECTOR, guest_fs_selector), |
| FIELD(GUEST_GS_SELECTOR, guest_gs_selector), |
| FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), |
| FIELD(GUEST_TR_SELECTOR, guest_tr_selector), |
| FIELD(HOST_ES_SELECTOR, host_es_selector), |
| FIELD(HOST_CS_SELECTOR, host_cs_selector), |
| FIELD(HOST_SS_SELECTOR, host_ss_selector), |
| FIELD(HOST_DS_SELECTOR, host_ds_selector), |
| FIELD(HOST_FS_SELECTOR, host_fs_selector), |
| FIELD(HOST_GS_SELECTOR, host_gs_selector), |
| FIELD(HOST_TR_SELECTOR, host_tr_selector), |
| FIELD64(IO_BITMAP_A, io_bitmap_a), |
| FIELD64(IO_BITMAP_B, io_bitmap_b), |
| FIELD64(MSR_BITMAP, msr_bitmap), |
| FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), |
| FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), |
| FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), |
| FIELD64(TSC_OFFSET, tsc_offset), |
| FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), |
| FIELD64(APIC_ACCESS_ADDR, apic_access_addr), |
| FIELD64(EPT_POINTER, ept_pointer), |
| FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
| FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), |
| FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
| FIELD64(GUEST_IA32_PAT, guest_ia32_pat), |
| FIELD64(GUEST_IA32_EFER, guest_ia32_efer), |
| FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), |
| FIELD64(GUEST_PDPTR0, guest_pdptr0), |
| FIELD64(GUEST_PDPTR1, guest_pdptr1), |
| FIELD64(GUEST_PDPTR2, guest_pdptr2), |
| FIELD64(GUEST_PDPTR3, guest_pdptr3), |
| FIELD64(HOST_IA32_PAT, host_ia32_pat), |
| FIELD64(HOST_IA32_EFER, host_ia32_efer), |
| FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), |
| FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), |
| FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), |
| FIELD(EXCEPTION_BITMAP, exception_bitmap), |
| FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), |
| FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), |
| FIELD(CR3_TARGET_COUNT, cr3_target_count), |
| FIELD(VM_EXIT_CONTROLS, vm_exit_controls), |
| FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), |
| FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), |
| FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), |
| FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), |
| FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), |
| FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), |
| FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), |
| FIELD(TPR_THRESHOLD, tpr_threshold), |
| FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), |
| FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), |
| FIELD(VM_EXIT_REASON, vm_exit_reason), |
| FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), |
| FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), |
| FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), |
| FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), |
| FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), |
| FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), |
| FIELD(GUEST_ES_LIMIT, guest_es_limit), |
| FIELD(GUEST_CS_LIMIT, guest_cs_limit), |
| FIELD(GUEST_SS_LIMIT, guest_ss_limit), |
| FIELD(GUEST_DS_LIMIT, guest_ds_limit), |
| FIELD(GUEST_FS_LIMIT, guest_fs_limit), |
| FIELD(GUEST_GS_LIMIT, guest_gs_limit), |
| FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), |
| FIELD(GUEST_TR_LIMIT, guest_tr_limit), |
| FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), |
| FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), |
| FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), |
| FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), |
| FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), |
| FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), |
| FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), |
| FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), |
| FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), |
| FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), |
| FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), |
| FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), |
| FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), |
| FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), |
| FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
| FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), |
| FIELD(CR0_READ_SHADOW, cr0_read_shadow), |
| FIELD(CR4_READ_SHADOW, cr4_read_shadow), |
| FIELD(CR3_TARGET_VALUE0, cr3_target_value0), |
| FIELD(CR3_TARGET_VALUE1, cr3_target_value1), |
| FIELD(CR3_TARGET_VALUE2, cr3_target_value2), |
| FIELD(CR3_TARGET_VALUE3, cr3_target_value3), |
| FIELD(EXIT_QUALIFICATION, exit_qualification), |
| FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), |
| FIELD(GUEST_CR0, guest_cr0), |
| FIELD(GUEST_CR3, guest_cr3), |
| FIELD(GUEST_CR4, guest_cr4), |
| FIELD(GUEST_ES_BASE, guest_es_base), |
| FIELD(GUEST_CS_BASE, guest_cs_base), |
| FIELD(GUEST_SS_BASE, guest_ss_base), |
| FIELD(GUEST_DS_BASE, guest_ds_base), |
| FIELD(GUEST_FS_BASE, guest_fs_base), |
| FIELD(GUEST_GS_BASE, guest_gs_base), |
| FIELD(GUEST_LDTR_BASE, guest_ldtr_base), |
| FIELD(GUEST_TR_BASE, guest_tr_base), |
| FIELD(GUEST_GDTR_BASE, guest_gdtr_base), |
| FIELD(GUEST_IDTR_BASE, guest_idtr_base), |
| FIELD(GUEST_DR7, guest_dr7), |
| FIELD(GUEST_RSP, guest_rsp), |
| FIELD(GUEST_RIP, guest_rip), |
| FIELD(GUEST_RFLAGS, guest_rflags), |
| FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), |
| FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), |
| FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), |
| FIELD(HOST_CR0, host_cr0), |
| FIELD(HOST_CR3, host_cr3), |
| FIELD(HOST_CR4, host_cr4), |
| FIELD(HOST_FS_BASE, host_fs_base), |
| FIELD(HOST_GS_BASE, host_gs_base), |
| FIELD(HOST_TR_BASE, host_tr_base), |
| FIELD(HOST_GDTR_BASE, host_gdtr_base), |
| FIELD(HOST_IDTR_BASE, host_idtr_base), |
| FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), |
| FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), |
| FIELD(HOST_RSP, host_rsp), |
| FIELD(HOST_RIP, host_rip), |
| }; |
| static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table); |
| |
| static inline short vmcs_field_to_offset(unsigned long field) |
| { |
| if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0) |
| return -1; |
| return vmcs_field_to_offset_table[field]; |
| } |
| |
| static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
| { |
| return to_vmx(vcpu)->nested.current_vmcs12; |
| } |
| |
| static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) |
| { |
| struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT); |
| if (is_error_page(page)) { |
| kvm_release_page_clean(page); |
| return NULL; |
| } |
| return page; |
| } |
| |
| static void nested_release_page(struct page *page) |
| { |
| kvm_release_page_dirty(page); |
| } |
| |
| static void nested_release_page_clean(struct page *page) |
| { |
| kvm_release_page_clean(page); |
| } |
| |
| static u64 construct_eptp(unsigned long root_hpa); |
| static void kvm_cpu_vmxon(u64 addr); |
| static void kvm_cpu_vmxoff(void); |
| static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
| static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
| |
| static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
| static DEFINE_PER_CPU(struct vmcs *, current_vmcs); |
| /* |
| * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed |
| * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. |
| */ |
| static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); |
| static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
| |
| static unsigned long *vmx_io_bitmap_a; |
| static unsigned long *vmx_io_bitmap_b; |
| static unsigned long *vmx_msr_bitmap_legacy; |
| static unsigned long *vmx_msr_bitmap_longmode; |
| |
| static bool cpu_has_load_ia32_efer; |
| static bool cpu_has_load_perf_global_ctrl; |
| |
| static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
| static DEFINE_SPINLOCK(vmx_vpid_lock); |
| |
| static struct vmcs_config { |
| int size; |
| int order; |
| u32 revision_id; |
| u32 pin_based_exec_ctrl; |
| u32 cpu_based_exec_ctrl; |
| u32 cpu_based_2nd_exec_ctrl; |
| u32 vmexit_ctrl; |
| u32 vmentry_ctrl; |
| } vmcs_config; |
| |
| static struct vmx_capability { |
| u32 ept; |
| u32 vpid; |
| } vmx_capability; |
| |
| #define VMX_SEGMENT_FIELD(seg) \ |
| [VCPU_SREG_##seg] = { \ |
| .selector = GUEST_##seg##_SELECTOR, \ |
| .base = GUEST_##seg##_BASE, \ |
| .limit = GUEST_##seg##_LIMIT, \ |
| .ar_bytes = GUEST_##seg##_AR_BYTES, \ |
| } |
| |
| static struct kvm_vmx_segment_field { |
| unsigned selector; |
| unsigned base; |
| unsigned limit; |
| unsigned ar_bytes; |
| } kvm_vmx_segment_fields[] = { |
| VMX_SEGMENT_FIELD(CS), |
| VMX_SEGMENT_FIELD(DS), |
| VMX_SEGMENT_FIELD(ES), |
| VMX_SEGMENT_FIELD(FS), |
| VMX_SEGMENT_FIELD(GS), |
| VMX_SEGMENT_FIELD(SS), |
| VMX_SEGMENT_FIELD(TR), |
| VMX_SEGMENT_FIELD(LDTR), |
| }; |
| |
| static u64 host_efer; |
| |
| static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
| |
| /* |
| * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
| * away by decrementing the array size. |
| */ |
| static const u32 vmx_msr_index[] = { |
| #ifdef CONFIG_X86_64 |
| MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
| #endif |
| MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
| }; |
| #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
| |
| static inline bool is_page_fault(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | |
| INTR_INFO_VALID_MASK)) == |
| (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
| } |
| |
| static inline bool is_no_device(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | |
| INTR_INFO_VALID_MASK)) == |
| (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
| } |
| |
| static inline bool is_invalid_opcode(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | |
| INTR_INFO_VALID_MASK)) == |
| (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
| } |
| |
| static inline bool is_external_interrupt(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) |
| == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); |
| } |
| |
| static inline bool is_machine_check(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | |
| INTR_INFO_VALID_MASK)) == |
| (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); |
| } |
| |
| static inline bool cpu_has_vmx_msr_bitmap(void) |
| { |
| return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
| } |
| |
| static inline bool cpu_has_vmx_tpr_shadow(void) |
| { |
| return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
| } |
| |
| static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
| { |
| return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
| } |
| |
| static inline bool cpu_has_secondary_exec_ctrls(void) |
| { |
| return vmcs_config.cpu_based_exec_ctrl & |
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
| } |
| |
| static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
| } |
| |
| static inline bool cpu_has_vmx_flexpriority(void) |
| { |
| return cpu_has_vmx_tpr_shadow() && |
| cpu_has_vmx_virtualize_apic_accesses(); |
| } |
| |
| static inline bool cpu_has_vmx_ept_execute_only(void) |
| { |
| return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_eptp_uncacheable(void) |
| { |
| return vmx_capability.ept & VMX_EPTP_UC_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_eptp_writeback(void) |
| { |
| return vmx_capability.ept & VMX_EPTP_WB_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_ept_2m_page(void) |
| { |
| return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_ept_1g_page(void) |
| { |
| return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_ept_4levels(void) |
| { |
| return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_invept_individual_addr(void) |
| { |
| return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_invept_context(void) |
| { |
| return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_invept_global(void) |
| { |
| return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_invvpid_single(void) |
| { |
| return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_invvpid_global(void) |
| { |
| return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; |
| } |
| |
| static inline bool cpu_has_vmx_ept(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_ENABLE_EPT; |
| } |
| |
| static inline bool cpu_has_vmx_unrestricted_guest(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_UNRESTRICTED_GUEST; |
| } |
| |
| static inline bool cpu_has_vmx_ple(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_PAUSE_LOOP_EXITING; |
| } |
| |
| static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
| { |
| return flexpriority_enabled && irqchip_in_kernel(kvm); |
| } |
| |
| static inline bool cpu_has_vmx_vpid(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_ENABLE_VPID; |
| } |
| |
| static inline bool cpu_has_vmx_rdtscp(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_RDTSCP; |
| } |
| |
| static inline bool cpu_has_virtual_nmis(void) |
| { |
| return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; |
| } |
| |
| static inline bool cpu_has_vmx_wbinvd_exit(void) |
| { |
| return vmcs_config.cpu_based_2nd_exec_ctrl & |
| SECONDARY_EXEC_WBINVD_EXITING; |
| } |
| |
| static inline bool report_flexpriority(void) |
| { |
| return flexpriority_enabled; |
| } |
| |
| static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
| { |
| return vmcs12->cpu_based_vm_exec_control & bit; |
| } |
| |
| static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) |
| { |
| return (vmcs12->cpu_based_vm_exec_control & |
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
| (vmcs12->secondary_vm_exec_control & bit); |
| } |
| |
| static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12, |
| struct kvm_vcpu *vcpu) |
| { |
| return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; |
| } |
| |
| static inline bool is_exception(u32 intr_info) |
| { |
| return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) |
| == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); |
| } |
| |
| static void nested_vmx_vmexit(struct kvm_vcpu *vcpu); |
| static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
| struct vmcs12 *vmcs12, |
| u32 reason, unsigned long qualification); |
| |
| static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
| { |
| int i; |
| |
| for (i = 0; i < vmx->nmsrs; ++i) |
| if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
| return i; |
| return -1; |
| } |
| |
| static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
| { |
| struct { |
| u64 vpid : 16; |
| u64 rsvd : 48; |
| u64 gva; |
| } operand = { vpid, 0, gva }; |
| |
| asm volatile (__ex(ASM_VMX_INVVPID) |
| /* CF==1 or ZF==1 --> rc = -1 */ |
| "; ja 1f ; ud2 ; 1:" |
| : : "a"(&operand), "c"(ext) : "cc", "memory"); |
| } |
| |
| static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
| { |
| struct { |
| u64 eptp, gpa; |
| } operand = {eptp, gpa}; |
| |
| asm volatile (__ex(ASM_VMX_INVEPT) |
| /* CF==1 or ZF==1 --> rc = -1 */ |
| "; ja 1f ; ud2 ; 1:\n" |
| : : "a" (&operand), "c" (ext) : "cc", "memory"); |
| } |
| |
| static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
| { |
| int i; |
| |
| i = __find_msr_index(vmx, msr); |
| if (i >= 0) |
| return &vmx->guest_msrs[i]; |
| return NULL; |
| } |
| |
| static void vmcs_clear(struct vmcs *vmcs) |
| { |
| u64 phys_addr = __pa(vmcs); |
| u8 error; |
| |
| asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
| : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
| : "cc", "memory"); |
| if (error) |
| printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", |
| vmcs, phys_addr); |
| } |
| |
| static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
| { |
| vmcs_clear(loaded_vmcs->vmcs); |
| loaded_vmcs->cpu = -1; |
| loaded_vmcs->launched = 0; |
| } |
| |
| static void vmcs_load(struct vmcs *vmcs) |
| { |
| u64 phys_addr = __pa(vmcs); |
| u8 error; |
| |
| asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
| : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
| : "cc", "memory"); |
| if (error) |
| printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
| vmcs, phys_addr); |
| } |
| |
| static void __loaded_vmcs_clear(void *arg) |
| { |
| struct loaded_vmcs *loaded_vmcs = arg; |
| int cpu = raw_smp_processor_id(); |
| |
| if (loaded_vmcs->cpu != cpu) |
| return; /* vcpu migration can race with cpu offline */ |
| if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) |
| per_cpu(current_vmcs, cpu) = NULL; |
| list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
| loaded_vmcs_init(loaded_vmcs); |
| } |
| |
| static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
| { |
| if (loaded_vmcs->cpu != -1) |
| smp_call_function_single( |
| loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1); |
| } |
| |
| static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
| { |
| if (vmx->vpid == 0) |
| return; |
| |
| if (cpu_has_vmx_invvpid_single()) |
| __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); |
| } |
| |
| static inline void vpid_sync_vcpu_global(void) |
| { |
| if (cpu_has_vmx_invvpid_global()) |
| __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); |
| } |
| |
| static inline void vpid_sync_context(struct vcpu_vmx *vmx) |
| { |
| if (cpu_has_vmx_invvpid_single()) |
| vpid_sync_vcpu_single(vmx); |
| else |
| vpid_sync_vcpu_global(); |
| } |
| |
| static inline void ept_sync_global(void) |
| { |
| if (cpu_has_vmx_invept_global()) |
| __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
| } |
| |
| static inline void ept_sync_context(u64 eptp) |
| { |
| if (enable_ept) { |
| if (cpu_has_vmx_invept_context()) |
| __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); |
| else |
| ept_sync_global(); |
| } |
| } |
| |
| static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) |
| { |
| if (enable_ept) { |
| if (cpu_has_vmx_invept_individual_addr()) |
| __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, |
| eptp, gpa); |
| else |
| ept_sync_context(eptp); |
| } |
| } |
| |
| static __always_inline unsigned long vmcs_readl(unsigned long field) |
| { |
| unsigned long value; |
| |
| asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
| : "=a"(value) : "d"(field) : "cc"); |
| return value; |
| } |
| |
| static __always_inline u16 vmcs_read16(unsigned long field) |
| { |
| return vmcs_readl(field); |
| } |
| |
| static __always_inline u32 vmcs_read32(unsigned long field) |
| { |
| return vmcs_readl(field); |
| } |
| |
| static __always_inline u64 vmcs_read64(unsigned long field) |
| { |
| #ifdef CONFIG_X86_64 |
| return vmcs_readl(field); |
| #else |
| return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); |
| #endif |
| } |
| |
| static noinline void vmwrite_error(unsigned long field, unsigned long value) |
| { |
| printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", |
| field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); |
| dump_stack(); |
| } |
| |
| static void vmcs_writel(unsigned long field, unsigned long value) |
| { |
| u8 error; |
| |
| asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
| : "=q"(error) : "a"(value), "d"(field) : "cc"); |
| if (unlikely(error)) |
| vmwrite_error(field, value); |
| } |
| |
| static void vmcs_write16(unsigned long field, u16 value) |
| { |
| vmcs_writel(field, value); |
| } |
| |
| static void vmcs_write32(unsigned long field, u32 value) |
| { |
| vmcs_writel(field, value); |
| } |
| |
| static void vmcs_write64(unsigned long field, u64 value) |
| { |
| vmcs_writel(field, value); |
| #ifndef CONFIG_X86_64 |
| asm volatile (""); |
| vmcs_writel(field+1, value >> 32); |
| #endif |
| } |
| |
| static void vmcs_clear_bits(unsigned long field, u32 mask) |
| { |
| vmcs_writel(field, vmcs_readl(field) & ~mask); |
| } |
| |
| static void vmcs_set_bits(unsigned long field, u32 mask) |
| { |
| vmcs_writel(field, vmcs_readl(field) | mask); |
| } |
| |
| static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
| { |
| vmx->segment_cache.bitmask = 0; |
| } |
| |
| static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, |
| unsigned field) |
| { |
| bool ret; |
| u32 mask = 1 << (seg * SEG_FIELD_NR + field); |
| |
| if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { |
| vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); |
| vmx->segment_cache.bitmask = 0; |
| } |
| ret = vmx->segment_cache.bitmask & mask; |
| vmx->segment_cache.bitmask |= mask; |
| return ret; |
| } |
| |
| static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) |
| { |
| u16 *p = &vmx->segment_cache.seg[seg].selector; |
| |
| if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) |
| *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); |
| return *p; |
| } |
| |
| static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) |
| { |
| ulong *p = &vmx->segment_cache.seg[seg].base; |
| |
| if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) |
| *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); |
| return *p; |
| } |
| |
| static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) |
| { |
| u32 *p = &vmx->segment_cache.seg[seg].limit; |
| |
| if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) |
| *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); |
| return *p; |
| } |
| |
| static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) |
| { |
| u32 *p = &vmx->segment_cache.seg[seg].ar; |
| |
| if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) |
| *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); |
| return *p; |
| } |
| |
| static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
| { |
| u32 eb; |
| |
| eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
| (1u << NM_VECTOR) | (1u << DB_VECTOR); |
| if ((vcpu->guest_debug & |
| (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == |
| (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) |
| eb |= 1u << BP_VECTOR; |
| if (to_vmx(vcpu)->rmode.vm86_active) |
| eb = ~0; |
| if (enable_ept) |
| eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
| if (vcpu->fpu_active) |
| eb &= ~(1u << NM_VECTOR); |
| |
| /* When we are running a nested L2 guest and L1 specified for it a |
| * certain exception bitmap, we must trap the same exceptions and pass |
| * them to L1. When running L2, we will only handle the exceptions |
| * specified above if L1 did not want them. |
| */ |
| if (is_guest_mode(vcpu)) |
| eb |= get_vmcs12(vcpu)->exception_bitmap; |
| |
| vmcs_write32(EXCEPTION_BITMAP, eb); |
| } |
| |
| static void clear_atomic_switch_msr_special(unsigned long entry, |
| unsigned long exit) |
| { |
| vmcs_clear_bits(VM_ENTRY_CONTROLS, entry); |
| vmcs_clear_bits(VM_EXIT_CONTROLS, exit); |
| } |
| |
| static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
| { |
| unsigned i; |
| struct msr_autoload *m = &vmx->msr_autoload; |
| |
| switch (msr) { |
| case MSR_EFER: |
| if (cpu_has_load_ia32_efer) { |
| clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER, |
| VM_EXIT_LOAD_IA32_EFER); |
| return; |
| } |
| break; |
| case MSR_CORE_PERF_GLOBAL_CTRL: |
| if (cpu_has_load_perf_global_ctrl) { |
| clear_atomic_switch_msr_special( |
| VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
| VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); |
| return; |
| } |
| break; |
| } |
| |
| for (i = 0; i < m->nr; ++i) |
| if (m->guest[i].index == msr) |
| break; |
| |
| if (i == m->nr) |
| return; |
| --m->nr; |
| m->guest[i] = m->guest[m->nr]; |
| m->host[i] = m->host[m->nr]; |
| vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); |
| vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); |
| } |
| |
| static void add_atomic_switch_msr_special(unsigned long entry, |
| unsigned long exit, unsigned long guest_val_vmcs, |
| unsigned long host_val_vmcs, u64 guest_val, u64 host_val) |
| { |
| vmcs_write64(guest_val_vmcs, guest_val); |
| vmcs_write64(host_val_vmcs, host_val); |
| vmcs_set_bits(VM_ENTRY_CONTROLS, entry); |
| vmcs_set_bits(VM_EXIT_CONTROLS, exit); |
| } |
| |
| static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
| u64 guest_val, u64 host_val) |
| { |
| unsigned i; |
| struct msr_autoload *m = &vmx->msr_autoload; |
| |
| switch (msr) { |
| case MSR_EFER: |
| if (cpu_has_load_ia32_efer) { |
| add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER, |
| VM_EXIT_LOAD_IA32_EFER, |
| GUEST_IA32_EFER, |
| HOST_IA32_EFER, |
| guest_val, host_val); |
| return; |
| } |
| break; |
| case MSR_CORE_PERF_GLOBAL_CTRL: |
| if (cpu_has_load_perf_global_ctrl) { |
| add_atomic_switch_msr_special( |
| VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
| VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, |
| GUEST_IA32_PERF_GLOBAL_CTRL, |
| HOST_IA32_PERF_GLOBAL_CTRL, |
| guest_val, host_val); |
| return; |
| } |
| break; |
| } |
| |
| for (i = 0; i < m->nr; ++i) |
| if (m->guest[i].index == msr) |
| break; |
| |
| if (i == NR_AUTOLOAD_MSRS) { |
| printk_once(KERN_WARNING"Not enough mst switch entries. " |
| "Can't add msr %x\n", msr); |
| return; |
| } else if (i == m->nr) { |
| ++m->nr; |
| vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); |
| vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); |
| } |
| |
| m->guest[i].index = msr; |
| m->guest[i].value = guest_val; |
| m->host[i].index = msr; |
| m->host[i].value = host_val; |
| } |
| |
| static void reload_tss(void) |
| { |
| /* |
| * VT restores TR but not its size. Useless. |
| */ |
| struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
| struct desc_struct *descs; |
| |
| descs = (void *)gdt->address; |
| descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
| load_TR_desc(); |
| } |
| |
| static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
| { |
| u64 guest_efer; |
| u64 ignore_bits; |
| |
| guest_efer = vmx->vcpu.arch.efer; |
| |
| /* |
| * NX is emulated; LMA and LME handled by hardware; SCE meaninless |
| * outside long mode |
| */ |
| ignore_bits = EFER_NX | EFER_SCE; |
| #ifdef CONFIG_X86_64 |
| ignore_bits |= EFER_LMA | EFER_LME; |
| /* SCE is meaningful only in long mode on Intel */ |
| if (guest_efer & EFER_LMA) |
| ignore_bits &= ~(u64)EFER_SCE; |
| #endif |
| guest_efer &= ~ignore_bits; |
| guest_efer |= host_efer & ignore_bits; |
| vmx->guest_msrs[efer_offset].data = guest_efer; |
| vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
| |
| clear_atomic_switch_msr(vmx, MSR_EFER); |
| /* On ept, can't emulate nx, and must switch nx atomically */ |
| if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { |
| guest_efer = vmx->vcpu.arch.efer; |
| if (!(guest_efer & EFER_LMA)) |
| guest_efer &= ~EFER_LME; |
| add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); |
| return false; |
| } |
| |
| return true; |
| } |
| |
| static unsigned long segment_base(u16 selector) |
| { |
| struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
| struct desc_struct *d; |
| unsigned long table_base; |
| unsigned long v; |
| |
| if (!(selector & ~3)) |
| return 0; |
| |
| table_base = gdt->address; |
| |
| if (selector & 4) { /* from ldt */ |
| u16 ldt_selector = kvm_read_ldt(); |
| |
| if (!(ldt_selector & ~3)) |
| return 0; |
| |
| table_base = segment_base(ldt_selector); |
| } |
| d = (struct desc_struct *)(table_base + (selector & ~7)); |
| v = get_desc_base(d); |
| #ifdef CONFIG_X86_64 |
| if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
| v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; |
| #endif |
| return v; |
| } |
| |
| static inline unsigned long kvm_read_tr_base(void) |
| { |
| u16 tr; |
| asm("str %0" : "=g"(tr)); |
| return segment_base(tr); |
| } |
| |
| static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| int i; |
| |
| if (vmx->host_state.loaded) |
| return; |
| |
| vmx->host_state.loaded = 1; |
| /* |
| * Set host fs and gs selectors. Unfortunately, 22.2.3 does not |
| * allow segment selectors with cpl > 0 or ti == 1. |
| */ |
| vmx->host_state.ldt_sel = kvm_read_ldt(); |
| vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
| savesegment(fs, vmx->host_state.fs_sel); |
| if (!(vmx->host_state.fs_sel & 7)) { |
| vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
| vmx->host_state.fs_reload_needed = 0; |
| } else { |
| vmcs_write16(HOST_FS_SELECTOR, 0); |
| vmx->host_state.fs_reload_needed = 1; |
| } |
| savesegment(gs, vmx->host_state.gs_sel); |
| if (!(vmx->host_state.gs_sel & 7)) |
| vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); |
| else { |
| vmcs_write16(HOST_GS_SELECTOR, 0); |
| vmx->host_state.gs_ldt_reload_needed = 1; |
| } |
| |
| #ifdef CONFIG_X86_64 |
| vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); |
| vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); |
| #else |
| vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
| vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); |
| #endif |
| |
| #ifdef CONFIG_X86_64 |
| rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
| if (is_long_mode(&vmx->vcpu)) |
| wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
| #endif |
| for (i = 0; i < vmx->save_nmsrs; ++i) |
| kvm_set_shared_msr(vmx->guest_msrs[i].index, |
| vmx->guest_msrs[i].data, |
| vmx->guest_msrs[i].mask); |
| } |
| |
| static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
| { |
| if (!vmx->host_state.loaded) |
| return; |
| |
| ++vmx->vcpu.stat.host_state_reload; |
| vmx->host_state.loaded = 0; |
| #ifdef CONFIG_X86_64 |
| if (is_long_mode(&vmx->vcpu)) |
| rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
| #endif |
| if (vmx->host_state.gs_ldt_reload_needed) { |
| kvm_load_ldt(vmx->host_state.ldt_sel); |
| #ifdef CONFIG_X86_64 |
| load_gs_index(vmx->host_state.gs_sel); |
| #else |
| loadsegment(gs, vmx->host_state.gs_sel); |
| #endif |
| } |
| if (vmx->host_state.fs_reload_needed) |
| loadsegment(fs, vmx->host_state.fs_sel); |
| reload_tss(); |
| #ifdef CONFIG_X86_64 |
| wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
| #endif |
| if (__thread_has_fpu(current)) |
| clts(); |
| load_gdt(&__get_cpu_var(host_gdt)); |
| } |
| |
| static void vmx_load_host_state(struct vcpu_vmx *vmx) |
| { |
| preempt_disable(); |
| __vmx_load_host_state(vmx); |
| preempt_enable(); |
| } |
| |
| /* |
| * Switches to specified vcpu, until a matching vcpu_put(), but assumes |
| * vcpu mutex is already taken. |
| */ |
| static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
| |
| if (!vmm_exclusive) |
| kvm_cpu_vmxon(phys_addr); |
| else if (vmx->loaded_vmcs->cpu != cpu) |
| loaded_vmcs_clear(vmx->loaded_vmcs); |
| |
| if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
| per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; |
| vmcs_load(vmx->loaded_vmcs->vmcs); |
| } |
| |
| if (vmx->loaded_vmcs->cpu != cpu) { |
| struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
| unsigned long sysenter_esp; |
| |
| kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
| local_irq_disable(); |
| list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
| &per_cpu(loaded_vmcss_on_cpu, cpu)); |
| local_irq_enable(); |
| |
| /* |
| * Linux uses per-cpu TSS and GDT, so set these when switching |
| * processors. |
| */ |
| vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
| vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
| |
| rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
| vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ |
| vmx->loaded_vmcs->cpu = cpu; |
| } |
| } |
| |
| static void vmx_vcpu_put(struct kvm_vcpu *vcpu) |
| { |
| __vmx_load_host_state(to_vmx(vcpu)); |
| if (!vmm_exclusive) { |
| __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
| vcpu->cpu = -1; |
| kvm_cpu_vmxoff(); |
| } |
| } |
| |
| static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
| { |
| ulong cr0; |
| |
| if (vcpu->fpu_active) |
| return; |
| vcpu->fpu_active = 1; |
| cr0 = vmcs_readl(GUEST_CR0); |
| cr0 &= ~(X86_CR0_TS | X86_CR0_MP); |
| cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); |
| vmcs_writel(GUEST_CR0, cr0); |
| update_exception_bitmap(vcpu); |
| vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
| if (is_guest_mode(vcpu)) |
| vcpu->arch.cr0_guest_owned_bits &= |
| ~get_vmcs12(vcpu)->cr0_guest_host_mask; |
| vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
| } |
| |
| static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
| |
| /* |
| * Return the cr0 value that a nested guest would read. This is a combination |
| * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by |
| * its hypervisor (cr0_read_shadow). |
| */ |
| static inline unsigned long nested_read_cr0(struct vmcs12 *fields) |
| { |
| return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | |
| (fields->cr0_read_shadow & fields->cr0_guest_host_mask); |
| } |
| static inline unsigned long nested_read_cr4(struct vmcs12 *fields) |
| { |
| return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | |
| (fields->cr4_read_shadow & fields->cr4_guest_host_mask); |
| } |
| |
| static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
| { |
| /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
| * set this *before* calling this function. |
| */ |
| vmx_decache_cr0_guest_bits(vcpu); |
| vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
| update_exception_bitmap(vcpu); |
| vcpu->arch.cr0_guest_owned_bits = 0; |
| vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
| if (is_guest_mode(vcpu)) { |
| /* |
| * L1's specified read shadow might not contain the TS bit, |
| * so now that we turned on shadowing of this bit, we need to |
| * set this bit of the shadow. Like in nested_vmx_run we need |
| * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet |
| * up-to-date here because we just decached cr0.TS (and we'll |
| * only update vmcs12->guest_cr0 on nested exit). |
| */ |
| struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
| vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | |
| (vcpu->arch.cr0 & X86_CR0_TS); |
| vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); |
| } else |
| vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); |
| } |
| |
| static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
| { |
| unsigned long rflags, save_rflags; |
| |
| if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
| __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
| rflags = vmcs_readl(GUEST_RFLAGS); |
| if (to_vmx(vcpu)->rmode.vm86_active) { |
| rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
| save_rflags = to_vmx(vcpu)->rmode.save_rflags; |
| rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; |
| } |
| to_vmx(vcpu)->rflags = rflags; |
| } |
| return to_vmx(vcpu)->rflags; |
| } |
| |
| static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
| { |
| __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
| __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
| to_vmx(vcpu)->rflags = rflags; |
| if (to_vmx(vcpu)->rmode.vm86_active) { |
| to_vmx(vcpu)->rmode.save_rflags = rflags; |
| rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
| } |
| vmcs_writel(GUEST_RFLAGS, rflags); |
| } |
| |
| static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
| { |
| u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); |
| int ret = 0; |
| |
| if (interruptibility & GUEST_INTR_STATE_STI) |
| ret |= KVM_X86_SHADOW_INT_STI; |
| if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
| ret |= KVM_X86_SHADOW_INT_MOV_SS; |
| |
| return ret & mask; |
| } |
| |
| static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
| { |
| u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); |
| u32 interruptibility = interruptibility_old; |
| |
| interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); |
| |
| if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
| interruptibility |= GUEST_INTR_STATE_MOV_SS; |
| else if (mask & KVM_X86_SHADOW_INT_STI) |
| interruptibility |= GUEST_INTR_STATE_STI; |
| |
| if ((interruptibility != interruptibility_old)) |
| vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); |
| } |
| |
| static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
| { |
| unsigned long rip; |
| |
| rip = kvm_rip_read(vcpu); |
| rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
| kvm_rip_write(vcpu, rip); |
| |
| /* skipping an emulated instruction also counts */ |
| vmx_set_interrupt_shadow(vcpu, 0); |
| } |
| |
| static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
| { |
| /* Ensure that we clear the HLT state in the VMCS. We don't need to |
| * explicitly skip the instruction because if the HLT state is set, then |
| * the instruction is already executing and RIP has already been |
| * advanced. */ |
| if (!yield_on_hlt && |
| vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) |
| vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
| } |
| |
| /* |
| * KVM wants to inject page-faults which it got to the guest. This function |
| * checks whether in a nested guest, we need to inject them to L1 or L2. |
| * This function assumes it is called with the exit reason in vmcs02 being |
| * a #PF exception (this is the only case in which KVM injects a #PF when L2 |
| * is running). |
| */ |
| static int nested_pf_handled(struct kvm_vcpu *vcpu) |
| { |
| struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
| |
| /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */ |
| if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR))) |
| return 0; |
| |
| nested_vmx_vmexit(vcpu); |
| return 1; |
| } |
| |
| static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
| bool has_error_code, u32 error_code, |
| bool reinject) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| u32 intr_info = nr | INTR_INFO_VALID_MASK; |
| |
| if (nr == PF_VECTOR && is_guest_mode(vcpu) && |
| nested_pf_handled(vcpu)) |
| return; |
| |
| if (has_error_code) { |
| vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
| intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
| } |
| |
| if (vmx->rmode.vm86_active) { |
| int inc_eip = 0; |
| if (kvm_exception_is_soft(nr)) |
| inc_eip = vcpu->arch.event_exit_inst_len; |
| if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) |
| kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
| return; |
| } |
| |
| if (kvm_exception_is_soft(nr)) { |
| vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, |
| vmx->vcpu.arch.event_exit_inst_len); |
| intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
| } else |
| intr_info |= INTR_TYPE_HARD_EXCEPTION; |
| |
| vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); |
| vmx_clear_hlt(vcpu); |
| } |
| |
| static bool vmx_rdtscp_supported(void) |
| { |
| return cpu_has_vmx_rdtscp(); |
| } |
| |
| /* |
| * Swap MSR entry in host/guest MSR entry array. |
| */ |
| static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
| { |
| struct shared_msr_entry tmp; |
| |
| tmp = vmx->guest_msrs[to]; |
| vmx->guest_msrs[to] = vmx->guest_msrs[from]; |
| vmx->guest_msrs[from] = tmp; |
| } |
| |
| /* |
| * Set up the vmcs to automatically save and restore system |
| * msrs. Don't touch the 64-bit msrs if the guest is in legacy |
| * mode, as fiddling with msrs is very expensive. |
| */ |
| static void setup_msrs(struct vcpu_vmx *vmx) |
| { |
| int save_nmsrs, index; |
| unsigned long *msr_bitmap; |
| |
| vmx_load_host_state(vmx); |
| save_nmsrs = 0; |
| #ifdef CONFIG_X86_64 |
| if (is_long_mode(&vmx->vcpu)) { |
| index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
| if (index >= 0) |
| move_msr_up(vmx, index, save_nmsrs++); |
| index = __find_msr_index(vmx, MSR_LSTAR); |
| if (index >= 0) |
| move_msr_up(vmx, index, save_nmsrs++); |
| index = __find_msr_index(vmx, MSR_CSTAR); |
| if (index >= 0) |
| move_msr_up(vmx, index, save_nmsrs++); |
| index = __find_msr_index(vmx, MSR_TSC_AUX); |
| if (index >= 0 && vmx->rdtscp_enabled) |
| move_msr_up(vmx, index, save_nmsrs++); |
| /* |
| * MSR_STAR is only needed on long mode guests, and only |
| * if efer.sce is enabled. |
| */ |
| index = __find_msr_index(vmx, MSR_STAR); |
| if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
| move_msr_up(vmx, index, save_nmsrs++); |
| } |
| #endif |
| index = __find_msr_index(vmx, MSR_EFER); |
| if (index >= 0 && update_transition_efer(vmx, index)) |
| move_msr_up(vmx, index, save_nmsrs++); |
| |
| vmx->save_nmsrs = save_nmsrs; |
| |
| if (cpu_has_vmx_msr_bitmap()) { |
| if (is_long_mode(&vmx->vcpu)) |
| msr_bitmap = vmx_msr_bitmap_longmode; |
| else |
| msr_bitmap = vmx_msr_bitmap_legacy; |
| |
| vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); |
| } |
| } |
| |
| /* |
| * reads and returns guest's timestamp counter "register" |
| * guest_tsc = host_tsc + tsc_offset -- 21.3 |
| */ |
| static u64 guest_read_tsc(void) |
| { |
| u64 host_tsc, tsc_offset; |
| |
| rdtscll(host_tsc); |
| tsc_offset = vmcs_read64(TSC_OFFSET); |
| return host_tsc + tsc_offset; |
| } |
| |
| /* |
| * Like guest_read_tsc, but always returns L1's notion of the timestamp |
| * counter, even if a nested guest (L2) is currently running. |
| */ |
| u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu) |
| { |
| u64 host_tsc, tsc_offset; |
| |
| rdtscll(host_tsc); |
| tsc_offset = is_guest_mode(vcpu) ? |
| to_vmx(vcpu)->nested.vmcs01_tsc_offset : |
| vmcs_read64(TSC_OFFSET); |
| return host_tsc + tsc_offset; |
| } |
| |
| /* |
| * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ |
| * ioctl. In this case the call-back should update internal vmx state to make |
| * the changes effective. |
| */ |
| static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
| { |
| /* Nothing to do here */ |
| } |
| |
| /* |
| * writes 'offset' into guest's timestamp counter offset register |
| */ |
| static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
| { |
| if (is_guest_mode(vcpu)) { |
| /* |
| * We're here if L1 chose not to trap WRMSR to TSC. According |
| * to the spec, this should set L1's TSC; The offset that L1 |
| * set for L2 remains unchanged, and still needs to be added |
| * to the newly set TSC to get L2's TSC. |
| */ |
| struct vmcs12 *vmcs12; |
| to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset; |
| /* recalculate vmcs02.TSC_OFFSET: */ |
| vmcs12 = get_vmcs12(vcpu); |
| vmcs_write64(TSC_OFFSET, offset + |
| (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? |
| vmcs12->tsc_offset : 0)); |
| } else { |
| vmcs_write64(TSC_OFFSET, offset); |
| } |
| } |
| |
| static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
| { |
| u64 offset = vmcs_read64(TSC_OFFSET); |
| vmcs_write64(TSC_OFFSET, offset + adjustment); |
| if (is_guest_mode(vcpu)) { |
| /* Even when running L2, the adjustment needs to apply to L1 */ |
| to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment; |
| } |
| } |
| |
| static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
| { |
| return target_tsc - native_read_tsc(); |
| } |
| |
| static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
| { |
| struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); |
| return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); |
| } |
| |
| /* |
| * nested_vmx_allowed() checks whether a guest should be allowed to use VMX |
| * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for |
| * all guests if the "nested" module option is off, and can also be disabled |
| * for a single guest by disabling its VMX cpuid bit. |
| */ |
| static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) |
| { |
| return nested && guest_cpuid_has_vmx(vcpu); |
| } |
| |
| /* |
| * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be |
| * returned for the various VMX controls MSRs when nested VMX is enabled. |
| * The same values should also be used to verify that vmcs12 control fields are |
| * valid during nested entry from L1 to L2. |
| * Each of these control msrs has a low and high 32-bit half: A low bit is on |
| * if the corresponding bit in the (32-bit) control field *must* be on, and a |
| * bit in the high half is on if the corresponding bit in the control field |
| * may be on. See also vmx_control_verify(). |
| * TODO: allow these variables to be modified (downgraded) by module options |
| * or other means. |
| */ |
| static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high; |
| static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high; |
| static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high; |
| static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high; |
| static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high; |
| static __init void nested_vmx_setup_ctls_msrs(void) |
| { |
| /* |
| * Note that as a general rule, the high half of the MSRs (bits in |
| * the control fields which may be 1) should be initialized by the |
| * intersection of the underlying hardware's MSR (i.e., features which |
| * can be supported) and the list of features we want to expose - |
| * because they are known to be properly supported in our code. |
| * Also, usually, the low half of the MSRs (bits which must be 1) can |
| * be set to 0, meaning that L1 may turn off any of these bits. The |
| * reason is that if one of these bits is necessary, it will appear |
| * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control |
| * fields of vmcs01 and vmcs02, will turn these bits off - and |
| * nested_vmx_exit_handled() will not pass related exits to L1. |
| * These rules have exceptions below. |
| */ |
| |
| /* pin-based controls */ |
| /* |
| * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is |
| * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR. |
| */ |
| nested_vmx_pinbased_ctls_low = 0x16 ; |
| nested_vmx_pinbased_ctls_high = 0x16 | |
| PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | |
| PIN_BASED_VIRTUAL_NMIS; |
| |
| /* exit controls */ |
| nested_vmx_exit_ctls_low = 0; |
| /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */ |
| #ifdef CONFIG_X86_64 |
| nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE; |
| #else |
| nested_vmx_exit_ctls_high = 0; |
| #endif |
| |
| /* entry controls */ |
| rdmsr(MSR_IA32_VMX_ENTRY_CTLS, |
| nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high); |
| nested_vmx_entry_ctls_low = 0; |
| nested_vmx_entry_ctls_high &= |
| VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE; |
| |
| /* cpu-based controls */ |
| rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, |
| nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high); |
| nested_vmx_procbased_ctls_low = 0; |
| nested_vmx_procbased_ctls_high &= |
| CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING | |
| CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
| CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | |
| CPU_BASED_CR3_STORE_EXITING | |
| #ifdef CONFIG_X86_64 |
| CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | |
| #endif |
| CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | |
| CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING | |
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
| /* |
| * We can allow some features even when not supported by the |
| * hardware. For example, L1 can specify an MSR bitmap - and we |
| * can use it to avoid exits to L1 - even when L0 runs L2 |
| * without MSR bitmaps. |
| */ |
| nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS; |
| |
| /* secondary cpu-based controls */ |
| rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
| nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high); |
| nested_vmx_secondary_ctls_low = 0; |
| nested_vmx_secondary_ctls_high &= |
| SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
| } |
| |
| static inline bool vmx_control_verify(u32 control, u32 low, u32 high) |
| { |
| /* |
| * Bits 0 in high must be 0, and bits 1 in low must be 1. |
| */ |
| return ((control & high) | low) == control; |
| } |
| |
| static inline u64 vmx_control_msr(u32 low, u32 high) |
| { |
| return low | ((u64)high << 32); |
| } |
| |
| /* |
| * If we allow our guest to use VMX instructions (i.e., nested VMX), we should |
| * also let it use VMX-specific MSRs. |
| * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a |
| * VMX-specific MSR, or 0 when we haven't (and the caller should handle it |
| * like all other MSRs). |
| */ |
| static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
| { |
| if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC && |
| msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) { |
| /* |
| * According to the spec, processors which do not support VMX |
| * should throw a #GP(0) when VMX capability MSRs are read. |
| */ |
| kvm_queue_exception_e(vcpu, GP_VECTOR, 0); |
| return 1; |
| } |
| |
| switch (msr_index) { |
| case MSR_IA32_FEATURE_CONTROL: |
| *pdata = 0; |
| break; |
| case MSR_IA32_VMX_BASIC: |
| /* |
| * This MSR reports some information about VMX support. We |
| * should return information about the VMX we emulate for the |
| * guest, and the VMCS structure we give it - not about the |
| * VMX support of the underlying hardware. |
| */ |
| *pdata = VMCS12_REVISION | |
| ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | |
| (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); |
| break; |
| case MSR_IA32_VMX_TRUE_PINBASED_CTLS: |
| case MSR_IA32_VMX_PINBASED_CTLS: |
| *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low, |
| nested_vmx_pinbased_ctls_high); |
| break; |
| case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: |
| case MSR_IA32_VMX_PROCBASED_CTLS: |
| *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low, |
| nested_vmx_procbased_ctls_high); |
| break; |
| case MSR_IA32_VMX_TRUE_EXIT_CTLS: |
| case MSR_IA32_VMX_EXIT_CTLS: |
| *pdata = vmx_control_msr(nested_vmx_exit_ctls_low, |
| nested_vmx_exit_ctls_high); |
| break; |
| case MSR_IA32_VMX_TRUE_ENTRY_CTLS: |
| case MSR_IA32_VMX_ENTRY_CTLS: |
| *pdata = vmx_control_msr(nested_vmx_entry_ctls_low, |
| nested_vmx_entry_ctls_high); |
| break; |
| case MSR_IA32_VMX_MISC: |
| *pdata = 0; |
| break; |
| /* |
| * These MSRs specify bits which the guest must keep fixed (on or off) |
| * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
| * We picked the standard core2 setting. |
| */ |
| #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) |
| #define VMXON_CR4_ALWAYSON X86_CR4_VMXE |
| case MSR_IA32_VMX_CR0_FIXED0: |
| *pdata = VMXON_CR0_ALWAYSON; |
| break; |
| case MSR_IA32_VMX_CR0_FIXED1: |
| *pdata = -1ULL; |
| break; |
| case MSR_IA32_VMX_CR4_FIXED0: |
| *pdata = VMXON_CR4_ALWAYSON; |
| break; |
| case MSR_IA32_VMX_CR4_FIXED1: |
| *pdata = -1ULL; |
| break; |
| case MSR_IA32_VMX_VMCS_ENUM: |
| *pdata = 0x1f; |
| break; |
| case MSR_IA32_VMX_PROCBASED_CTLS2: |
| *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low, |
| nested_vmx_secondary_ctls_high); |
| break; |
| case MSR_IA32_VMX_EPT_VPID_CAP: |
| /* Currently, no nested ept or nested vpid */ |
| *pdata = 0; |
| break; |
| default: |
| return 0; |
| } |
| |
| return 1; |
| } |
| |
| static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) |
| { |
| if (!nested_vmx_allowed(vcpu)) |
| return 0; |
| |
| if (msr_index == MSR_IA32_FEATURE_CONTROL) |
| /* TODO: the right thing. */ |
| return 1; |
| /* |
| * No need to treat VMX capability MSRs specially: If we don't handle |
| * them, handle_wrmsr will #GP(0), which is correct (they are readonly) |
| */ |
| return 0; |
| } |
| |
| /* |
| * Reads an msr value (of 'msr_index') into 'pdata'. |
| * Returns 0 on success, non-0 otherwise. |
| * Assumes vcpu_load() was already called. |
| */ |
| static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
| { |
| u64 data; |
| struct shared_msr_entry *msr; |
| |
| if (!pdata) { |
| printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); |
| return -EINVAL; |
| } |
| |
| switch (msr_index) { |
| #ifdef CONFIG_X86_64 |
| case MSR_FS_BASE: |
| data = vmcs_readl(GUEST_FS_BASE); |
| break; |
| case MSR_GS_BASE: |
| data = vmcs_readl(GUEST_GS_BASE); |
| break; |
| case MSR_KERNEL_GS_BASE: |
| vmx_load_host_state(to_vmx(vcpu)); |
| data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
| break; |
| #endif |
| case MSR_EFER: |
| return kvm_get_msr_common(vcpu, msr_index, pdata); |
| case MSR_IA32_TSC: |
| data = guest_read_tsc(); |
| break; |
| case MSR_IA32_SYSENTER_CS: |
| data = vmcs_read32(GUEST_SYSENTER_CS); |
| break; |
| case MSR_IA32_SYSENTER_EIP: |
| data = vmcs_readl(GUEST_SYSENTER_EIP); |
| break; |
| case MSR_IA32_SYSENTER_ESP: |
| data = vmcs_readl(GUEST_SYSENTER_ESP); |
| break; |
| case MSR_TSC_AUX: |
| if (!to_vmx(vcpu)->rdtscp_enabled) |
| return 1; |
| /* Otherwise falls through */ |
| default: |
| vmx_load_host_state(to_vmx(vcpu)); |
| if (vmx_get_vmx_msr(vcpu, msr_index, pdata)) |
| return 0; |
| msr = find_msr_entry(to_vmx(vcpu), msr_index); |
| if (msr) { |
| vmx_load_host_state(to_vmx(vcpu)); |
| data = msr->data; |
| break; |
| } |
| return kvm_get_msr_common(vcpu, msr_index, pdata); |
| } |
| |
| *pdata = data; |
| return 0; |
| } |
| |
| /* |
| * Writes msr value into into the appropriate "register". |
| * Returns 0 on success, non-0 otherwise. |
| * Assumes vcpu_load() was already called. |
| */ |
| static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| struct shared_msr_entry *msr; |
| int ret = 0; |
| |
| switch (msr_index) { |
| case MSR_EFER: |
| vmx_load_host_state(vmx); |
| ret = kvm_set_msr_common(vcpu, msr_index, data); |
| break; |
| #ifdef CONFIG_X86_64 |
| case MSR_FS_BASE: |
| vmx_segment_cache_clear(vmx); |
| vmcs_writel(GUEST_FS_BASE, data); |
| break; |
| case MSR_GS_BASE: |
| vmx_segment_cache_clear(vmx); |
| vmcs_writel(GUEST_GS_BASE, data); |
| break; |
| case MSR_KERNEL_GS_BASE: |
| vmx_load_host_state(vmx); |
| vmx->msr_guest_kernel_gs_base = data; |
| break; |
| #endif |
| case MSR_IA32_SYSENTER_CS: |
| vmcs_write32(GUEST_SYSENTER_CS, data); |
| break; |
| case MSR_IA32_SYSENTER_EIP: |
| vmcs_writel(GUEST_SYSENTER_EIP, data); |
| break; |
| case MSR_IA32_SYSENTER_ESP: |
| vmcs_writel(GUEST_SYSENTER_ESP, data); |
| break; |
| case MSR_IA32_TSC: |
| kvm_write_tsc(vcpu, data); |
| break; |
| case MSR_IA32_CR_PAT: |
| if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
| vmcs_write64(GUEST_IA32_PAT, data); |
| vcpu->arch.pat = data; |
| break; |
| } |
| ret = kvm_set_msr_common(vcpu, msr_index, data); |
| break; |
| case MSR_TSC_AUX: |
| if (!vmx->rdtscp_enabled) |
| return 1; |
| /* Check reserved bit, higher 32 bits should be zero */ |
| if ((data >> 32) != 0) |
| return 1; |
| /* Otherwise falls through */ |
| default: |
| if (vmx_set_vmx_msr(vcpu, msr_index, data)) |
| break; |
| msr = find_msr_entry(vmx, msr_index); |
| if (msr) { |
| vmx_load_host_state(vmx); |
| msr->data = data; |
| break; |
| } |
| ret = kvm_set_msr_common(vcpu, msr_index, data); |
| } |
| |
| return ret; |
| } |
| |
| static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
| { |
| __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
| switch (reg) { |
| case VCPU_REGS_RSP: |
| vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); |
| break; |
| case VCPU_REGS_RIP: |
| vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); |
| break; |
| case VCPU_EXREG_PDPTR: |
| if (enable_ept) |
| ept_save_pdptrs(vcpu); |
| break; |
| default: |
| break; |
| } |
| } |
| |
| static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
| { |
| if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
| vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); |
| else |
| vmcs_writel(GUEST_DR7, vcpu->arch.dr7); |
| |
| update_exception_bitmap(vcpu); |
| } |
| |
| static __init int cpu_has_kvm_support(void) |
| { |
| return cpu_has_vmx(); |
| } |
| |
| static __init int vmx_disabled_by_bios(void) |
| { |
| u64 msr; |
| |
| rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); |
| if (msr & FEATURE_CONTROL_LOCKED) { |
| /* launched w/ TXT and VMX disabled */ |
| if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
| && tboot_enabled()) |
| return 1; |
| /* launched w/o TXT and VMX only enabled w/ TXT */ |
| if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
| && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
| && !tboot_enabled()) { |
| printk(KERN_WARNING "kvm: disable TXT in the BIOS or " |
| "activate TXT before enabling KVM\n"); |
| return 1; |
| } |
| /* launched w/o TXT and VMX disabled */ |
| if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
| && !tboot_enabled()) |
| return 1; |
| } |
| |
| return 0; |
| } |
| |
| static void kvm_cpu_vmxon(u64 addr) |
| { |
| asm volatile (ASM_VMX_VMXON_RAX |
| : : "a"(&addr), "m"(addr) |
| : "memory", "cc"); |
| } |
| |
| static int hardware_enable(void *garbage) |
| { |
| int cpu = raw_smp_processor_id(); |
| u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
| u64 old, test_bits; |
| |
| if (read_cr4() & X86_CR4_VMXE) |
| return -EBUSY; |
| |
| INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
| rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
| |
| test_bits = FEATURE_CONTROL_LOCKED; |
| test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; |
| if (tboot_enabled()) |
| test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; |
| |
| if ((old & test_bits) != test_bits) { |
| /* enable and lock */ |
| wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
| } |
| write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
| |
| if (vmm_exclusive) { |
| kvm_cpu_vmxon(phys_addr); |
| ept_sync_global(); |
| } |
| |
| store_gdt(&__get_cpu_var(host_gdt)); |
| |
| return 0; |
| } |
| |
| static void vmclear_local_loaded_vmcss(void) |
| { |
| int cpu = raw_smp_processor_id(); |
| struct loaded_vmcs *v, *n; |
| |
| list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
| loaded_vmcss_on_cpu_link) |
| __loaded_vmcs_clear(v); |
| } |
| |
| |
| /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() |
| * tricks. |
| */ |
| static void kvm_cpu_vmxoff(void) |
| { |
| asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
| } |
| |
| static void hardware_disable(void *garbage) |
| { |
| if (vmm_exclusive) { |
| vmclear_local_loaded_vmcss(); |
| kvm_cpu_vmxoff(); |
| } |
| write_cr4(read_cr4() & ~X86_CR4_VMXE); |
| } |
| |
| static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
| u32 msr, u32 *result) |
| { |
| u32 vmx_msr_low, vmx_msr_high; |
| u32 ctl = ctl_min | ctl_opt; |
| |
| rdmsr(msr, vmx_msr_low, vmx_msr_high); |
| |
| ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ |
| ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ |
| |
| /* Ensure minimum (required) set of control bits are supported. */ |
| if (ctl_min & ~ctl) |
| return -EIO; |
| |
| *result = ctl; |
| return 0; |
| } |
| |
| static __init bool allow_1_setting(u32 msr, u32 ctl) |
| { |
| u32 vmx_msr_low, vmx_msr_high; |
| |
| rdmsr(msr, vmx_msr_low, vmx_msr_high); |
| return vmx_msr_high & ctl; |
| } |
| |
| static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
| { |
| u32 vmx_msr_low, vmx_msr_high; |
| u32 min, opt, min2, opt2; |
| u32 _pin_based_exec_control = 0; |
| u32 _cpu_based_exec_control = 0; |
| u32 _cpu_based_2nd_exec_control = 0; |
| u32 _vmexit_control = 0; |
| u32 _vmentry_control = 0; |
| |
| min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
| opt = PIN_BASED_VIRTUAL_NMIS; |
| if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
| &_pin_based_exec_control) < 0) |
| return -EIO; |
| |
| min = |
| #ifdef CONFIG_X86_64 |
| CPU_BASED_CR8_LOAD_EXITING | |
| CPU_BASED_CR8_STORE_EXITING | |
| #endif |
| CPU_BASED_CR3_LOAD_EXITING | |
| CPU_BASED_CR3_STORE_EXITING | |
| CPU_BASED_USE_IO_BITMAPS | |
| CPU_BASED_MOV_DR_EXITING | |
| CPU_BASED_USE_TSC_OFFSETING | |
| CPU_BASED_MWAIT_EXITING | |
| CPU_BASED_MONITOR_EXITING | |
| CPU_BASED_INVLPG_EXITING; |
| |
| if (yield_on_hlt) |
| min |= CPU_BASED_HLT_EXITING; |
| |
| opt = CPU_BASED_TPR_SHADOW | |
| CPU_BASED_USE_MSR_BITMAPS | |
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
| if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
| &_cpu_based_exec_control) < 0) |
| return -EIO; |
| #ifdef CONFIG_X86_64 |
| if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) |
| _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & |
| ~CPU_BASED_CR8_STORE_EXITING; |
| #endif |
| if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
| min2 = 0; |
| opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
| SECONDARY_EXEC_WBINVD_EXITING | |
| SECONDARY_EXEC_ENABLE_VPID | |
| SECONDARY_EXEC_ENABLE_EPT | |
| SECONDARY_EXEC_UNRESTRICTED_GUEST | |
| SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
| SECONDARY_EXEC_RDTSCP; |
| if (adjust_vmx_controls(min2, opt2, |
| MSR_IA32_VMX_PROCBASED_CTLS2, |
| &_cpu_based_2nd_exec_control) < 0) |
| return -EIO; |
| } |
| #ifndef CONFIG_X86_64 |
| if (!(_cpu_based_2nd_exec_control & |
| SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) |
| _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; |
| #endif |
| if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
| /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
| enabled */ |
| _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
| CPU_BASED_CR3_STORE_EXITING | |
| CPU_BASED_INVLPG_EXITING); |
| rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
| vmx_capability.ept, vmx_capability.vpid); |
| } |
| |
| min = 0; |
| #ifdef CONFIG_X86_64 |
| min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; |
| #endif |
| opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
| if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
| &_vmexit_control) < 0) |
| return -EIO; |
| |
| min = 0; |
| opt = VM_ENTRY_LOAD_IA32_PAT; |
| if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
| &_vmentry_control) < 0) |
| return -EIO; |
| |
| rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
| |
| /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ |
| if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) |
| return -EIO; |
| |
| #ifdef CONFIG_X86_64 |
| /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ |
| if (vmx_msr_high & (1u<<16)) |
| return -EIO; |
| #endif |
| |
| /* Require Write-Back (WB) memory type for VMCS accesses. */ |
| if (((vmx_msr_high >> 18) & 15) != 6) |
| return -EIO; |
| |
| vmcs_conf->size = vmx_msr_high & 0x1fff; |
| vmcs_conf->order = get_order(vmcs_config.size); |
| vmcs_conf->revision_id = vmx_msr_low; |
| |
| vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
| vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; |
| vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
| vmcs_conf->vmexit_ctrl = _vmexit_control; |
| vmcs_conf->vmentry_ctrl = _vmentry_control; |
| |
| cpu_has_load_ia32_efer = |
| allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, |
| VM_ENTRY_LOAD_IA32_EFER) |
| && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, |
| VM_EXIT_LOAD_IA32_EFER); |
| |
| cpu_has_load_perf_global_ctrl = |
| allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, |
| VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) |
| && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, |
| VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); |
| |
| /* |
| * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL |
| * but due to arrata below it can't be used. Workaround is to use |
| * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
| * |
| * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] |
| * |
| * AAK155 (model 26) |
| * AAP115 (model 30) |
| * AAT100 (model 37) |
| * BC86,AAY89,BD102 (model 44) |
| * BA97 (model 46) |
| * |
| */ |
| if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { |
| switch (boot_cpu_data.x86_model) { |
| case 26: |
| case 30: |
| case 37: |
| case 44: |
| case 46: |
| cpu_has_load_perf_global_ctrl = false; |
| printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " |
| "does not work properly. Using workaround\n"); |
| break; |
| default: |
| break; |
| } |
| } |
| |
| return 0; |
| } |
| |
| static struct vmcs *alloc_vmcs_cpu(int cpu) |
| { |
| int node = cpu_to_node(cpu); |
| struct page *pages; |
| struct vmcs *vmcs; |
| |
| pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
| if (!pages) |
| return NULL; |
| vmcs = page_address(pages); |
| memset(vmcs, 0, vmcs_config.size); |
| vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ |
| return vmcs; |
| } |
| |
| static struct vmcs *alloc_vmcs(void) |
| { |
| return alloc_vmcs_cpu(raw_smp_processor_id()); |
| } |
| |
| static void free_vmcs(struct vmcs *vmcs) |
| { |
| free_pages((unsigned long)vmcs, vmcs_config.order); |
| } |
| |
| /* |
| * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded |
| */ |
| static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) |
| { |
| if (!loaded_vmcs->vmcs) |
| return; |
| loaded_vmcs_clear(loaded_vmcs); |
| free_vmcs(loaded_vmcs->vmcs); |
| loaded_vmcs->vmcs = NULL; |
| } |
| |
| static void free_kvm_area(void) |
| { |
| int cpu; |
| |
| for_each_possible_cpu(cpu) { |
| free_vmcs(per_cpu(vmxarea, cpu)); |
| per_cpu(vmxarea, cpu) = NULL; |
| } |
| } |
| |
| static __init int alloc_kvm_area(void) |
| { |
| int cpu; |
| |
| for_each_possible_cpu(cpu) { |
| struct vmcs *vmcs; |
| |
| vmcs = alloc_vmcs_cpu(cpu); |
| if (!vmcs) { |
| free_kvm_area(); |
| return -ENOMEM; |
| } |
| |
| per_cpu(vmxarea, cpu) = vmcs; |
| } |
| return 0; |
| } |
| |
| static __init int hardware_setup(void) |
| { |
| if (setup_vmcs_config(&vmcs_config) < 0) |
| return -EIO; |
| |
| if (boot_cpu_has(X86_FEATURE_NX)) |
| kvm_enable_efer_bits(EFER_NX); |
| |
| if (!cpu_has_vmx_vpid()) |
| enable_vpid = 0; |
| |
| if (!cpu_has_vmx_ept() || |
| !cpu_has_vmx_ept_4levels()) { |
| enable_ept = 0; |
| enable_unrestricted_guest = 0; |
| } |
| |
| if (!cpu_has_vmx_unrestricted_guest()) |
| enable_unrestricted_guest = 0; |
| |
| if (!cpu_has_vmx_flexpriority()) |
| flexpriority_enabled = 0; |
| |
| if (!cpu_has_vmx_tpr_shadow()) |
| kvm_x86_ops->update_cr8_intercept = NULL; |
| |
| if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
| kvm_disable_largepages(); |
| |
| if (!cpu_has_vmx_ple()) |
| ple_gap = 0; |
| |
| if (nested) |
| nested_vmx_setup_ctls_msrs(); |
| |
| return alloc_kvm_area(); |
| } |
| |
| static __exit void hardware_unsetup(void) |
| { |
| free_kvm_area(); |
| } |
| |
| static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
| { |
| struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
| |
| if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
| vmcs_write16(sf->selector, save->selector); |
| vmcs_writel(sf->base, save->base); |
| vmcs_write32(sf->limit, save->limit); |
| vmcs_write32(sf->ar_bytes, save->ar); |
| } else { |
| u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) |
| << AR_DPL_SHIFT; |
| vmcs_write32(sf->ar_bytes, 0x93 | dpl); |
| } |
| } |
| |
| static void enter_pmode(struct kvm_vcpu *vcpu) |
| { |
| unsigned long flags; |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| |
| vmx->emulation_required = 1; |
| vmx->rmode.vm86_active = 0; |
| |
| vmx_segment_cache_clear(vmx); |
| |
| vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector); |
| vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
| vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); |
| vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); |
| |
| flags = vmcs_readl(GUEST_RFLAGS); |
| flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
| flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; |
| vmcs_writel(GUEST_RFLAGS, flags); |
| |
| vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
| (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); |
| |
| update_exception_bitmap(vcpu); |
| |
| if (emulate_invalid_guest_state) |
| return; |
| |
| fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
| fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); |
| fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); |
| fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); |
| |
| vmx_segment_cache_clear(vmx); |
| |
| vmcs_write16(GUEST_SS_SELECTOR, 0); |
| vmcs_write32(GUEST_SS_AR_BYTES, 0x93); |
| |
| vmcs_write16(GUEST_CS_SELECTOR, |
| vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); |
| vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); |
| } |
| |
| static gva_t rmode_tss_base(struct kvm *kvm) |
| { |
| if (!kvm->arch.tss_addr) { |
| struct kvm_memslots *slots; |
| gfn_t base_gfn; |
| |
| slots = kvm_memslots(kvm); |
| base_gfn = slots->memslots[0].base_gfn + |
| kvm->memslots->memslots[0].npages - 3; |
| return base_gfn << PAGE_SHIFT; |
| } |
| return kvm->arch.tss_addr; |
| } |
| |
| static void fix_rmode_seg(int seg, struct kvm_save_segment *save) |
| { |
| struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
| |
| save->selector = vmcs_read16(sf->selector); |
| save->base = vmcs_readl(sf->base); |
| save->limit = vmcs_read32(sf->limit); |
| save->ar = vmcs_read32(sf->ar_bytes); |
| vmcs_write16(sf->selector, save->base >> 4); |
| vmcs_write32(sf->base, save->base & 0xffff0); |
| vmcs_write32(sf->limit, 0xffff); |
| vmcs_write32(sf->ar_bytes, 0xf3); |
| if (save->base & 0xf) |
| printk_once(KERN_WARNING "kvm: segment base is not paragraph" |
| " aligned when entering protected mode (seg=%d)", |
| seg); |
| } |
| |
| static void enter_rmode(struct kvm_vcpu *vcpu) |
| { |
| unsigned long flags; |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| |
| if (enable_unrestricted_guest) |
| return; |
| |
| vmx->emulation_required = 1; |
| vmx->rmode.vm86_active = 1; |
| |
| /* |
| * Very old userspace does not call KVM_SET_TSS_ADDR before entering |
| * vcpu. Call it here with phys address pointing 16M below 4G. |
| */ |
| if (!vcpu->kvm->arch.tss_addr) { |
| printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
| "called before entering vcpu\n"); |
| srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
| vmx_set_tss_addr(vcpu->kvm, 0xfeffd000); |
| vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
| } |
| |
| vmx_segment_cache_clear(vmx); |
| |
| vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR); |
| vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
| vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
| |
| vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
| vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
| |
| vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
| vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
| |
| flags = vmcs_readl(GUEST_RFLAGS); |
| vmx->rmode.save_rflags = flags; |
| |
| flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
| |
| vmcs_writel(GUEST_RFLAGS, flags); |
| vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
| update_exception_bitmap(vcpu); |
| |
| if (emulate_invalid_guest_state) |
| goto continue_rmode; |
| |
| vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
| vmcs_write32(GUEST_SS_LIMIT, 0xffff); |
| vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); |
| |
| vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); |
| vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
| if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
| vmcs_writel(GUEST_CS_BASE, 0xf0000); |
| vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
| |
| fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
| fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); |
| fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); |
| fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); |
| |
| continue_rmode: |
| kvm_mmu_reset_context(vcpu); |
| } |
| |
| static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
| |
| if (!msr) |
| return; |
| |
| /* |
| * Force kernel_gs_base reloading before EFER changes, as control |
| * of this msr depends on is_long_mode(). |
| */ |
| vmx_load_host_state(to_vmx(vcpu)); |
| vcpu->arch.efer = efer; |
| if (efer & EFER_LMA) { |
| vmcs_write32(VM_ENTRY_CONTROLS, |
| vmcs_read32(VM_ENTRY_CONTROLS) | |
| VM_ENTRY_IA32E_MODE); |
| msr->data = efer; |
| } else { |
| vmcs_write32(VM_ENTRY_CONTROLS, |
| vmcs_read32(VM_ENTRY_CONTROLS) & |
| ~VM_ENTRY_IA32E_MODE); |
| |
| msr->data = efer & ~EFER_LME; |
| } |
| setup_msrs(vmx); |
| } |
| |
| #ifdef CONFIG_X86_64 |
| |
| static void enter_lmode(struct kvm_vcpu *vcpu) |
| { |
| u32 guest_tr_ar; |
| |
| vmx_segment_cache_clear(to_vmx(vcpu)); |
| |
| guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
| if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { |
| pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
| __func__); |
| vmcs_write32(GUEST_TR_AR_BYTES, |
| (guest_tr_ar & ~AR_TYPE_MASK) |
| | AR_TYPE_BUSY_64_TSS); |
| } |
| vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
| } |
| |
| static void exit_lmode(struct kvm_vcpu *vcpu) |
| { |
| vmcs_write32(VM_ENTRY_CONTROLS, |
| vmcs_read32(VM_ENTRY_CONTROLS) |
| & ~VM_ENTRY_IA32E_MODE); |
| vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
| } |
| |
| #endif |
| |
| static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
| { |
| vpid_sync_context(to_vmx(vcpu)); |
| if (enable_ept) { |
| if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
| return; |
| ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
| } |
| } |
| |
| static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
| { |
| ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; |
| |
| vcpu->arch.cr0 &= ~cr0_guest_owned_bits; |
| vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; |
| } |
| |
| static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
| { |
| if (enable_ept && is_paging(vcpu)) |
| vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
| __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
| } |
| |
| static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
| { |
| ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
| |
| vcpu->arch.cr4 &= ~cr4_guest_owned_bits; |
| vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; |
| } |
| |
| static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
| { |
| if (!test_bit(VCPU_EXREG_PDPTR, |
| (unsigned long *)&vcpu->arch.regs_dirty)) |
| return; |
| |
| if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
| vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]); |
| vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]); |
| vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]); |
| vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]); |
| } |
| } |
| |
| static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
| { |
| if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
| vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
| vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); |
| vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); |
| vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); |
| } |
| |
| __set_bit(VCPU_EXREG_PDPTR, |
| (unsigned long *)&vcpu->arch.regs_avail); |
| __set_bit(VCPU_EXREG_PDPTR, |
| (unsigned long *)&vcpu->arch.regs_dirty); |
| } |
| |
| static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
| |
| static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, |
| unsigned long cr0, |
| struct kvm_vcpu *vcpu) |
| { |
| if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
| vmx_decache_cr3(vcpu); |
| if (!(cr0 & X86_CR0_PG)) { |
| /* From paging/starting to nonpaging */ |
| vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, |
| vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
| (CPU_BASED_CR3_LOAD_EXITING | |
| CPU_BASED_CR3_STORE_EXITING)); |
| vcpu->arch.cr0 = cr0; |
| vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
| } else if (!is_paging(vcpu)) { |
| /* From nonpaging to paging */ |
| vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, |
| vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
| ~(CPU_BASED_CR3_LOAD_EXITING | |
| CPU_BASED_CR3_STORE_EXITING)); |
| vcpu->arch.cr0 = cr0; |
| vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
| } |
| |
| if (!(cr0 & X86_CR0_WP)) |
| *hw_cr0 &= ~X86_CR0_WP; |
| } |
| |
| static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| unsigned long hw_cr0; |
| |
| if (enable_unrestricted_guest) |
| hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) |
| | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
| else |
| hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; |
| |
| if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
| enter_pmode(vcpu); |
| |
| if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
| enter_rmode(vcpu); |
| |
| #ifdef CONFIG_X86_64 |
| if (vcpu->arch.efer & EFER_LME) { |
| if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
| enter_lmode(vcpu); |
| if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
| exit_lmode(vcpu); |
| } |
| #endif |
| |
| if (enable_ept) |
| ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
| |
| if (!vcpu->fpu_active) |
| hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
| |
| vmcs_writel(CR0_READ_SHADOW, cr0); |
| vmcs_writel(GUEST_CR0, hw_cr0); |
| vcpu->arch.cr0 = cr0; |
| __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
| } |
| |
| static u64 construct_eptp(unsigned long root_hpa) |
| { |
| u64 eptp; |
| |
| /* TODO write the value reading from MSR */ |
| eptp = VMX_EPT_DEFAULT_MT | |
| VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; |
| eptp |= (root_hpa & PAGE_MASK); |
| |
| return eptp; |
| } |
| |
| static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
| { |
| unsigned long guest_cr3; |
| u64 eptp; |
| |
| guest_cr3 = cr3; |
| if (enable_ept) { |
| eptp = construct_eptp(cr3); |
| vmcs_write64(EPT_POINTER, eptp); |
| guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) : |
| vcpu->kvm->arch.ept_identity_map_addr; |
| ept_load_pdptrs(vcpu); |
| } |
| |
| vmx_flush_tlb(vcpu); |
| vmcs_writel(GUEST_CR3, guest_cr3); |
| } |
| |
| static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
| { |
| unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
| KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
| |
| if (cr4 & X86_CR4_VMXE) { |
| /* |
| * To use VMXON (and later other VMX instructions), a guest |
| * must first be able to turn on cr4.VMXE (see handle_vmon()). |
| * So basically the check on whether to allow nested VMX |
| * is here. |
| */ |
| if (!nested_vmx_allowed(vcpu)) |
| return 1; |
| } else if (to_vmx(vcpu)->nested.vmxon) |
| return 1; |
| |
| vcpu->arch.cr4 = cr4; |
| if (enable_ept) { |
| if (!is_paging(vcpu)) { |
| hw_cr4 &= ~X86_CR4_PAE; |
| hw_cr4 |= X86_CR4_PSE; |
| } else if (!(cr4 & X86_CR4_PAE)) { |
| hw_cr4 &= ~X86_CR4_PAE; |
| } |
| } |
| |
| vmcs_writel(CR4_READ_SHADOW, cr4); |
| vmcs_writel(GUEST_CR4, hw_cr4); |
| return 0; |
| } |
| |
| static void vmx_get_segment(struct kvm_vcpu *vcpu, |
| struct kvm_segment *var, int seg) |
| { |
| struct vcpu_vmx *vmx = to_vmx(vcpu); |
| struct kvm_save_segment *save; |
| u32 ar; |
| |
| if (vmx->rmode.vm86_active |
| && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES |
| || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS |
| || seg == VCPU_SREG_GS) |
| && !emulate_invalid_guest_state) { |
| switch (seg) { |
| case VCPU_SREG_TR: save = &vmx->rmode.tr; break; |
| case VCPU_SREG_ES: save = &vmx->rmode.es; break; |
| case VCPU_SREG_DS: save = &vmx->rmode.ds; break; |
| case VCPU_SREG_FS: save = &vmx->rmode.fs; break; |
| case VCPU_SREG_GS: save = &vmx->rmode.gs; break; |
| default: BUG(); |
| } |
| var->selector = save->selector; |
| var->base = save->base; |
| var->limit = save->limit; |
| ar = save->ar; |
| if (seg == VCPU_SREG_TR |
| || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
| goto use_saved_rmode_seg; |
| } |
| var->base = vmx_read_guest_seg_base(vmx, seg); |
| var->limit = vmx_read_guest_seg_limit(vmx, seg); |
| var->selector = vmx_read_guest_seg_selector(vmx, seg); |
| ar = vmx_read_guest_seg_ar(vmx, seg); |
| use_saved_rmode_seg: |
| if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
| ar = 0; |
| var->type = ar & 15; |
| var->s = (ar >> 4) & 1; |
| var->dpl = (ar >> 5) & 3; |
| var->present = (ar >> 7) & 1; |
| var->avl = (ar >> 12) & 1; |
| var->l = (ar >> 13) & 1; |
| var->db = (ar >> 14) & 1; |
| var->g = (ar >> 15) & 1; |
| var->unusable = (ar >> 16) & 1; |
| } |
| |
| static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
| { |
| struct kvm_segment s; |
| |
| if (to_vmx(vcpu)->rmode.vm86_active) { |
| vmx_get_segment(vcpu, &s, seg); |
| return s.base; |
| } |
| return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
| } |
| |
| static int __vmx_get_cpl(struct kvm_vcpu *vcpu) |
| { |
| if (!is_protmode(vcpu)) |
| return 0; |
| |
| if (!is_long_mode(vcpu) |
| && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */ |
| return 3; |
| |
| return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3; |
| } |
| |
| static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
| { |
| if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) { |
| __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
| to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu); |
| } |
| return to_vmx(vcpu)->cpl; |
| } |
| |
| |
| static u32 vmx_segment_access_rights(struct kvm_segment *var) |
| { |
| u32 ar; |
| |
| if (var->unusable) |
| ar = 1 << 16; |
| else { |
| ar = var->type & 15; |
| ar |= (var->s & 1) << 4; |
| ar |= (var->dpl & 3) << 5; |
| ar |= (var->present & 1) << 7; |
| |