NAND ECC: Fix NAND controller timeouts
Return -EIO in case of a timeout while waiting for the NAND controller
to become ready. Previously, the code would just keep on going which
might result in hard to debug issues further down the road.
Change-Id: Idcfa6de70881191e8a756c4e628dd8c0e05c9370
diff --git a/drivers/mtd/nand/comcerto_nand.c b/drivers/mtd/nand/comcerto_nand.c
index d5ca078..8b23488 100644
--- a/drivers/mtd/nand/comcerto_nand.c
+++ b/drivers/mtd/nand/comcerto_nand.c
@@ -274,11 +274,13 @@
unsigned long timeo = jiffies + 2;
/* Wait for syndrome calculation to complete */
- do {
- if ((readl_relaxed(ecc_base_addr + ECC_IDLE_STAT)) & ECC_IDLE)
- break;
+ while (!(readl_relaxed(ecc_base_addr + ECC_IDLE_STAT) & ECC_IDLE)) {
touch_softlockup_watchdog();
- } while (time_before(jiffies, timeo));
+ if (time_after_eq(jiffies, timeo)) {
+ pr_warn_ratelimited("Timeout waiting for parity module to become idle");
+ return -EIO;
+ }
+ }
/* If no correction is required */
if (likely(!((readl_relaxed(ecc_base_addr + ECC_POLY_STAT)) & ECC_CORR_REQ))) {
@@ -292,15 +294,20 @@
udelay(25);
+ timeo = jiffies + 2;
err_corr_data_prev = 0;
/* Read Correction data status register till header is 0x7FD */
- do {
+ while(1) {
err_corr_data_prev = readl_relaxed(ecc_base_addr + ECC_CORR_DATA_STAT);
if ((err_corr_data_prev >> ECC_BCH_INDEX_SHIFT) == 0x87FD)
break;
touch_softlockup_watchdog();
- } while (time_before(jiffies, timeo));
+ if (time_after_eq(jiffies, timeo)) {
+ pr_warn_ratelimited("Timeout waiting for ECC correction data");
+ return -EIO;
+ }
+ }
udelay(25);
err_corr_data = 0x0;
