| /* |
| * Copyright (c) 2013 MundoReader S.L. |
| * Author: Heiko Stuebner <heiko@sntech.de> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include "skeleton.dtsi" |
| |
| / { |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| mshc0 = &emmc; |
| mshc1 = &mmc0; |
| mshc2 = &mmc1; |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &uart2; |
| serial3 = &uart3; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| }; |
| |
| amba { |
| compatible = "arm,amba-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| dmac1_s: dma-controller@20018000 { |
| compatible = "arm,pl330", "arm,primecell"; |
| reg = <0x20018000 0x4000>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| clocks = <&cru ACLK_DMA1>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| dmac1_ns: dma-controller@2001c000 { |
| compatible = "arm,pl330", "arm,primecell"; |
| reg = <0x2001c000 0x4000>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| clocks = <&cru ACLK_DMA1>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| dmac2: dma-controller@20078000 { |
| compatible = "arm,pl330", "arm,primecell"; |
| reg = <0x20078000 0x4000>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| clocks = <&cru ACLK_DMA2>; |
| clock-names = "apb_pclk"; |
| }; |
| }; |
| |
| xin24m: oscillator { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| #clock-cells = <0>; |
| clock-output-names = "xin24m"; |
| }; |
| |
| L2: l2-cache-controller@10138000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x10138000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| scu@1013c000 { |
| compatible = "arm,cortex-a9-scu"; |
| reg = <0x1013c000 0x100>; |
| }; |
| |
| global_timer: global-timer@1013c200 { |
| compatible = "arm,cortex-a9-global-timer"; |
| reg = <0x1013c200 0x20>; |
| interrupts = <GIC_PPI 11 0x304>; |
| clocks = <&cru CORE_PERI>; |
| }; |
| |
| local_timer: local-timer@1013c600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x1013c600 0x20>; |
| interrupts = <GIC_PPI 13 0x304>; |
| clocks = <&cru CORE_PERI>; |
| }; |
| |
| gic: interrupt-controller@1013d000 { |
| compatible = "arm,cortex-a9-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x1013d000 0x1000>, |
| <0x1013c100 0x0100>; |
| }; |
| |
| uart0: serial@10124000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x10124000 0x400>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <1>; |
| clock-names = "baudclk", "apb_pclk"; |
| clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@10126000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x10126000 0x400>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <1>; |
| clock-names = "baudclk", "apb_pclk"; |
| clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
| status = "disabled"; |
| }; |
| |
| usb_otg: usb@10180000 { |
| compatible = "rockchip,rk3066-usb", "snps,dwc2"; |
| reg = <0x10180000 0x40000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_OTG0>; |
| clock-names = "otg"; |
| status = "disabled"; |
| }; |
| |
| usb_host: usb@101c0000 { |
| compatible = "snps,dwc2"; |
| reg = <0x101c0000 0x40000>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_OTG1>; |
| clock-names = "otg"; |
| status = "disabled"; |
| }; |
| |
| emac: ethernet@10204000 { |
| compatible = "snps,arc-emac"; |
| reg = <0x10204000 0x3c>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; |
| clock-names = "hclk", "macref"; |
| max-speed = <100>; |
| phy-mode = "rmii"; |
| |
| status = "disabled"; |
| }; |
| |
| mmc0: dwmmc@10214000 { |
| compatible = "rockchip,rk2928-dw-mshc"; |
| reg = <0x10214000 0x1000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
| clock-names = "biu", "ciu"; |
| fifo-depth = <256>; |
| status = "disabled"; |
| }; |
| |
| mmc1: dwmmc@10218000 { |
| compatible = "rockchip,rk2928-dw-mshc"; |
| reg = <0x10218000 0x1000>; |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; |
| clock-names = "biu", "ciu"; |
| fifo-depth = <256>; |
| status = "disabled"; |
| }; |
| |
| emmc: dwmmc@1021c000 { |
| compatible = "rockchip,rk2928-dw-mshc"; |
| reg = <0x1021c000 0x1000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; |
| clock-names = "biu", "ciu"; |
| fifo-depth = <256>; |
| status = "disabled"; |
| }; |
| |
| pmu: pmu@20004000 { |
| compatible = "rockchip,rk3066-pmu", "syscon"; |
| reg = <0x20004000 0x100>; |
| }; |
| |
| grf: grf@20008000 { |
| compatible = "syscon"; |
| reg = <0x20008000 0x200>; |
| }; |
| |
| i2c0: i2c@2002d000 { |
| compatible = "rockchip,rk3066-i2c"; |
| reg = <0x2002d000 0x1000>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clock-names = "i2c"; |
| clocks = <&cru PCLK_I2C0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2002f000 { |
| compatible = "rockchip,rk3066-i2c"; |
| reg = <0x2002f000 0x1000>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clocks = <&cru PCLK_I2C1>; |
| clock-names = "i2c"; |
| |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@20030000 { |
| compatible = "rockchip,rk2928-pwm"; |
| reg = <0x20030000 0x10>; |
| #pwm-cells = <2>; |
| clocks = <&cru PCLK_PWM01>; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@20030010 { |
| compatible = "rockchip,rk2928-pwm"; |
| reg = <0x20030010 0x10>; |
| #pwm-cells = <2>; |
| clocks = <&cru PCLK_PWM01>; |
| status = "disabled"; |
| }; |
| |
| wdt: watchdog@2004c000 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x2004c000 0x100>; |
| clocks = <&cru PCLK_WDT>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@20050020 { |
| compatible = "rockchip,rk2928-pwm"; |
| reg = <0x20050020 0x10>; |
| #pwm-cells = <2>; |
| clocks = <&cru PCLK_PWM23>; |
| status = "disabled"; |
| }; |
| |
| pwm3: pwm@20050030 { |
| compatible = "rockchip,rk2928-pwm"; |
| reg = <0x20050030 0x10>; |
| #pwm-cells = <2>; |
| clocks = <&cru PCLK_PWM23>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@20056000 { |
| compatible = "rockchip,rk3066-i2c"; |
| reg = <0x20056000 0x1000>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clocks = <&cru PCLK_I2C2>; |
| clock-names = "i2c"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@2005a000 { |
| compatible = "rockchip,rk3066-i2c"; |
| reg = <0x2005a000 0x1000>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clocks = <&cru PCLK_I2C3>; |
| clock-names = "i2c"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@2005e000 { |
| compatible = "rockchip,rk3066-i2c"; |
| reg = <0x2005e000 0x1000>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| rockchip,grf = <&grf>; |
| |
| clocks = <&cru PCLK_I2C4>; |
| clock-names = "i2c"; |
| |
| status = "disabled"; |
| }; |
| |
| uart2: serial@20064000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x20064000 0x400>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <1>; |
| clock-names = "baudclk", "apb_pclk"; |
| clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@20068000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x20068000 0x400>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <1>; |
| clock-names = "baudclk", "apb_pclk"; |
| clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; |
| status = "disabled"; |
| }; |
| |
| saradc: saradc@2006c000 { |
| compatible = "rockchip,saradc"; |
| reg = <0x2006c000 0x100>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| #io-channel-cells = <1>; |
| clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; |
| clock-names = "saradc", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@20070000 { |
| compatible = "rockchip,rk3066-spi"; |
| clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; |
| clock-names = "spiclk", "apb_pclk"; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x20070000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&dmac2 10>, <&dmac2 11>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@20074000 { |
| compatible = "rockchip,rk3066-spi"; |
| clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; |
| clock-names = "spiclk", "apb_pclk"; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x20074000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&dmac2 12>, <&dmac2 13>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| }; |
